Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	139050	1			T32	4		T33	49		T34	7
values[2]	9388	1			T33	1		T104	189		T187	2
values[3]	3803	1			T104	74		T360	51		T359	1
values[4]	2067	1			T104	43		T360	11		T730	7
values[5]	1381	1			T104	67		T360	7		T730	10
values[6]	902	1			T104	29		T360	7		T730	5
values[7]	733	1			T104	21		T360	3		T730	5
values[8]	575	1			T104	9		T730	5		T731	12
values[9]	498	1			T104	6		T730	1		T731	2
values[10]	356	1			T730	5		T732	1		T387	7
values[11]	335	1			T730	2		T732	1		T387	5
values[12]	335	1			T730	3		T732	1		T387	4
values[13]	325	1			T730	5		T732	1		T387	8
values[14]	281	1			T730	4		T732	1		T387	8
values[15]	294	1			T730	8		T732	1		T387	8
values[16]	321	1			T730	5		T732	1		T387	8
values[17]	239	1			T730	1		T732	1		T387	13
values[18]	241	1			T730	5		T732	1		T387	12
values[19]	243	1			T730	4		T732	1		T387	10
values[20]	259	1			T730	6		T732	1		T387	8
values[21]	252	1			T730	2		T732	1		T387	6
values[22]	242	1			T730	1		T732	1		T387	3
values[23]	295	1			T730	2		T732	1		T387	10
values[24]	266	1			T730	4		T732	1		T387	21
values[25]	267	1			T730	2		T732	1		T387	11
values[26]	259	1			T730	4		T732	1		T387	8
values[27]	280	1			T730	1		T732	1		T387	7
values[28]	269	1			T730	4		T732	1		T387	3
values[29]	221	1			T730	2		T732	1		T387	3
values[30]	230	1			T730	1		T732	1		T387	7
values[31]	215	1			T730	5		T732	1		T387	8
values[32]	240	1			T730	2		T732	1		T387	7
values[33]	185	1			T730	1		T732	1		T387	4
values[34]	193	1			T730	2		T732	1		T387	3
values[35]	234	1			T730	1		T732	1		T387	6
values[36]	210	1			T730	2		T732	1		T387	7
values[37]	217	1			T730	4		T732	1		T387	3
values[38]	240	1			T730	11		T732	1		T387	7
values[39]	203	1			T730	6		T732	1		T387	8
values[40]	220	1			T730	3		T732	1		T387	7
values[41]	240	1			T730	1		T732	1		T387	15
values[42]	244	1			T730	3		T732	1		T387	8
values[43]	201	1			T730	3		T732	1		T387	6
values[44]	191	1			T730	3		T732	1		T387	2
values[45]	226	1			T730	3		T732	1		T577	10
values[46]	181	1			T730	1		T732	1		T577	9
values[47]	241	1			T730	2		T732	1		T577	8
values[48]	197	1			T730	2		T732	1		T577	5
values[49]	186	1			T730	1		T732	1		T577	9
values[50]	214	1			T730	4		T732	1		T577	17
values[51]	173	1			T730	3		T732	1		T577	9
values[52]	144	1			T730	1		T732	1		T577	11
values[53]	190	1			T730	3		T732	1		T577	12
values[54]	170	1			T730	6		T732	1		T577	8
values[55]	179	1			T730	4		T732	1		T577	8
values[56]	151	1			T730	1		T732	1		T577	3
values[57]	183	1			T730	5		T732	1		T577	6
values[58]	165	1			T730	2		T732	1		T577	5
values[59]	175	1			T730	2		T732	1		T577	4
values[60]	166	1			T730	10		T732	1		T577	4
values[61]	168	1			T730	6		T732	1		T577	3
values[62]	153	1			T730	7		T732	1		T577	3
values[63]	189	1			T730	6		T732	1		T577	6
values[64]	156	1			T730	2		T732	1		T577	5
values[65]	117	1			T730	2		T732	1		T577	3
values[66]	134	1			T730	2		T732	1		T577	7
values[67]	128	1			T730	1		T732	1		T577	7
values[68]	109	1			T730	2		T732	1		T577	9
values[69]	102	1			T730	2		T732	1		T577	6
values[70]	109	1			T730	1		T732	1		T577	6
values[71]	103	1			T730	2		T732	1		T577	11
values[72]	119	1			T730	3		T732	1		T577	11
values[73]	110	1			T730	2		T732	1		T733	1
values[74]	90	1			T730	1		T732	1		T733	1
values[75]	97	1			T730	1		T732	1		T733	1
values[76]	107	1			T730	5		T732	1		T733	1
values[77]	110	1			T730	6		T732	1		T733	1
values[78]	80	1			T730	4		T732	1		T733	1
values[79]	99	1			T730	2		T732	1		T733	1
values[80]	121	1			T730	3		T732	1		T733	1
values[81]	92	1			T730	2		T732	1		T733	1
values[82]	87	1			T730	1		T732	1		T733	1
values[83]	101	1			T730	1		T732	1		T733	1
values[84]	83	1			T730	1		T732	1		T733	1
values[85]	94	1			T730	2		T732	1		T733	1
values[86]	96	1			T730	1		T732	1		T733	1
values[87]	125	1			T730	2		T732	1		T733	1
values[88]	127	1			T730	6		T732	1		T733	1
values[89]	108	1			T730	4		T732	1		T733	1
values[90]	91	1			T730	4		T732	1		T733	1
values[91]	90	1			T730	9		T732	1		T733	1
values[92]	71	1			T730	5		T732	1		T733	1
values[93]	91	1			T730	3		T732	1		T733	1
values[94]	81	1			T730	6		T732	1		T733	1
values[95]	87	1			T730	3		T732	1		T733	1
values[96]	103	1			T730	5		T732	1		T733	1
values[97]	85	1			T730	5		T732	1		T733	1
values[98]	83	1			T730	2		T732	1		T733	1
values[99]	92	1			T730	2		T732	1		T733	1
values[100]	97	1			T730	3		T732	1		T733	1
values[101]	83	1			T730	3		T732	1		T733	1
values[102]	83	1			T730	1		T732	1		T733	1
values[103]	70	1			T730	8		T732	2		T733	1
values[104]	53	1			T730	1		T732	1		T733	1
values[105]	56	1			T730	1		T732	1		T733	1
values[106]	75	1			T730	2		T732	1		T733	1
values[107]	64	1			T730	2		T732	2		T733	2
values[108]	65	1			T730	1		T732	5		T733	1
values[109]	74	1			T730	2		T732	2		T733	1
values[110]	77	1			T730	1		T732	1		T733	6
values[111]	64	1			T730	4		T732	1		T733	3
values[112]	77	1			T730	1		T732	3		T733	4
values[113]	84	1			T730	2		T732	4		T733	4
values[114]	60	1			T730	2		T732	1		T733	1
values[115]	64	1			T730	2		T732	1		T733	1
values[116]	62	1			T730	2		T732	1		T733	1
values[117]	56	1			T730	2		T732	3		T733	1
values[118]	63	1			T730	3		T732	2		T733	2
values[119]	86	1			T730	5		T732	9		T733	2
values[120]	74	1			T730	6		T732	1		T733	2
values[121]	59	1			T730	3		T732	2		T733	2
values[122]	62	1			T730	2		T732	3		T733	1
values[123]	72	1			T730	5		T732	3		T733	1
values[124]	67	1			T730	7		T732	1		T733	3
values[125]	105	1			T730	21		T732	2		T733	1
values[126]	164	1			T730	29		T732	4		T733	6
values[127]	630	1			T730	66		T732	27		T733	37
values[128]	4148	1			T730	29		T732	253		T733	303

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	156374	1			T32	4		T33	63		T34	4
values[2]	4026	1			T33	4		T104	1		T370	3
values[3]	2052	1			T359	1		T432	64		T552	1
values[4]	1648	1			T432	56		T552	1		T569	26
values[5]	1481	1			T432	38		T569	46		T734	1
values[6]	1249	1			T432	35		T569	31		T734	1
values[7]	1048	1			T432	53		T569	12		T734	1
values[8]	874	1			T432	32		T569	4		T734	1
values[9]	789	1			T432	25		T569	7		T734	1
values[10]	761	1			T432	26		T569	7		T734	1
values[11]	762	1			T432	43		T734	1		T732	1
values[12]	616	1			T432	32		T734	1		T732	1
values[13]	631	1			T432	18		T734	1		T732	1
values[14]	522	1			T432	5		T734	1		T732	1
values[15]	412	1			T432	2		T734	1		T732	1
values[16]	405	1			T734	1		T732	1		T400	1
values[17]	449	1			T734	1		T732	1		T400	1
values[18]	388	1			T734	1		T732	1		T400	1
values[19]	377	1			T734	1		T732	1		T400	1
values[20]	387	1			T734	1		T732	1		T400	1
values[21]	355	1			T734	1		T732	1		T400	1
values[22]	352	1			T734	1		T732	1		T400	1
values[23]	329	1			T734	1		T732	1		T400	1
values[24]	227	1			T734	1		T732	1		T400	1
values[25]	240	1			T734	1		T732	1		T400	1
values[26]	246	1			T734	1		T732	1		T400	1
values[27]	194	1			T734	1		T732	1		T400	1
values[28]	171	1			T734	1		T732	1		T400	1
values[29]	177	1			T734	1		T732	1		T400	1
values[30]	156	1			T734	1		T732	1		T400	1
values[31]	124	1			T734	1		T732	1		T400	1
values[32]	101	1			T734	1		T732	1		T400	1
values[33]	97	1			T734	1		T732	1		T400	1
values[34]	105	1			T734	1		T732	1		T400	1
values[35]	97	1			T734	1		T732	1		T400	1
values[36]	98	1			T734	1		T732	1		T400	1
values[37]	101	1			T734	1		T732	1		T400	1
values[38]	114	1			T734	1		T732	1		T400	1
values[39]	131	1			T734	1		T732	1		T400	1
values[40]	132	1			T734	1		T732	1		T400	1
values[41]	117	1			T734	1		T732	1		T400	1
values[42]	96	1			T734	1		T732	1		T400	1
values[43]	81	1			T734	1		T732	1		T400	1
values[44]	77	1			T734	1		T732	1		T400	1
values[45]	88	1			T734	1		T732	1		T400	1
values[46]	92	1			T734	1		T732	1		T400	1
values[47]	85	1			T734	1		T732	1		T400	1
values[48]	112	1			T734	1		T732	1		T400	1
values[49]	104	1			T734	1		T732	1		T400	1
values[50]	81	1			T734	1		T732	1		T400	1
values[51]	79	1			T734	1		T732	1		T400	1
values[52]	59	1			T734	1		T732	1		T400	1
values[53]	62	1			T734	1		T732	1		T400	1
values[54]	67	1			T734	1		T732	1		T400	1
values[55]	63	1			T734	1		T732	1		T400	1
values[56]	62	1			T734	1		T732	1		T400	1
values[57]	91	1			T734	1		T732	1		T400	1
values[58]	77	1			T734	1		T732	1		T400	1
values[59]	88	1			T734	1		T732	1		T400	1
values[60]	69	1			T734	1		T732	1		T400	1
values[61]	60	1			T734	1		T732	1		T400	1
values[62]	59	1			T734	1		T732	1		T400	1
values[63]	41	1			T734	1		T732	1		T400	1
values[64]	46	1			T734	1		T732	1		T400	1
values[65]	47	1			T734	1		T732	1		T400	1
values[66]	49	1			T734	1		T732	1		T400	1
values[67]	61	1			T734	1		T732	1		T400	1
values[68]	48	1			T734	1		T732	1		T400	1
values[69]	42	1			T734	1		T732	1		T400	1
values[70]	48	1			T734	1		T732	1		T400	1
values[71]	53	1			T734	1		T732	1		T400	1
values[72]	64	1			T734	2		T732	1		T400	1
values[73]	56	1			T734	1		T732	1		T400	1
values[74]	57	1			T734	1		T732	1		T400	1
values[75]	61	1			T734	1		T732	1		T400	1
values[76]	70	1			T734	3		T732	1		T400	1
values[77]	90	1			T734	5		T732	1		T400	1
values[78]	69	1			T734	5		T732	1		T400	1
values[79]	71	1			T734	6		T732	1		T400	1
values[80]	62	1			T734	5		T732	1		T400	1
values[81]	70	1			T734	3		T732	1		T400	1
values[82]	83	1			T734	6		T732	1		T400	1
values[83]	90	1			T734	1		T732	1		T400	1
values[84]	69	1			T734	2		T732	1		T400	1
values[85]	67	1			T734	1		T732	1		T400	1
values[86]	88	1			T734	2		T732	1		T400	1
values[87]	85	1			T734	2		T732	1		T400	1
values[88]	80	1			T734	5		T732	1		T400	1
values[89]	84	1			T734	3		T732	1		T400	1
values[90]	80	1			T734	4		T732	1		T400	1
values[91]	90	1			T734	2		T732	1		T400	1
values[92]	68	1			T734	2		T732	1		T400	1
values[93]	76	1			T734	2		T732	1		T400	1
values[94]	98	1			T734	5		T732	1		T400	1
values[95]	86	1			T734	4		T732	1		T400	1
values[96]	82	1			T734	1		T732	1		T400	1
values[97]	93	1			T734	8		T732	1		T400	1
values[98]	74	1			T734	1		T732	1		T400	1
values[99]	79	1			T734	1		T732	1		T400	1
values[100]	96	1			T734	1		T732	1		T400	1
values[101]	77	1			T734	2		T732	1		T400	1
values[102]	83	1			T734	5		T732	1		T400	1
values[103]	80	1			T734	2		T732	1		T400	1
values[104]	75	1			T734	2		T732	1		T400	1
values[105]	85	1			T734	5		T732	1		T400	1
values[106]	77	1			T734	4		T732	1		T400	1
values[107]	70	1			T734	2		T732	1		T400	1
values[108]	70	1			T734	1		T732	1		T400	1
values[109]	84	1			T734	2		T732	1		T400	2
values[110]	79	1			T734	5		T732	1		T400	3
values[111]	82	1			T734	3		T732	1		T400	2
values[112]	86	1			T734	2		T732	1		T400	1
values[113]	78	1			T734	1		T732	1		T400	1
values[114]	87	1			T734	1		T732	1		T400	2
values[115]	90	1			T734	1		T732	1		T400	1
values[116]	87	1			T734	4		T732	1		T400	2
values[117]	79	1			T734	1		T732	1		T400	3
values[118]	92	1			T734	2		T732	1		T400	2
values[119]	98	1			T734	2		T732	1		T400	2
values[120]	104	1			T734	2		T732	1		T400	2
values[121]	80	1			T734	1		T732	1		T400	1
values[122]	81	1			T734	2		T732	1		T400	3
values[123]	133	1			T734	3		T732	1		T400	2
values[124]	223	1			T734	3		T732	1		T400	1
values[125]	348	1			T734	1		T732	1		T400	3
values[126]	581	1			T734	15		T732	17		T400	21
values[127]	2179	1			T734	83		T732	140		T400	148
values[128]	3860	1			T734	159		T732	220		T400	267

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	142251	1			T32	10		T33	63		T34	9
values[2]	10314	1			T33	2		T104	1		T187	3
values[3]	3760	1			T360	42		T359	1		T348	259
values[4]	2248	1			T360	10		T348	125		T432	2
values[5]	1341	1			T360	2		T348	45		T432	2
values[6]	825	1			T348	14		T432	1		T573	2
values[7]	485	1			T432	2		T543	8		T735	1
values[8]	366	1			T432	1		T543	3		T735	1
values[9]	332	1			T432	3		T543	8		T735	1
values[10]	276	1			T432	4		T543	5		T735	1
values[11]	294	1			T432	7		T543	4		T735	1
values[12]	280	1			T432	5		T543	9		T735	1
values[13]	230	1			T432	2		T543	22		T735	1
values[14]	228	1			T432	1		T543	3		T735	1
values[15]	259	1			T432	3		T543	3		T735	1
values[16]	243	1			T432	3		T543	11		T735	1
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