Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.41	95.44	94.71	95.74		95.42	97.57	99.57

Total tests in report: 2857

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
32.68	32.68	51.16	51.16	37.91	37.91	39.02	39.02			46.08	46.08	20.93	20.93	0.96	0.96	/workspace/coverage/cover_reg_top/7.chip_tl_errors.3771500955
48.70	16.02	60.03	8.88	60.55	22.64	52.05	13.04			66.37	20.29	49.26	28.33	3.92	2.96	/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3841364985
63.87	15.17	71.68	11.65	79.07	18.52	58.17	6.12			84.47	18.10	85.93	36.67	3.92	0.00	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2961579025
70.06	6.19	82.08	10.39	81.87	2.80	63.78	5.61			84.62	0.15	85.93	0.00	22.09	18.17	/workspace/coverage/cover_reg_top/60.xbar_stress_all.1274384409
74.11	4.05	82.08	0.00	82.01	0.13	63.78	0.00			84.67	0.05	85.93	0.00	46.23	24.14	/workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1196411893
77.12	3.01	84.14	2.07	82.68	0.67	73.24	9.46			85.28	0.62	91.11	5.19	46.27	0.05	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3739305185
79.52	2.40	84.14	0.00	82.68	0.00	73.24	0.00			85.28	0.00	91.11	0.00	60.68	14.41	/workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.1790614626
81.26	1.73	89.37	5.23	84.96	2.28	73.55	0.31			87.86	2.58	91.11	0.00	60.68	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.2400722562
82.95	1.69	89.37	0.00	84.99	0.03	73.55	0.00			87.86	0.00	91.11	0.00	70.82	10.14	/workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.1402502617
84.17	1.22	89.37	0.00	84.99	0.00	73.55	0.00			87.86	0.00	91.11	0.00	78.16	7.33	/workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.209784739
85.32	1.15	89.44	0.06	84.99	0.00	80.19	6.63			87.86	0.00	91.30	0.19	78.16	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1337518022
86.30	0.98	90.15	0.72	87.49	2.50	80.21	0.03			90.50	2.64	91.30	0.00	78.16	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.4190348141
87.16	0.86	90.90	0.75	87.64	0.15	80.23	0.02			90.66	0.17	95.37	4.07	78.16	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3514630487
87.92	0.76	90.90	0.00	87.64	0.00	84.76	4.53			90.66	0.00	95.37	0.00	78.16	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.981658239
88.65	0.73	90.90	0.00	87.68	0.03	84.76	0.00			90.66	0.00	95.37	0.00	82.53	4.37	/workspace/coverage/cover_reg_top/16.xbar_stress_all.1060077858
89.30	0.65	90.90	0.00	87.68	0.00	84.76	0.00			90.66	0.00	95.37	0.00	86.45	3.92	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.1211955650
89.92	0.62	92.13	1.23	88.73	1.06	84.99	0.23			91.87	1.20	95.37	0.00	86.45	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.3440981426
90.49	0.56	92.95	0.82	89.90	1.17	85.03	0.04			93.22	1.35	95.37	0.00	86.45	0.00	/workspace/coverage/default/1.chip_jtag_csr_rw.2518427558
91.00	0.52	92.96	0.01	89.91	0.01	87.92	2.89			93.22	0.00	95.56	0.19	86.45	0.00	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.30989975
91.46	0.45	92.96	0.01	89.97	0.07	88.47	0.55			93.23	0.01	95.56	0.00	88.54	2.09	/workspace/coverage/cover_reg_top/34.xbar_error_random.361933736
91.88	0.43	92.96	0.00	89.97	0.00	88.47	0.00			93.23	0.00	95.56	0.00	91.10	2.56	/workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.301078877
92.30	0.42	92.96	0.00	90.01	0.04	88.47	0.00			93.23	0.00	95.56	0.00	93.60	2.49	/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.1917095528
92.69	0.38	93.12	0.16	90.17	0.15	90.22	1.75			93.28	0.06	95.74	0.19	93.60	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2836140392
93.04	0.35	93.12	0.00	90.17	0.00	90.22	0.00			93.28	0.00	95.74	0.00	95.70	2.10	/workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.1384063657
93.32	0.28	93.55	0.43	90.67	0.50	90.68	0.46			93.56	0.28	95.74	0.00	95.70	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2072971638
93.53	0.21	94.00	0.45	91.03	0.37	90.78	0.09			93.91	0.35	95.74	0.00	95.70	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.3628800485
93.73	0.21	94.20	0.21	91.51	0.47	90.81	0.04			94.43	0.52	95.74	0.00	95.70	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.3191295174
93.91	0.18	94.38	0.17	91.69	0.18	90.83	0.01			94.55	0.13	96.30	0.56	95.70	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1468127954
94.05	0.14	94.41	0.03	91.76	0.07	91.40	0.57			94.73	0.18	96.30	0.00	95.70	0.00	/workspace/coverage/default/1.rom_raw_unlock.454847092
94.19	0.14	94.41	0.00	92.59	0.83	91.40	0.00			94.73	0.00	96.30	0.00	95.71	0.01	/workspace/coverage/cover_reg_top/0.chip_tl_errors.253012645
94.32	0.13	94.41	0.00	92.60	0.01	91.40	0.00			94.73	0.00	96.30	0.00	96.49	0.78	/workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.4114300348
94.44	0.12	94.41	0.00	92.61	0.01	91.40	0.00			94.73	0.00	96.30	0.00	97.23	0.74	/workspace/coverage/cover_reg_top/65.xbar_random_large_delays.2928455553
94.56	0.12	94.41	0.01	92.61	0.00	92.08	0.68			94.73	0.00	96.30	0.00	97.25	0.02	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3416264276
94.66	0.10	94.41	0.00	92.61	0.00	92.69	0.61			94.73	0.00	96.30	0.00	97.25	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.319398176
94.76	0.10	94.41	0.01	92.62	0.01	93.05	0.36			94.74	0.01	96.48	0.19	97.26	0.01	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.702362349
94.85	0.09	94.41	0.00	92.62	0.01	93.59	0.53			94.74	0.00	96.48	0.00	97.26	0.00	/workspace/coverage/default/1.chip_sw_all_escalation_resets.2177167518
94.94	0.09	94.41	0.00	92.87	0.25	93.59	0.00			95.02	0.28	96.48	0.00	97.26	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2300893552
95.02	0.08	94.41	0.00	92.87	0.00	94.06	0.47			95.02	0.00	96.48	0.00	97.26	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.125488893
95.09	0.07	94.41	0.00	92.87	0.00	94.06	0.00			95.02	0.00	96.48	0.00	97.70	0.43	/workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.3887335844
95.15	0.06	94.42	0.01	92.88	0.01	94.25	0.19			95.02	0.00	96.67	0.19	97.70	0.00	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2833516750
95.21	0.06	94.42	0.00	93.24	0.36	94.25	0.00			95.02	0.00	96.67	0.00	97.70	0.00	/workspace/coverage/cover_reg_top/5.chip_tl_errors.3568772130
95.27	0.06	94.43	0.01	93.43	0.19	94.36	0.11			95.04	0.02	96.67	0.00	97.72	0.02	/workspace/coverage/cover_reg_top/17.chip_csr_rw.3457095851
95.32	0.04	94.43	0.00	93.44	0.01	94.36	0.00			95.04	0.00	96.67	0.00	97.97	0.25	/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.1734299154
95.36	0.04	94.60	0.17	93.52	0.08	94.36	0.01			95.04	0.00	96.67	0.00	97.97	0.00	/workspace/coverage/default/1.chip_sw_gpio.3042120550
95.40	0.04	94.61	0.01	93.54	0.01	94.36	0.00			95.06	0.03	96.85	0.19	97.98	0.01	/workspace/coverage/default/32.chip_sw_all_escalation_resets.940058105
95.44	0.04	94.64	0.03	93.54	0.01	94.36	0.01			95.07	0.01	97.04	0.19	97.99	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.403246350
95.48	0.04	94.65	0.01	93.56	0.01	94.36	0.00			95.08	0.01	97.22	0.19	98.00	0.01	/workspace/coverage/default/3.chip_sw_all_escalation_resets.2049793161
95.52	0.04	94.65	0.01	93.57	0.01	94.37	0.01			95.09	0.01	97.41	0.19	98.01	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.2034450857
95.55	0.04	94.65	0.00	93.67	0.10	94.37	0.00			95.20	0.12	97.41	0.00	98.01	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.215637424
95.59	0.04	94.65	0.00	93.67	0.01	94.37	0.00			95.20	0.00	97.41	0.00	98.23	0.21	/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.465416444
95.62	0.04	94.65	0.00	93.67	0.00	94.58	0.21			95.20	0.00	97.41	0.00	98.23	0.00	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2389409609
95.66	0.03	94.65	0.00	93.67	0.00	94.59	0.01			95.20	0.00	97.59	0.19	98.23	0.00	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.673423855
95.69	0.03	94.69	0.04	93.72	0.04	94.68	0.09			95.21	0.01	97.59	0.00	98.23	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.74118451
95.72	0.03	94.74	0.04	93.72	0.00	94.81	0.13			95.21	0.00	97.59	0.00	98.23	0.00	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.1856492492
95.74	0.03	94.74	0.00	93.72	0.00	94.98	0.17			95.21	0.00	97.59	0.00	98.23	0.00	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3400445398
95.77	0.03	94.74	0.00	93.72	0.00	95.14	0.16			95.21	0.00	97.59	0.00	98.23	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1991981094
95.80	0.03	94.80	0.07	93.75	0.04	95.14	0.00			95.26	0.05	97.59	0.00	98.23	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3948676098
95.82	0.03	94.80	0.00	93.89	0.14	95.14	0.00			95.26	0.00	97.59	0.00	98.24	0.01	/workspace/coverage/cover_reg_top/2.chip_tl_errors.3127892917
95.85	0.02	94.84	0.04	93.92	0.03	95.16	0.02			95.32	0.06	97.59	0.00	98.24	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3647389293
95.87	0.02	94.92	0.08	93.92	0.00	95.21	0.04			95.33	0.01	97.59	0.00	98.24	0.00	/workspace/coverage/default/0.chip_tap_straps_testunlock0.417834967
95.89	0.02	94.92	0.00	93.94	0.02	95.30	0.09			95.34	0.01	97.59	0.00	98.24	0.00	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.464964605
95.90	0.02	94.92	0.00	94.04	0.10	95.30	0.00			95.34	0.00	97.59	0.00	98.24	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.2283858943
95.92	0.02	94.92	0.00	94.04	0.00	95.30	0.00			95.34	0.00	97.59	0.00	98.33	0.09	/workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.1964129264
95.93	0.01	94.92	0.00	94.04	0.00	95.37	0.08			95.34	0.00	97.59	0.00	98.33	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.315363332
95.94	0.01	94.92	0.00	94.05	0.01	95.37	0.00			95.34	0.00	97.59	0.00	98.40	0.07	/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.3079264989
95.96	0.01	94.92	0.00	94.05	0.00	95.37	0.00			95.34	0.00	97.59	0.00	98.47	0.07	/workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.64969794
95.97	0.01	94.95	0.04	94.07	0.02	95.37	0.00			95.34	0.01	97.59	0.00	98.47	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1250100586
95.98	0.01	94.99	0.04	94.09	0.02	95.37	0.00			95.35	0.01	97.59	0.00	98.47	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2326166408
95.99	0.01	95.03	0.04	94.11	0.02	95.37	0.00			95.36	0.01	97.59	0.00	98.47	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1896112684
96.00	0.01	95.03	0.00	94.16	0.05	95.37	0.00			95.36	0.00	97.59	0.00	98.48	0.01	/workspace/coverage/cover_reg_top/28.chip_tl_errors.2605701370
96.01	0.01	95.03	0.00	94.22	0.06	95.37	0.00			95.36	0.00	97.59	0.00	98.48	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1113884518
96.02	0.01	95.03	0.00	94.22	0.00	95.37	0.00			95.36	0.00	97.59	0.00	98.54	0.06	/workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.4093799748
96.03	0.01	95.03	0.00	94.22	0.00	95.37	0.00			95.36	0.00	97.59	0.00	98.60	0.06	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.2978180401
96.04	0.01	95.05	0.03	94.24	0.01	95.37	0.00			95.38	0.02	97.59	0.00	98.60	0.00	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.352878154
96.05	0.01	95.05	0.01	94.25	0.01	95.40	0.03			95.39	0.01	97.59	0.00	98.60	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.2441364050
96.06	0.01	95.08	0.02	94.26	0.01	95.40	0.00			95.40	0.02	97.59	0.00	98.60	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2136109702
96.06	0.01	95.08	0.01	94.30	0.04	95.40	0.00			95.40	0.00	97.59	0.00	98.60	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_rw.2135018062
96.07	0.01	95.08	0.00	94.30	0.00	95.40	0.00			95.40	0.00	97.59	0.00	98.65	0.05	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2945183977
96.08	0.01	95.08	0.00	94.30	0.00	95.40	0.00			95.40	0.00	97.59	0.00	98.70	0.05	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2039684853
96.09	0.01	95.08	0.00	94.35	0.04	95.40	0.00			95.40	0.00	97.59	0.00	98.70	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.3196745908
96.09	0.01	95.08	0.00	94.39	0.04	95.40	0.00			95.40	0.00	97.59	0.00	98.70	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2449616065
96.10	0.01	95.08	0.00	94.39	0.00	95.45	0.04			95.40	0.00	97.59	0.00	98.70	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.971498707
96.11	0.01	95.08	0.01	94.40	0.01	95.46	0.02			95.40	0.00	97.59	0.00	98.71	0.01	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1507528445
96.11	0.01	95.11	0.02	94.40	0.00	95.47	0.01			95.40	0.00	97.59	0.00	98.71	0.00	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1355096496
96.12	0.01	95.11	0.00	94.42	0.03	95.47	0.00			95.40	0.00	97.59	0.00	98.71	0.00	/workspace/coverage/cover_reg_top/15.chip_tl_errors.611238898
96.12	0.01	95.11	0.00	94.45	0.03	95.47	0.00			95.40	0.00	97.59	0.00	98.71	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.4101275827
96.13	0.01	95.11	0.00	94.45	0.00	95.50	0.03			95.40	0.00	97.59	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4192578314
96.13	0.01	95.11	0.00	94.45	0.00	95.53	0.03			95.40	0.00	97.59	0.00	98.71	0.00	/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2278788261
96.14	0.01	95.11	0.00	94.45	0.00	95.55	0.02			95.40	0.00	97.59	0.00	98.72	0.01	/workspace/coverage/default/42.chip_sw_all_escalation_resets.2262830773
96.14	0.01	95.11	0.00	94.48	0.03	95.55	0.00			95.40	0.00	97.59	0.00	98.72	0.00	/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.2481350046
96.15	0.01	95.11	0.00	94.51	0.03	95.55	0.00			95.40	0.00	97.59	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.3933072452
96.15	0.01	95.11	0.00	94.53	0.03	95.55	0.00			95.40	0.00	97.59	0.00	98.72	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.1627322667
96.15	0.01	95.11	0.01	94.54	0.01	95.56	0.01			95.40	0.00	97.59	0.00	98.72	0.00	/workspace/coverage/default/1.rom_e2e_shutdown_output.2011548169
96.16	0.01	95.11	0.00	94.54	0.00	95.56	0.00			95.40	0.00	97.59	0.00	98.74	0.02	/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.3075586090
96.16	0.01	95.11	0.00	94.54	0.00	95.56	0.00			95.40	0.00	97.59	0.00	98.77	0.02	/workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.437178781
96.16	0.01	95.11	0.00	94.55	0.01	95.56	0.00			95.40	0.00	97.59	0.00	98.78	0.01	/workspace/coverage/cover_reg_top/54.xbar_stress_all.2049197212
96.17	0.01	95.11	0.00	94.55	0.00	95.57	0.02			95.40	0.00	97.59	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_flash_init.2311853331
96.17	0.01	95.11	0.00	94.55	0.00	95.59	0.02			95.40	0.00	97.59	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4010780513
96.17	0.01	95.11	0.00	94.55	0.00	95.60	0.01			95.40	0.00	97.59	0.00	98.79	0.01	/workspace/coverage/default/77.chip_sw_all_escalation_resets.2645683822
96.18	0.01	95.11	0.00	94.57	0.02	95.60	0.00			95.40	0.00	97.59	0.00	98.79	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx.1508642622
96.18	0.01	95.11	0.01	94.58	0.01	95.60	0.00			95.40	0.00	97.59	0.00	98.79	0.00	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.225000892
96.18	0.01	95.12	0.01	94.60	0.01	95.60	0.00			95.40	0.00	97.59	0.00	98.79	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2484531585
96.19	0.01	95.13	0.01	94.60	0.01	95.60	0.00			95.40	0.00	97.59	0.00	98.79	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.3989889427
96.19	0.01	95.13	0.00	94.61	0.01	95.61	0.01			95.40	0.00	97.59	0.00	98.79	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2669405157
96.19	0.01	95.13	0.00	94.61	0.01	95.61	0.00			95.40	0.00	97.59	0.00	98.80	0.01	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.2781380330
96.19	0.01	95.13	0.00	94.63	0.01	95.61	0.00			95.40	0.00	97.59	0.00	98.80	0.00	/workspace/coverage/cover_reg_top/12.chip_tl_errors.3003451115
96.20	0.01	95.14	0.01	94.63	0.00	95.61	0.01			95.40	0.00	97.59	0.00	98.80	0.00	/workspace/coverage/default/12.chip_sw_all_escalation_resets.4279489241
96.20	0.01	95.14	0.00	94.63	0.00	95.63	0.01			95.40	0.00	97.59	0.00	98.80	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1450117290
96.20	0.01	95.14	0.00	94.64	0.01	95.63	0.01			95.40	0.00	97.59	0.00	98.80	0.00	/workspace/coverage/default/0.chip_sw_alert_test.1929009657
96.20	0.01	95.14	0.00	94.65	0.01	95.63	0.01			95.40	0.00	97.59	0.00	98.80	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.649997004
96.20	0.01	95.14	0.01	94.65	0.00	95.64	0.01			95.40	0.00	97.59	0.00	98.80	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.985727221
96.21	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	98.81	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.238692751
96.21	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	98.82	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.4028830483
96.21	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	98.84	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.4078832124
96.21	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	98.85	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.4041639094
96.21	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	98.86	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2434872195
96.22	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	98.87	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1123894634
96.22	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	98.88	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3766301830
96.22	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	98.90	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.522064293
96.22	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	98.91	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2596838915
96.22	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	98.92	0.01	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3918462383
96.23	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	98.93	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.3163814860
96.23	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	98.94	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.224363724
96.23	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	98.95	0.01	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3970970273
96.23	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	98.97	0.01	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2001412086
96.23	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	98.98	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.807995949
96.24	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	98.99	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.4144062546
96.24	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.00	0.01	/workspace/coverage/default/2.chip_sw_all_escalation_resets.3141321084
96.24	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.01	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.508759103
96.24	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.02	0.01	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1440613243
96.24	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.04	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.4279726230
96.25	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.05	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.4080276507
96.25	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.06	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.695250831
96.25	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.07	0.01	/workspace/coverage/default/23.chip_sw_all_escalation_resets.668004394
96.25	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.08	0.01	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.54863832
96.25	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.10	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1349859148
96.26	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.11	0.01	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.794470506
96.26	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.12	0.01	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3128242288
96.26	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.13	0.01	/workspace/coverage/default/31.chip_sw_all_escalation_resets.4137367982
96.26	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.14	0.01	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2953072101
96.26	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.15	0.01	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1719170178
96.27	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.17	0.01	/workspace/coverage/default/35.chip_sw_all_escalation_resets.131450711
96.27	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.18	0.01	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1308687715
96.27	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.19	0.01	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.4167384727
96.27	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.20	0.01	/workspace/coverage/default/38.chip_sw_all_escalation_resets.3781382792
96.27	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.21	0.01	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1653077717
96.28	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.22	0.01	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3546751509
96.28	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.24	0.01	/workspace/coverage/default/40.chip_sw_all_escalation_resets.3299068174
96.28	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.25	0.01	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2576152099
96.28	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.26	0.01	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3034239825
96.28	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.27	0.01	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.4161282042
96.28	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.28	0.01	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.823160982
96.29	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.29	0.01	/workspace/coverage/default/46.chip_sw_all_escalation_resets.461076932
96.29	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.31	0.01	/workspace/coverage/default/47.chip_sw_all_escalation_resets.2102894583
96.29	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.32	0.01	/workspace/coverage/default/48.chip_sw_all_escalation_resets.257206043
96.29	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.33	0.01	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2125997905
96.29	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.34	0.01	/workspace/coverage/default/50.chip_sw_all_escalation_resets.901880778
96.30	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.35	0.01	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3297649333
96.30	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.37	0.01	/workspace/coverage/default/52.chip_sw_all_escalation_resets.1618398408
96.30	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.38	0.01	/workspace/coverage/default/53.chip_sw_all_escalation_resets.505064639
96.30	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.39	0.01	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.783674327
96.30	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.40	0.01	/workspace/coverage/default/57.chip_sw_all_escalation_resets.289522877
96.31	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.41	0.01	/workspace/coverage/default/59.chip_sw_all_escalation_resets.3795250900
96.31	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.42	0.01	/workspace/coverage/default/6.chip_sw_all_escalation_resets.1976195833
96.31	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.44	0.01	/workspace/coverage/default/61.chip_sw_all_escalation_resets.1713758045
96.31	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.45	0.01	/workspace/coverage/default/62.chip_sw_all_escalation_resets.836730582
96.31	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.46	0.01	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1849000813
96.32	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.47	0.01	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2122496866
96.32	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.48	0.01	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.4146964726
96.32	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.49	0.01	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.4238015859
96.32	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.51	0.01	/workspace/coverage/default/74.chip_sw_all_escalation_resets.1436704601
96.32	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.52	0.01	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1614535936
96.33	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.53	0.01	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1558093425
96.33	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.54	0.01	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.151653295
96.33	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.55	0.01	/workspace/coverage/default/87.chip_sw_all_escalation_resets.123219970
96.33	0.01	95.14	0.00	94.65	0.00	95.64	0.00			95.40	0.00	97.59	0.00	99.57	0.01	/workspace/coverage/default/89.chip_sw_all_escalation_resets.1204305850
96.33	0.01	95.14	0.00	94.66	0.01	95.64	0.00			95.40	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.2797366577
96.34	0.01	95.14	0.00	94.67	0.01	95.64	0.00			95.40	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sival_flash_info_access.3971806626
96.34	0.01	95.15	0.01	94.67	0.01	95.64	0.00			95.40	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.835186567
96.34	0.01	95.15	0.00	94.67	0.00	95.65	0.01			95.40	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3774785884
96.34	0.01	95.16	0.01	94.67	0.00	95.65	0.01			95.40	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.3928848130
96.34	0.01	95.16	0.01	94.67	0.00	95.66	0.01			95.40	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2937446061
96.34	0.01	95.16	0.00	94.67	0.00	95.67	0.01			95.40	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.673327447
96.35	0.01	95.16	0.00	94.67	0.00	95.68	0.01			95.40	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1379591497
96.35	0.01	95.16	0.00	94.67	0.00	95.68	0.00			95.41	0.01	97.59	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2948521477
96.35	0.01	95.16	0.00	94.67	0.00	95.68	0.00			95.42	0.01	97.59	0.00	99.57	0.00	/workspace/coverage/default/2.chip_tap_straps_dev.123886591
96.35	0.01	95.16	0.00	94.68	0.01	95.68	0.00			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.3617772180
96.35	0.01	95.16	0.00	94.69	0.01	95.68	0.00			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.487381526
96.35	0.01	95.17	0.01	94.69	0.00	95.68	0.00			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2185417993
96.35	0.01	95.18	0.01	94.69	0.00	95.68	0.00			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.451773182
96.35	0.01	95.18	0.00	94.69	0.00	95.68	0.01			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1313826961
96.36	0.01	95.18	0.00	94.69	0.00	95.69	0.01			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.19783162
96.36	0.01	95.18	0.00	94.69	0.00	95.69	0.01			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3102134123
96.36	0.01	95.18	0.00	94.69	0.00	95.70	0.01			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.246470339
96.36	0.01	95.18	0.00	94.69	0.00	95.70	0.01			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2657459060
96.36	0.01	95.18	0.00	94.69	0.00	95.71	0.01			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1263447652
96.36	0.01	95.18	0.00	94.69	0.00	95.71	0.01			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4191842974
96.36	0.01	95.18	0.00	94.69	0.00	95.72	0.01			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3585362062
96.36	0.01	95.18	0.00	94.69	0.00	95.72	0.01			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/2.chip_sw_flash_init.835709354
96.36	0.01	95.18	0.00	94.69	0.01	95.72	0.00			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/16.chip_tl_errors.2942461038
96.36	0.01	95.18	0.00	94.69	0.01	95.72	0.00			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/17.chip_tl_errors.2726952136
96.36	0.01	95.18	0.00	94.70	0.01	95.72	0.00			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.536674653
96.36	0.01	95.18	0.00	94.70	0.01	95.72	0.00			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.366464948
96.36	0.01	95.18	0.00	94.71	0.01	95.72	0.00			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2079550243
96.36	0.01	95.18	0.00	94.71	0.01	95.72	0.00			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/2.chip_jtag_csr_rw.6364367
96.36	0.01	95.18	0.00	94.71	0.01	95.72	0.00			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/2.chip_sw_gpio.2151445542
96.37	0.01	95.18	0.00	94.71	0.00	95.72	0.01			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.4021536846
96.37	0.01	95.18	0.00	94.71	0.00	95.73	0.01			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.710779715
96.37	0.01	95.18	0.00	94.71	0.00	95.73	0.01			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3620363039
96.37	0.01	95.18	0.00	94.71	0.00	95.73	0.01			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.2264848496
96.37	0.01	95.18	0.00	94.71	0.00	95.74	0.01			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_edn_auto_mode.500554273
96.37	0.01	95.18	0.00	94.71	0.00	95.74	0.01			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3276690121
96.37	0.01	95.18	0.00	94.71	0.00	95.74	0.01			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2969299467
96.37	0.01	95.18	0.00	94.71	0.00	95.74	0.01			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.706665821
96.37	0.01	95.18	0.00	94.71	0.00	95.74	0.01			95.42	0.00	97.59	0.00	99.57	0.00	/workspace/coverage/default/29.chip_sw_all_escalation_resets.746335861

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.550667292
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1654902088
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.439507932
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2061052644
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1493976673
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3111522907
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2825611821
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2168391868
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3264174436
/workspace/coverage/cover_reg_top/0.xbar_error_random.3992267277
/workspace/coverage/cover_reg_top/0.xbar_random.3697549481
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2793850658
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1182290746
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3539729441
/workspace/coverage/cover_reg_top/0.xbar_same_source.2820057771
/workspace/coverage/cover_reg_top/0.xbar_smoke.2889057658
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2423948336
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2063912837
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3379640421
/workspace/coverage/cover_reg_top/0.xbar_stress_all.3595034210
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2019070994
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1009220631
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1040554678
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3583781379
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.4107878231
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3649607128
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.2138030945
/workspace/coverage/cover_reg_top/1.chip_csr_rw.1344725002
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.1734288093
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2803588469
/workspace/coverage/cover_reg_top/1.chip_tl_errors.2728326637
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2757792790
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.584773888
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.498164041
/workspace/coverage/cover_reg_top/1.xbar_error_random.957031711
/workspace/coverage/cover_reg_top/1.xbar_random.2656753992
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.954199172
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.270200887
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1848186450
/workspace/coverage/cover_reg_top/1.xbar_same_source.90741239
/workspace/coverage/cover_reg_top/1.xbar_smoke.2738449037
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1237843151
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2181279484
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1422688628
/workspace/coverage/cover_reg_top/1.xbar_stress_all.5788601
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1246269546
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3270650485
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2347438759
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.885606053
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.2742468714
/workspace/coverage/cover_reg_top/10.chip_csr_rw.1319923685
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1991298108
/workspace/coverage/cover_reg_top/10.chip_tl_errors.1734952113
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1964512637
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3748247974
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.613332626
/workspace/coverage/cover_reg_top/10.xbar_error_random.3094834483
/workspace/coverage/cover_reg_top/10.xbar_random.4131254366
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1812919793
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3571620711
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3713585318
/workspace/coverage/cover_reg_top/10.xbar_same_source.182783601
/workspace/coverage/cover_reg_top/10.xbar_smoke.1287551422
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2845649831
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.797644147
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2475760819
/workspace/coverage/cover_reg_top/10.xbar_stress_all.1299111367
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2138794838
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3359435508
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1356848212
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1353331235
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.941610987
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2731149580
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.1749919347
/workspace/coverage/cover_reg_top/11.chip_tl_errors.1718024083
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.3123323665
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3204414333
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.4280383785
/workspace/coverage/cover_reg_top/11.xbar_error_random.770266741
/workspace/coverage/cover_reg_top/11.xbar_random.4067683975
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.4211707245
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.293341018
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3279420878
/workspace/coverage/cover_reg_top/11.xbar_same_source.1252464705
/workspace/coverage/cover_reg_top/11.xbar_smoke.1316607502
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1237501028
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.1478047039
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.333592661
/workspace/coverage/cover_reg_top/11.xbar_stress_all.1491066547
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2386471099
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2857238849
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2950775250
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.471179629
/workspace/coverage/cover_reg_top/12.chip_csr_rw.3988753057
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2789466285
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.2940556936
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.4211389281
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.4071587054
/workspace/coverage/cover_reg_top/12.xbar_error_random.15821607
/workspace/coverage/cover_reg_top/12.xbar_random.2665407883
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2364530249
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.4245246842
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.478317189
/workspace/coverage/cover_reg_top/12.xbar_same_source.2132966812
/workspace/coverage/cover_reg_top/12.xbar_smoke.1123228604
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.52459339
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1145009162
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3364844743
/workspace/coverage/cover_reg_top/12.xbar_stress_all.1650865510
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2075608243
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3056961523
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.207544079
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.19716820
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.1315627197
/workspace/coverage/cover_reg_top/13.chip_csr_rw.4236227624
/workspace/coverage/cover_reg_top/13.chip_tl_errors.3674933897
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.1883670735
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.302336359
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.974178511
/workspace/coverage/cover_reg_top/13.xbar_error_random.2663638497
/workspace/coverage/cover_reg_top/13.xbar_random.650527124
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2115186819
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2056768957
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3159509082
/workspace/coverage/cover_reg_top/13.xbar_same_source.2049641071
/workspace/coverage/cover_reg_top/13.xbar_smoke.1662534196
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2472943813
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.456500177
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3609744910
/workspace/coverage/cover_reg_top/13.xbar_stress_all.3012454691
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.4123872526
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1814309438
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.774292585
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1693089488
/workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.3234828957
/workspace/coverage/cover_reg_top/14.chip_csr_rw.3293139490
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.1618208139
/workspace/coverage/cover_reg_top/14.chip_tl_errors.3541737390
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.2724376791
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3031906936
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.1818625290
/workspace/coverage/cover_reg_top/14.xbar_error_random.2276033607
/workspace/coverage/cover_reg_top/14.xbar_random.1808887506
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.2372907267
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.3224076632
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.2594509550
/workspace/coverage/cover_reg_top/14.xbar_same_source.3287088026
/workspace/coverage/cover_reg_top/14.xbar_smoke.168660467
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.13975615
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2897150458
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.2353415896
/workspace/coverage/cover_reg_top/14.xbar_stress_all.1416354724
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.1457272577
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.744660943
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/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1936585292
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.4187414448
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1795135943
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3969301909
/workspace/coverage/default/3.chip_tap_straps_dev.2408683786
/workspace/coverage/default/3.chip_tap_straps_prod.88144670
/workspace/coverage/default/3.chip_tap_straps_rma.3169589001
/workspace/coverage/default/3.chip_tap_straps_testunlock0.3938158991
/workspace/coverage/default/30.chip_sw_all_escalation_resets.480733038
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2666571040
/workspace/coverage/default/33.chip_sw_all_escalation_resets.2149972930
/workspace/coverage/default/34.chip_sw_all_escalation_resets.184028488
/workspace/coverage/default/36.chip_sw_all_escalation_resets.2370166940
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1119511777
/workspace/coverage/default/37.chip_sw_all_escalation_resets.1996884367
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.329360883
/workspace/coverage/default/39.chip_sw_all_escalation_resets.1169414011
/workspace/coverage/default/4.chip_sw_all_escalation_resets.2280947734
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3461673699
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.4052270659
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2572855417
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.937993350
/workspace/coverage/default/4.chip_sw_uart_tx_rx.20658588
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3282713176
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1946032050
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2308509507
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3152450731
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1279479874
/workspace/coverage/default/4.chip_tap_straps_dev.556475255
/workspace/coverage/default/4.chip_tap_straps_prod.2454789568
/workspace/coverage/default/4.chip_tap_straps_rma.2626044498
/workspace/coverage/default/4.chip_tap_straps_testunlock0.3209593936
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3076778881
/workspace/coverage/default/41.chip_sw_all_escalation_resets.1167107040
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1664303757
/workspace/coverage/default/43.chip_sw_all_escalation_resets.3349922778
/workspace/coverage/default/44.chip_sw_all_escalation_resets.1882043508
/workspace/coverage/default/45.chip_sw_all_escalation_resets.535839813
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1511457279
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1394526906
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.721821621
/workspace/coverage/default/49.chip_sw_all_escalation_resets.2738829268
/workspace/coverage/default/5.chip_sw_all_escalation_resets.921421169
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.363352615
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2522695859
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3857930866
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3023647825
/workspace/coverage/default/51.chip_sw_all_escalation_resets.1658064776
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.51047642
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.4065925083
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2198680940
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3179183153
/workspace/coverage/default/55.chip_sw_all_escalation_resets.2123142221
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2690022017
/workspace/coverage/default/56.chip_sw_all_escalation_resets.2058258621
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3449806007
/workspace/coverage/default/58.chip_sw_all_escalation_resets.779627844
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1848992862
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1434038672
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2843371552
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1787794639
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1170535248
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2012877914
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3005093125
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2215065916
/workspace/coverage/default/63.chip_sw_all_escalation_resets.3358460273
/workspace/coverage/default/64.chip_sw_all_escalation_resets.1456956164
/workspace/coverage/default/65.chip_sw_all_escalation_resets.3819748197
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.171960848
/workspace/coverage/default/66.chip_sw_all_escalation_resets.4054780076
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.187843220
/workspace/coverage/default/67.chip_sw_all_escalation_resets.3140832638
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2965534557
/workspace/coverage/default/68.chip_sw_all_escalation_resets.592107777
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.510375249
/workspace/coverage/default/69.chip_sw_all_escalation_resets.675030747
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.352016473
/workspace/coverage/default/7.chip_sw_all_escalation_resets.2799807983
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3630587286
/workspace/coverage/default/70.chip_sw_all_escalation_resets.210128517
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2469460934
/workspace/coverage/default/71.chip_sw_all_escalation_resets.171906847
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2874808236
/workspace/coverage/default/72.chip_sw_all_escalation_resets.226695296
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1671137015
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1700475812
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2876840074
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1430653380
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1560243320
/workspace/coverage/default/76.chip_sw_all_escalation_resets.796962027
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.280597848
/workspace/coverage/default/78.chip_sw_all_escalation_resets.2234569492
/workspace/coverage/default/79.chip_sw_all_escalation_resets.3235874314
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1732451331
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3675788040
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2889411971
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.944196401
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.4108165173
/workspace/coverage/default/80.chip_sw_all_escalation_resets.3855036576
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.588301891
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3785677472
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.4129671883
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1400417545
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3409527589
/workspace/coverage/default/83.chip_sw_all_escalation_resets.4069607857
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.4236372396
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2788864498
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.41599156
/workspace/coverage/default/85.chip_sw_all_escalation_resets.924870923
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2864193183
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1759021290
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1091199303
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.442606783
/workspace/coverage/default/88.chip_sw_all_escalation_resets.2399240760
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.4118595098
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.308639566
/workspace/coverage/default/9.chip_sw_all_escalation_resets.2758479024
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2406686333
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1157780262
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2606785246
/workspace/coverage/default/91.chip_sw_all_escalation_resets.499982714
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3894359526
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2051626398
/workspace/coverage/default/94.chip_sw_all_escalation_resets.482640849
/workspace/coverage/default/95.chip_sw_all_escalation_resets.4249702713
/workspace/coverage/default/96.chip_sw_all_escalation_resets.78689056
/workspace/coverage/default/97.chip_sw_all_escalation_resets.136419115
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3784810788
/workspace/coverage/default/99.chip_sw_all_escalation_resets.3313054195
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.4207932635
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.382240485
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2138871170
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3471918018
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.593500158
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1840291839
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1160608754
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2557652825
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1352169031

---

Total test records in report: 2857

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tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T32	/workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.3252148966			Jan 25 03:23:36 AM PST 24	Jan 25 03:25:09 AM PST 24	4647114803 ps
T33	/workspace/coverage/cover_reg_top/26.xbar_random.1419688826			Jan 25 03:10:39 AM PST 24	Jan 25 03:11:28 AM PST 24	1247578061 ps
T34	/workspace/coverage/cover_reg_top/27.xbar_random.135730146			Jan 25 03:10:59 AM PST 24	Jan 25 03:11:06 AM PST 24	33915569 ps
T56	/workspace/coverage/cover_reg_top/0.xbar_same_source.2820057771			Jan 25 02:48:17 AM PST 24	Jan 25 02:48:52 AM PST 24	433729567 ps
T55	/workspace/coverage/cover_reg_top/47.xbar_access_same_device.147993037			Jan 25 03:23:03 AM PST 24	Jan 25 03:25:16 AM PST 24	2989194183 ps
T104	/workspace/coverage/cover_reg_top/60.xbar_stress_all.1274384409			Jan 25 03:31:56 AM PST 24	Jan 25 03:41:34 AM PST 24	15688769744 ps
T301	/workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.1594462510			Jan 25 03:41:43 AM PST 24	Jan 25 03:42:51 AM PST 24	5809512129 ps
T186	/workspace/coverage/cover_reg_top/34.xbar_error_random.361933736			Jan 25 03:15:06 AM PST 24	Jan 25 03:15:36 AM PST 24	280701665 ps
T187	/workspace/coverage/cover_reg_top/75.xbar_error_random.850109386			Jan 25 03:41:52 AM PST 24	Jan 25 03:42:40 AM PST 24	1301987475 ps
T29	/workspace/coverage/cover_reg_top/7.chip_tl_errors.3771500955			Jan 25 02:53:21 AM PST 24	Jan 25 03:00:07 AM PST 24	4180001935 ps
T370	/workspace/coverage/cover_reg_top/65.xbar_random_large_delays.2928455553			Jan 25 03:34:24 AM PST 24	Jan 25 03:51:24 AM PST 24	85041221212 ps
T377	/workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.3937051091			Jan 25 03:29:09 AM PST 24	Jan 25 03:31:01 AM PST 24	5613146209 ps
T364	/workspace/coverage/cover_reg_top/30.xbar_error_random.2700553276			Jan 25 03:13:09 AM PST 24	Jan 25 03:13:22 AM PST 24	78137261 ps
T376	/workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.1542711779			Jan 25 03:07:23 AM PST 24	Jan 25 03:07:33 AM PST 24	128861259 ps
T105	/workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.1951305488			Jan 25 03:52:46 AM PST 24	Jan 25 04:00:30 AM PST 24	3093647759 ps
T378	/workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.2891059608			Jan 25 03:40:17 AM PST 24	Jan 25 03:42:12 AM PST 24	10232816712 ps
T360	/workspace/coverage/cover_reg_top/46.xbar_stress_all.2287417859			Jan 25 03:22:32 AM PST 24	Jan 25 03:33:46 AM PST 24	16565774551 ps
T368	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.2307658949			Jan 25 03:55:39 AM PST 24	Jan 25 03:56:49 AM PST 24	189325187 ps
T500	/workspace/coverage/cover_reg_top/38.xbar_smoke.1708724821			Jan 25 03:16:32 AM PST 24	Jan 25 03:16:41 AM PST 24	150893348 ps
T361	/workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.2842547444			Jan 25 03:20:40 AM PST 24	Jan 25 03:21:03 AM PST 24	207263938 ps
T510	/workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.684233960			Jan 25 03:51:28 AM PST 24	Jan 25 03:53:10 AM PST 24	8498363100 ps
T371	/workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.2198160716			Jan 25 04:44:57 AM PST 24	Jan 25 04:55:51 AM PST 24	33623271588 ps
T359	/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.4245246842			Jan 25 02:57:56 AM PST 24	Jan 25 03:03:43 AM PST 24	18866305398 ps
T381	/workspace/coverage/cover_reg_top/35.xbar_error_random.2803332781			Jan 25 03:15:27 AM PST 24	Jan 25 03:15:55 AM PST 24	270021083 ps
T808	/workspace/coverage/cover_reg_top/68.xbar_smoke.2884123077			Jan 25 03:35:58 AM PST 24	Jan 25 03:36:21 AM PST 24	46294729 ps
T379	/workspace/coverage/cover_reg_top/57.xbar_error_random.1812420912			Jan 25 03:29:48 AM PST 24	Jan 25 03:30:17 AM PST 24	651867701 ps
T380	/workspace/coverage/cover_reg_top/42.xbar_access_same_device.4287033089			Jan 25 03:40:24 AM PST 24	Jan 25 03:41:09 AM PST 24	857828954 ps
T348	/workspace/coverage/cover_reg_top/16.xbar_stress_all.1060077858			Jan 25 03:02:10 AM PST 24	Jan 25 03:09:32 AM PST 24	12053159449 ps
T30	/workspace/coverage/cover_reg_top/17.chip_csr_rw.3457095851			Jan 25 03:03:24 AM PST 24	Jan 25 03:11:52 AM PST 24	5712479648 ps
T31	/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3841364985			Jan 25 02:58:55 AM PST 24	Jan 25 04:02:04 AM PST 24	30933779523 ps
T369	/workspace/coverage/cover_reg_top/6.xbar_random_large_delays.2902710266			Jan 25 02:52:42 AM PST 24	Jan 25 03:08:07 AM PST 24	85500481590 ps
T366	/workspace/coverage/cover_reg_top/43.xbar_same_source.1416814334			Jan 25 03:20:20 AM PST 24	Jan 25 03:20:45 AM PST 24	211375225 ps
T383	/workspace/coverage/cover_reg_top/78.xbar_error_random.1473099383			Jan 25 03:43:36 AM PST 24	Jan 25 03:45:01 AM PST 24	2007030585 ps
T566	/workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.4029052143			Jan 25 03:44:47 AM PST 24	Jan 25 03:45:52 AM PST 24	1482107178 ps
T509	/workspace/coverage/cover_reg_top/23.xbar_smoke.311457722			Jan 25 03:07:37 AM PST 24	Jan 25 03:07:45 AM PST 24	48121643 ps
T367	/workspace/coverage/cover_reg_top/10.xbar_stress_all.1299111367			Jan 25 02:56:38 AM PST 24	Jan 25 02:59:32 AM PST 24	1491399063 ps
T572	/workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.2752105166			Jan 25 04:43:22 AM PST 24	Jan 25 04:44:24 AM PST 24	677749009 ps
T730	/workspace/coverage/cover_reg_top/51.xbar_access_same_device.2304252094			Jan 25 03:25:56 AM PST 24	Jan 25 03:27:34 AM PST 24	2514344626 ps
T382	/workspace/coverage/cover_reg_top/5.xbar_error_random.723125279			Jan 25 02:51:52 AM PST 24	Jan 25 02:52:22 AM PST 24	321608975 ps
T740	/workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.301078877			Jan 25 03:11:47 AM PST 24	Jan 25 03:25:27 AM PST 24	45274464826 ps
T373	/workspace/coverage/cover_reg_top/99.xbar_random_large_delays.3856629170			Jan 25 04:27:04 AM PST 24	Jan 25 04:39:09 AM PST 24	60437372362 ps
T499	/workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.683615382			Jan 25 03:17:57 AM PST 24	Jan 25 03:19:25 AM PST 24	4850859035 ps
T372	/workspace/coverage/cover_reg_top/42.xbar_random_large_delays.3750046146			Jan 25 04:36:45 AM PST 24	Jan 25 04:45:59 AM PST 24	48300980680 ps
T741	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.3507543020			Jan 25 03:02:10 AM PST 24	Jan 25 03:04:02 AM PST 24	3028743153 ps
T809	/workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.1310222612			Jan 25 03:47:26 AM PST 24	Jan 25 03:48:18 AM PST 24	4396030317 ps
T810	/workspace/coverage/cover_reg_top/60.xbar_error_random.1398214855			Jan 25 03:31:33 AM PST 24	Jan 25 03:32:04 AM PST 24	880387486 ps
T374	/workspace/coverage/cover_reg_top/82.xbar_random_large_delays.4184861065			Jan 25 03:45:45 AM PST 24	Jan 25 03:48:37 AM PST 24	15691392010 ps
T1	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1160608754			Jan 24 10:39:53 PM PST 24	Jan 24 10:42:40 PM PST 24	4871775176 ps
T2	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2961579025			Jan 24 10:39:58 PM PST 24	Jan 24 10:44:06 PM PST 24	5336102568 ps
T3	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2138871170			Jan 24 10:39:50 PM PST 24	Jan 24 10:45:09 PM PST 24	5748946000 ps
T7	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3471918018			Jan 24 10:39:50 PM PST 24	Jan 24 10:42:43 PM PST 24	3367816564 ps
T60	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.382240485			Jan 24 10:39:54 PM PST 24	Jan 24 10:43:50 PM PST 24	4099555652 ps
T61	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.4207932635			Jan 24 10:39:52 PM PST 24	Jan 24 10:44:27 PM PST 24	5774545224 ps
T62	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.593500158			Jan 25 02:06:24 AM PST 24	Jan 25 02:11:52 AM PST 24	5285980428 ps
T63	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1352169031			Jan 24 10:39:59 PM PST 24	Jan 24 10:43:34 PM PST 24	3942837568 ps
T64	/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1840291839			Jan 24 10:39:48 PM PST 24	Jan 24 10:43:11 PM PST 24	5085903670 ps
T65	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2557652825			Jan 24 10:39:52 PM PST 24	Jan 24 10:44:01 PM PST 24	4770095030 ps
T17	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.113098362			Jan 25 04:03:17 AM PST 24	Jan 25 04:06:58 AM PST 24	2452150968 ps
T18	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.702362349			Jan 25 01:48:04 AM PST 24	Jan 25 01:56:10 AM PST 24	3326880750 ps
T19	/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2091795408			Jan 25 12:12:00 AM PST 24	Jan 25 12:17:05 AM PST 24	2353955963 ps
T20	/workspace/coverage/default/2.chip_sw_all_escalation_resets.3141321084			Jan 25 12:47:46 AM PST 24	Jan 25 12:57:26 AM PST 24	5283070172 ps
T72	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.1856492492			Jan 25 12:53:02 AM PST 24	Jan 25 01:08:20 AM PST 24	6405597247 ps
T21	/workspace/coverage/default/77.chip_sw_all_escalation_resets.2645683822			Jan 25 02:01:39 AM PST 24	Jan 25 02:13:06 AM PST 24	4658344732 ps
T41	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3739305185			Jan 25 12:25:53 AM PST 24	Jan 25 12:53:20 AM PST 24	11440302218 ps
T73	/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2836140392			Jan 25 02:04:24 AM PST 24	Jan 25 02:11:44 AM PST 24	6408414618 ps
T74	/workspace/coverage/default/35.chip_sw_all_escalation_resets.131450711			Jan 25 01:48:28 AM PST 24	Jan 25 02:00:20 AM PST 24	5869926888 ps
T75	/workspace/coverage/default/1.chip_sw_aes_masking_off.133391960			Jan 25 12:29:10 AM PST 24	Jan 25 12:36:02 AM PST 24	3391444473 ps
T76	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3560677974			Jan 25 02:30:03 AM PST 24	Jan 25 02:37:00 AM PST 24	4369565464 ps
T45	/workspace/coverage/default/1.chip_tap_straps_prod.1211450288			Jan 25 01:01:14 AM PST 24	Jan 25 01:04:01 AM PST 24	3334314286 ps
T175	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.180190115			Jan 25 01:06:55 AM PST 24	Jan 25 01:35:23 AM PST 24	7620741846 ps
T141	/workspace/coverage/default/1.rom_e2e_smoke.2769836798			Jan 25 01:46:33 AM PST 24	Jan 25 02:23:46 AM PST 24	8353632610 ps
T181	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.4021536846			Jan 25 03:38:21 AM PST 24	Jan 25 03:45:49 AM PST 24	3786423440 ps
T152	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3918462383			Jan 25 02:10:19 AM PST 24	Jan 25 02:16:41 AM PST 24	3473871064 ps
T95	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2833516750			Jan 25 02:53:14 AM PST 24	Jan 25 03:03:37 AM PST 24	5393050038 ps
T159	/workspace/coverage/default/42.chip_sw_all_escalation_resets.2262830773			Jan 25 01:50:18 AM PST 24	Jan 25 02:04:16 AM PST 24	4918601240 ps
T160	/workspace/coverage/default/52.chip_sw_all_escalation_resets.1618398408			Jan 25 03:58:54 AM PST 24	Jan 25 04:06:49 AM PST 24	5053072720 ps
T100	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1507528445			Jan 25 12:26:48 AM PST 24	Jan 25 01:17:48 AM PST 24	27188773772 ps
T47	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.320468671			Jan 25 01:13:33 AM PST 24	Jan 25 01:26:22 AM PST 24	3860878480 ps
T134	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.464964605			Jan 25 01:19:20 AM PST 24	Jan 25 02:00:16 AM PST 24	22780465091 ps
T671	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3076778881			Jan 25 04:53:50 AM PST 24	Jan 25 04:58:40 AM PST 24	3270290568 ps
T38	/workspace/coverage/default/1.rom_raw_unlock.454847092			Jan 25 12:44:44 AM PST 24	Jan 25 01:25:47 AM PST 24	15977479273 ps
T346	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1349859148			Jan 25 01:45:06 AM PST 24	Jan 25 01:52:19 AM PST 24	4014323896 ps
T347	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.1016692358			Jan 25 03:06:48 AM PST 24	Jan 25 03:11:01 AM PST 24	2344817008 ps
T106	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1379591497			Jan 25 12:00:08 AM PST 24	Jan 25 12:06:13 AM PST 24	4818895378 ps
T57	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.1358815435			Jan 25 12:04:50 AM PST 24	Jan 25 12:11:14 AM PST 24	4072741136 ps
T8	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1468127954			Jan 25 01:46:02 AM PST 24	Jan 25 01:54:27 AM PST 24	4435757504 ps
T77	/workspace/coverage/default/1.chip_sw_aes_entropy.1777305833			Jan 25 12:30:34 AM PST 24	Jan 25 12:34:16 AM PST 24	2169617656 ps
T78	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1121901998			Jan 25 12:06:56 AM PST 24	Jan 25 12:12:08 AM PST 24	2915095064 ps
T79	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.4187414448			Jan 25 01:34:30 AM PST 24	Jan 25 01:51:56 AM PST 24	5216996740 ps
T46	/workspace/coverage/default/1.chip_tap_straps_testunlock0.1925149444			Jan 25 12:38:32 AM PST 24	Jan 25 12:55:29 AM PST 24	8969707829 ps
T80	/workspace/coverage/default/1.chip_sw_edn_sw_mode.3232708714			Jan 25 02:15:54 AM PST 24	Jan 25 02:44:37 AM PST 24	7413845440 ps
T81	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.30989975			Jan 25 02:13:51 AM PST 24	Jan 25 02:58:03 AM PST 24	9901395010 ps
T82	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2155357439			Jan 25 08:30:10 AM PST 24	Jan 25 08:55:22 AM PST 24	9094707500 ps
T83	/workspace/coverage/default/91.chip_sw_all_escalation_resets.499982714			Jan 25 03:46:54 AM PST 24	Jan 25 03:59:21 AM PST 24	6308899776 ps
T84	/workspace/coverage/default/55.chip_sw_all_escalation_resets.2123142221			Jan 25 02:40:27 AM PST 24	Jan 25 02:53:07 AM PST 24	5117432112 ps
T341	/workspace/coverage/default/2.rom_e2e_asm_init_prod.1846522643			Jan 25 03:01:48 AM PST 24	Jan 25 03:40:07 AM PST 24	8705383610 ps
T627	/workspace/coverage/default/34.chip_sw_all_escalation_resets.184028488			Jan 25 02:04:39 AM PST 24	Jan 25 02:17:33 AM PST 24	4451506456 ps
T342	/workspace/coverage/default/1.chip_sw_uart_smoketest_signed.1040776036			Jan 25 12:48:45 AM PST 24	Jan 25 01:31:06 AM PST 24	9219116170 ps
T97	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1936585292			Jan 25 01:33:42 AM PST 24	Jan 25 02:58:54 AM PST 24	22778776828 ps
T66	/workspace/coverage/default/29.chip_sw_all_escalation_resets.746335861			Jan 25 01:47:17 AM PST 24	Jan 25 01:58:14 AM PST 24	5308171516 ps
T58	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3416264276			Jan 25 01:02:32 AM PST 24	Jan 25 01:34:30 AM PST 24	12461930288 ps
T103	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3276690121			Jan 25 05:25:24 AM PST 24	Jan 25 05:42:33 AM PST 24	5006329720 ps
T644	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.510375249			Jan 25 02:03:18 AM PST 24	Jan 25 02:10:01 AM PST 24	3044282200 ps
T264	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.451773182			Jan 24 11:55:27 PM PST 24	Jan 25 12:10:43 AM PST 24	4857934982 ps
T260	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2811838044			Jan 25 12:22:07 AM PST 24	Jan 25 12:40:31 AM PST 24	5456157440 ps
T343	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.131949463			Jan 25 12:39:15 AM PST 24	Jan 25 01:22:32 AM PST 24	8042235846 ps
T277	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2449616065			Jan 25 01:04:28 AM PST 24	Jan 25 01:19:19 AM PST 24	4967006002 ps
T811	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1679948304			Jan 25 12:25:51 AM PST 24	Jan 25 12:34:33 AM PST 24	6294803352 ps
T265	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.101400666			Jan 25 12:52:04 AM PST 24	Jan 25 01:08:13 AM PST 24	5622820390 ps
T39	/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2278788261			Jan 25 01:36:07 AM PST 24	Jan 25 01:56:58 AM PST 24	13137766185 ps
T714	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3857930866			Jan 25 01:52:23 AM PST 24	Jan 25 01:59:10 AM PST 24	3698207606 ps
T630	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.4200529225			Jan 25 01:39:27 AM PST 24	Jan 25 01:48:49 AM PST 24	3643978800 ps
T812	/workspace/coverage/default/0.chip_sw_kmac_idle.2452745183			Jan 25 12:08:33 AM PST 24	Jan 25 12:13:09 AM PST 24	2964378222 ps
T284	/workspace/coverage/default/64.chip_sw_all_escalation_resets.1456956164			Jan 25 01:56:08 AM PST 24	Jan 25 02:09:21 AM PST 24	5141152670 ps
T645	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1671137015			Jan 25 02:00:37 AM PST 24	Jan 25 02:06:57 AM PST 24	3463109688 ps
T619	/workspace/coverage/default/43.chip_sw_all_escalation_resets.3349922778			Jan 25 01:50:08 AM PST 24	Jan 25 02:04:07 AM PST 24	5308162242 ps
T333	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1745970577			Jan 25 12:39:57 AM PST 24	Jan 25 12:42:54 AM PST 24	2503522756 ps
T255	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2399642472			Jan 25 12:21:48 AM PST 24	Jan 25 12:42:46 AM PST 24	5739132812 ps
T98	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4192578314			Jan 25 02:43:20 AM PST 24	Jan 25 02:54:19 AM PST 24	3301308792 ps
T96	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.981658239			Jan 25 12:13:04 AM PST 24	Jan 25 12:20:47 AM PST 24	3345406690 ps
T344	/workspace/coverage/default/2.chip_sw_uart_smoketest_signed.3495343207			Jan 25 01:35:56 AM PST 24	Jan 25 02:17:08 AM PST 24	8678158740 ps
T35	/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3647389293			Jan 25 03:30:46 AM PST 24	Jan 25 03:38:39 AM PST 24	5255547300 ps
T813	/workspace/coverage/default/0.chip_sw_kmac_app_rom.251463070			Jan 25 12:44:21 AM PST 24	Jan 25 12:49:11 AM PST 24	3350861280 ps
T814	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.4010576834			Jan 25 12:19:55 AM PST 24	Jan 25 12:24:00 AM PST 24	2665687824 ps
T815	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2557209283			Jan 25 12:19:37 AM PST 24	Jan 25 12:28:28 AM PST 24	3848697120 ps
T595	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3045149293			Jan 24 11:53:35 PM PST 24	Jan 25 12:17:23 AM PST 24	8198120334 ps
T137	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2969299467			Jan 25 12:06:42 AM PST 24	Jan 25 12:18:48 AM PST 24	4706244228 ps
T99	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3884473310			Jan 25 01:13:42 AM PST 24	Jan 25 01:23:37 AM PST 24	4719347496 ps
T816	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1698168354			Jan 25 12:37:28 AM PST 24	Jan 25 12:47:17 AM PST 24	4788983980 ps
T817	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.830253009			Jan 25 12:06:10 AM PST 24	Jan 25 12:11:34 AM PST 24	3129445268 ps
T818	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3566990774			Jan 25 01:33:01 AM PST 24	Jan 25 01:37:20 AM PST 24	2555072362 ps
T292	/workspace/coverage/default/15.chip_sw_all_escalation_resets.1071071179			Jan 25 01:42:02 AM PST 24	Jan 25 01:56:16 AM PST 24	6218786990 ps
T149	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2890222095			Jan 25 01:22:14 AM PST 24	Jan 25 01:32:53 AM PST 24	4634829562 ps
T711	/workspace/coverage/default/62.chip_sw_all_escalation_resets.836730582			Jan 25 01:55:44 AM PST 24	Jan 25 02:11:10 AM PST 24	5260103884 ps
T261	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1247431672			Jan 25 01:40:23 AM PST 24	Jan 25 01:53:22 AM PST 24	4156473430 ps
T721	/workspace/coverage/default/39.chip_sw_all_escalation_resets.1169414011			Jan 25 02:06:46 AM PST 24	Jan 25 02:20:38 AM PST 24	6217487360 ps
T304	/workspace/coverage/default/11.chip_sw_all_escalation_resets.2034450857			Jan 25 01:40:23 AM PST 24	Jan 25 01:51:05 AM PST 24	4791357724 ps
T588	/workspace/coverage/default/8.chip_sw_all_escalation_resets.3675788040			Jan 25 01:36:51 AM PST 24	Jan 25 01:49:05 AM PST 24	5371126598 ps
T40	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2889411971			Jan 25 01:37:28 AM PST 24	Jan 25 01:52:26 AM PST 24	8485055585 ps
T674	/workspace/coverage/default/45.chip_sw_all_escalation_resets.535839813			Jan 25 03:54:37 AM PST 24	Jan 25 04:05:03 AM PST 24	4674227572 ps
T819	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2602655889			Jan 25 05:37:48 AM PST 24	Jan 25 05:40:58 AM PST 24	2457549444 ps
T48	/workspace/coverage/default/3.chip_tap_straps_rma.3169589001			Jan 25 01:34:00 AM PST 24	Jan 25 01:41:17 AM PST 24	4453579852 ps
T599	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1276822498			Jan 25 01:29:45 AM PST 24	Jan 25 01:45:11 AM PST 24	4947206516 ps
T820	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1145665541			Jan 25 01:01:59 AM PST 24	Jan 25 01:07:20 AM PST 24	3184332084 ps
T667	/workspace/coverage/default/69.chip_sw_all_escalation_resets.675030747			Jan 25 01:57:24 AM PST 24	Jan 25 02:07:35 AM PST 24	4751199082 ps
T821	/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.350029447			Jan 25 12:00:03 AM PST 24	Jan 25 12:04:30 AM PST 24	2729503476 ps
T107	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3948676098			Jan 25 12:35:09 AM PST 24	Jan 25 12:53:43 AM PST 24	7463123482 ps
T111	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2136109702			Jan 25 03:18:01 AM PST 24	Jan 25 03:29:41 AM PST 24	6675171048 ps
T822	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2492027385			Jan 25 01:02:20 AM PST 24	Jan 25 01:09:31 AM PST 24	3607917228 ps
T274	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3520230259			Jan 24 11:55:39 PM PST 24	Jan 25 12:04:23 AM PST 24	3647945774 ps
T585	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.2701173933			Jan 25 12:22:17 AM PST 24	Jan 25 04:47:50 AM PST 24	67071190324 ps
T823	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1335936998			Jan 25 02:42:57 AM PST 24	Jan 25 03:05:39 AM PST 24	7712540673 ps
T183	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.721821621			Jan 25 01:51:47 AM PST 24	Jan 25 01:59:39 AM PST 24	3680678570 ps
T176	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.1444179462			Jan 25 12:46:20 AM PST 24	Jan 25 01:02:29 AM PST 24	6727692520 ps
T220	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1571818268			Jan 25 01:10:48 AM PST 24	Jan 25 01:21:28 AM PST 24	7767378824 ps
T221	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1143150461			Jan 25 12:40:06 AM PST 24	Jan 25 12:59:16 AM PST 24	6427490584 ps
T222	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2111047528			Jan 25 12:54:41 AM PST 24	Jan 25 01:38:27 AM PST 24	23890847487 ps
T128	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1337518022			Jan 25 12:26:11 AM PST 24	Jan 25 01:10:36 AM PST 24	34271724534 ps
T824	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.1917534997			Jan 25 12:27:41 AM PST 24	Jan 25 12:31:59 AM PST 24	3028951342 ps
T345	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.761092216			Jan 25 12:19:55 AM PST 24	Jan 25 12:53:00 AM PST 24	6232889016 ps
T825	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.462129438			Jan 25 01:42:40 AM PST 24	Jan 25 02:33:04 AM PST 24	13271914320 ps
T690	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1614535936			Jan 25 02:02:44 AM PST 24	Jan 25 02:09:32 AM PST 24	4480366328 ps
T129	/workspace/coverage/default/1.chip_sw_all_escalation_resets.2177167518			Jan 25 12:22:28 AM PST 24	Jan 25 12:35:54 AM PST 24	5931571344 ps
T723	/workspace/coverage/default/84.chip_sw_all_escalation_resets.2788864498			Jan 25 02:04:54 AM PST 24	Jan 25 02:16:56 AM PST 24	5433032314 ps
T826	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.4291435966			Jan 25 02:22:57 AM PST 24	Jan 25 02:36:35 AM PST 24	5683781250 ps
T67	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.4065925083			Jan 25 03:46:26 AM PST 24	Jan 25 03:52:51 AM PST 24	4082063492 ps
T663	/workspace/coverage/default/97.chip_sw_all_escalation_resets.136419115			Jan 25 02:05:56 AM PST 24	Jan 25 02:17:50 AM PST 24	6204508280 ps
T601	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2079550243			Jan 25 12:03:52 AM PST 24	Jan 25 12:17:58 AM PST 24	4201756596 ps
T250	/workspace/coverage/default/0.chip_plic_all_irqs_0.2400722562			Jan 25 12:08:14 AM PST 24	Jan 25 12:29:01 AM PST 24	5845201522 ps
T101	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.986772342			Jan 25 02:56:47 AM PST 24	Jan 25 03:29:33 AM PST 24	7771614760 ps
T628	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3128242288			Jan 25 03:17:46 AM PST 24	Jan 25 03:25:20 AM PST 24	3344889216 ps
T827	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.684910374			Jan 25 12:47:13 AM PST 24	Jan 25 12:50:19 AM PST 24	3136466416 ps
T362	/workspace/coverage/default/1.chip_sw_kmac_entropy.3991793277			Jan 25 12:24:49 AM PST 24	Jan 25 12:31:09 AM PST 24	3544372896 ps
T828	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1856445057			Jan 25 01:12:40 AM PST 24	Jan 25 01:19:07 AM PST 24	4724616330 ps
T696	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.783674327			Jan 25 01:54:30 AM PST 24	Jan 25 02:01:23 AM PST 24	3424598744 ps
T153	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2325598944			Jan 25 12:04:19 AM PST 24	Jan 25 12:38:10 AM PST 24	7808214820 ps
T281	/workspace/coverage/default/1.chip_sw_pattgen_ios.2264255309			Jan 25 02:28:06 AM PST 24	Jan 25 02:32:14 AM PST 24	2673562800 ps
T102	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1084338683			Jan 25 01:50:38 AM PST 24	Jan 25 03:11:01 AM PST 24	16539332802 ps
T829	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2330165842			Jan 25 02:39:08 AM PST 24	Jan 25 02:58:11 AM PST 24	5631884366 ps
T26	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2783469943			Jan 25 12:54:17 AM PST 24	Jan 25 01:00:05 AM PST 24	4796547080 ps
T830	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.344305014			Jan 25 01:32:05 AM PST 24	Jan 25 01:52:15 AM PST 24	6018030358 ps
T831	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1519938193			Jan 25 01:15:36 AM PST 24	Jan 25 01:22:50 AM PST 24	2966546128 ps
T251	/workspace/coverage/default/2.chip_plic_all_irqs_20.3440981426			Jan 25 01:12:06 AM PST 24	Jan 25 01:28:04 AM PST 24	4452698900 ps
T114	/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.523751853			Jan 25 12:38:08 AM PST 24	Jan 25 12:45:33 AM PST 24	5832066040 ps
T608	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3936364471			Jan 25 02:47:12 AM PST 24	Jan 25 03:17:23 AM PST 24	8336989868 ps
T586	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3470620148			Jan 25 12:18:38 AM PST 24	Jan 25 01:00:47 AM PST 24	9162703772 ps
T293	/workspace/coverage/default/30.chip_sw_all_escalation_resets.480733038			Jan 25 01:47:52 AM PST 24	Jan 25 01:59:30 AM PST 24	5392405492 ps
T150	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.82768186			Jan 25 12:25:09 AM PST 24	Jan 25 12:32:58 AM PST 24	6149542278 ps
T691	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.4167384727			Jan 25 01:48:43 AM PST 24	Jan 25 01:55:43 AM PST 24	3568055960 ps
T36	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.4119856654			Jan 25 12:20:53 AM PST 24	Jan 25 12:28:08 AM PST 24	4642886120 ps
T177	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.631655147			Jan 25 12:03:10 AM PST 24	Jan 25 12:11:33 AM PST 24	2946211800 ps
T223	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.3576530089			Jan 25 12:27:10 AM PST 24	Jan 25 12:34:11 AM PST 24	4956511400 ps
T832	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2904285474			Jan 25 04:55:27 AM PST 24	Jan 25 04:59:17 AM PST 24	3593698608 ps
T833	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3777154756			Jan 25 12:19:43 AM PST 24	Jan 25 01:04:22 AM PST 24	8603778192 ps
T669	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.4041639094			Jan 25 01:39:13 AM PST 24	Jan 25 01:45:30 AM PST 24	4074630624 ps
T834	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.4241161090			Jan 25 12:35:01 AM PST 24	Jan 25 12:45:21 AM PST 24	6707729900 ps
T620	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1394526906			Jan 25 03:13:44 AM PST 24	Jan 25 03:19:21 AM PST 24	3999701652 ps
T633	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.4270063648			Jan 25 12:10:22 AM PST 24	Jan 25 12:18:01 AM PST 24	3225500760 ps
T626	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.187843220			Jan 25 01:56:47 AM PST 24	Jan 25 02:03:29 AM PST 24	3601392820 ps
T158	/workspace/coverage/default/2.chip_sw_spi_device_tpm.3697437601			Jan 25 01:02:05 AM PST 24	Jan 25 01:07:42 AM PST 24	2921533189 ps
T163	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.50235010			Jan 25 12:06:50 AM PST 24	Jan 25 12:16:57 AM PST 24	3507503176 ps
T621	/workspace/coverage/default/28.chip_sw_all_escalation_resets.758471569			Jan 25 03:18:04 AM PST 24	Jan 25 03:29:16 AM PST 24	5617800756 ps
T92	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2515243406			Jan 25 12:02:59 AM PST 24	Jan 25 01:20:40 AM PST 24	18508493968 ps
T835	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2400266967			Jan 25 12:25:33 AM PST 24	Jan 25 12:33:05 AM PST 24	4630451733 ps
T836	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1338748906			Jan 25 02:24:21 AM PST 24	Jan 25 02:27:45 AM PST 24	3281471884 ps
T325	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3632009555			Jan 25 01:49:38 AM PST 24	Jan 25 02:47:08 AM PST 24	12699088624 ps
T268	/workspace/coverage/default/3.chip_sw_uart_tx_rx.2633096136			Jan 25 01:34:29 AM PST 24	Jan 25 01:52:53 AM PST 24	5456446712 ps
T314	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3600797872			Jan 25 02:37:34 AM PST 24	Jan 25 02:45:27 AM PST 24	5789931102 ps
T115	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1724712063			Jan 25 12:34:27 AM PST 24	Jan 25 12:38:44 AM PST 24	2584105584 ps
T579	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2895582073			Jan 25 03:04:32 AM PST 24	Jan 25 03:29:47 AM PST 24	12275071431 ps
T837	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.634002983			Jan 25 04:53:09 AM PST 24	Jan 25 04:55:18 AM PST 24	2505942228 ps
T688	/workspace/coverage/default/82.chip_sw_all_escalation_resets.1400417545			Jan 25 02:04:47 AM PST 24	Jan 25 02:15:42 AM PST 24	5357540720 ps
T838	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1946032050			Jan 25 01:35:01 AM PST 24	Jan 25 01:45:56 AM PST 24	5280752459 ps
T258	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.3933072452			Jan 25 12:06:07 AM PST 24	Jan 25 12:33:35 AM PST 24	7208317416 ps
T131	/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.326016759			Jan 25 01:17:18 AM PST 24	Jan 25 01:28:28 AM PST 24	5712236280 ps
T634	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.3660008660			Jan 25 12:37:50 AM PST 24	Jan 25 12:56:30 AM PST 24	7375116910 ps
T637	/workspace/coverage/default/87.chip_sw_all_escalation_resets.123219970			Jan 25 02:01:54 AM PST 24	Jan 25 02:13:57 AM PST 24	5404382760 ps
T632	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.840552889			Jan 25 12:21:33 AM PST 24	Jan 25 12:33:55 AM PST 24	6182291100 ps
T328	/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3319924140			Jan 25 12:46:53 AM PST 24	Jan 25 01:24:07 AM PST 24	8467737842 ps
T334	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3004113427			Jan 24 11:55:59 PM PST 24	Jan 25 12:00:02 AM PST 24	2338796384 ps
T120	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.30009652			Jan 25 01:03:38 AM PST 24	Jan 25 02:21:28 AM PST 24	17774836860 ps
T282	/workspace/coverage/default/0.chip_sw_pattgen_ios.3989889427			Jan 24 11:53:47 PM PST 24	Jan 25 12:00:28 AM PST 24	3006800960 ps
T587	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3071322742			Jan 25 05:12:06 AM PST 24	Jan 25 05:19:40 AM PST 24	9666104286 ps
T93	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1234824483			Jan 25 01:08:01 AM PST 24	Jan 25 01:23:35 AM PST 24	5150823107 ps
T839	/workspace/coverage/default/2.chip_sw_csrng_smoketest.810797491			Jan 25 01:32:49 AM PST 24	Jan 25 01:38:05 AM PST 24	2415021950 ps
T275	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.4011933036			Jan 25 12:51:34 AM PST 24	Jan 25 01:10:31 AM PST 24	5176084120 ps
T326	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3774785884			Jan 25 12:21:13 AM PST 24	Jan 25 01:22:54 AM PST 24	11681452312 ps
T840	/workspace/coverage/default/0.chip_sw_example_rom.3292086711			Jan 24 11:52:06 PM PST 24	Jan 24 11:54:10 PM PST 24	1894902126 ps
T841	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1509979081			Jan 25 03:30:54 AM PST 24	Jan 25 03:35:10 AM PST 24	3381336741 ps
T842	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.16435836			Jan 25 02:54:53 AM PST 24	Jan 25 03:04:06 AM PST 24	6301142720 ps
T151	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3075237905			Jan 25 01:15:38 AM PST 24	Jan 25 01:23:55 AM PST 24	4127003719 ps
T85	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3765032477			Jan 25 01:04:19 AM PST 24	Jan 25 01:13:14 AM PST 24	17956594456 ps
T624	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3970970273			Jan 25 05:11:42 AM PST 24	Jan 25 05:16:44 AM PST 24	4088271328 ps
T189	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3547950269			Jan 25 12:45:32 AM PST 24	Jan 25 12:49:26 AM PST 24	2864937320 ps
T668	/workspace/coverage/default/95.chip_sw_all_escalation_resets.4249702713			Jan 25 02:49:46 AM PST 24	Jan 25 03:01:59 AM PST 24	4861037704 ps
T86	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2074799349			Jan 25 12:27:10 AM PST 24	Jan 25 12:36:40 AM PST 24	18178250774 ps
T843	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.527688887			Jan 25 01:14:03 AM PST 24	Jan 25 01:23:37 AM PST 24	5745412900 ps
T675	/workspace/coverage/default/90.chip_sw_all_escalation_resets.2606785246			Jan 25 02:03:19 AM PST 24	Jan 25 02:17:02 AM PST 24	6428913002 ps
T113	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.352878154			Jan 25 02:06:54 AM PST 24	Jan 25 02:17:21 AM PST 24	4350253370 ps
T844	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2191702667			Jan 25 12:11:54 AM PST 24	Jan 25 12:16:54 AM PST 24	3273726163 ps
T9	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1896112684			Jan 25 03:22:41 AM PST 24	Jan 25 03:29:48 AM PST 24	5390882964 ps
T144	/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2238076860			Jan 25 01:10:17 AM PST 24	Jan 25 01:23:12 AM PST 24	6173853527 ps
T239	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2119599884			Jan 25 12:21:37 AM PST 24	Jan 25 12:29:23 AM PST 24	4583571216 ps
T240	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.648450257			Jan 25 01:24:40 AM PST 24	Jan 25 01:31:09 AM PST 24	3187554987 ps
T241	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3920167396			Jan 25 12:07:49 AM PST 24	Jan 25 12:18:42 AM PST 24	7445955252 ps
T242	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2576495969			Jan 25 02:29:37 AM PST 24	Jan 25 02:50:19 AM PST 24	8474084710 ps
T243	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1781936287			Jan 25 12:47:54 AM PST 24	Jan 25 01:32:26 AM PST 24	9266265609 ps
T244	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3297763499			Jan 25 06:36:30 AM PST 24	Jan 25 06:40:26 AM PST 24	2270458588 ps
T245	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1434038672			Jan 25 01:36:32 AM PST 24	Jan 25 01:42:41 AM PST 24	3443501150 ps
T246	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2576152099			Jan 25 01:50:25 AM PST 24	Jan 25 01:59:10 AM PST 24	3414060782 ps