Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	162173	1			T32	4		T33	35		T34	4
values[2]	4811	1			T33	1		T55	2		T104	1
values[3]	2313	1			T55	2		T360	78		T573	6
values[4]	1689	1			T55	3		T360	43		T573	5
values[5]	1300	1			T55	6		T360	13		T573	7
values[6]	1213	1			T55	6		T360	5		T573	10
values[7]	1102	1			T55	1		T360	5		T573	15
values[8]	943	1			T55	1		T360	5		T573	12
values[9]	826	1			T55	2		T573	12		T406	1
values[10]	768	1			T55	6		T573	11		T406	1
values[11]	635	1			T55	7		T573	8		T406	1
values[12]	546	1			T55	4		T573	3		T406	1
values[13]	533	1			T55	3		T573	3		T406	1
values[14]	564	1			T55	3		T573	7		T406	1
values[15]	498	1			T55	1		T573	7		T406	1
values[16]	438	1			T55	2		T573	8		T406	1
values[17]	372	1			T55	4		T573	1		T406	1
values[18]	235	1			T55	5		T573	3		T406	1
values[19]	166	1			T55	1		T573	8		T406	1
values[20]	166	1			T55	2		T573	6		T406	1
values[21]	114	1			T55	3		T573	2		T406	1
values[22]	115	1			T55	1		T573	4		T406	1
values[23]	129	1			T55	3		T573	5		T406	1
values[24]	121	1			T55	2		T573	9		T406	1
values[25]	106	1			T55	5		T573	5		T406	1
values[26]	77	1			T55	5		T573	2		T406	1
values[27]	82	1			T55	6		T406	1		T742	1
values[28]	76	1			T55	6		T406	1		T742	1
values[29]	76	1			T55	1		T406	1		T742	1
values[30]	85	1			T55	5		T406	1		T742	1
values[31]	86	1			T55	3		T406	1		T742	1
values[32]	80	1			T55	1		T406	1		T742	1
values[33]	91	1			T55	1		T406	1		T742	1
values[34]	97	1			T55	1		T406	1		T742	1
values[35]	84	1			T55	2		T406	1		T742	1
values[36]	73	1			T55	3		T406	1		T742	1
values[37]	71	1			T55	6		T406	1		T742	1
values[38]	73	1			T55	4		T406	1		T742	1
values[39]	55	1			T55	2		T406	1		T742	1
values[40]	45	1			T55	4		T406	1		T742	1
values[41]	52	1			T55	7		T406	1		T742	1
values[42]	47	1			T55	5		T406	1		T742	1
values[43]	37	1			T55	4		T406	1		T742	1
values[44]	35	1			T55	4		T406	1		T742	1
values[45]	34	1			T55	2		T406	1		T742	1
values[46]	39	1			T55	2		T406	1		T742	1
values[47]	40	1			T55	6		T406	1		T742	1
values[48]	45	1			T55	6		T406	1		T742	1
values[49]	36	1			T55	1		T406	2		T742	1
values[50]	26	1			T55	1		T406	1		T742	1
values[51]	36	1			T55	2		T406	1		T742	1
values[52]	33	1			T55	1		T406	2		T742	1
values[53]	34	1			T55	3		T406	1		T742	1
values[54]	39	1			T55	6		T406	1		T742	1
values[55]	23	1			T55	2		T406	1		T742	1
values[56]	42	1			T55	2		T406	1		T742	1
values[57]	30	1			T55	2		T406	1		T742	1
values[58]	31	1			T55	1		T406	1		T742	1
values[59]	38	1			T55	3		T406	1		T742	1
values[60]	34	1			T55	2		T406	1		T742	1
values[61]	30	1			T55	1		T406	1		T742	1
values[62]	33	1			T55	2		T406	1		T742	1
values[63]	39	1			T55	2		T406	1		T742	1
values[64]	32	1			T55	4		T406	1		T742	1
values[65]	34	1			T55	5		T406	1		T742	1
values[66]	31	1			T55	2		T406	1		T742	1
values[67]	38	1			T55	2		T406	1		T742	1
values[68]	31	1			T55	1		T406	1		T742	1
values[69]	34	1			T55	2		T406	1		T742	1
values[70]	36	1			T55	3		T406	1		T742	1
values[71]	43	1			T55	2		T406	1		T742	1
values[72]	34	1			T55	3		T406	1		T742	1
values[73]	34	1			T55	2		T406	1		T742	1
values[74]	36	1			T55	7		T406	1		T742	1
values[75]	33	1			T55	4		T406	1		T742	1
values[76]	34	1			T55	1		T406	1		T742	1
values[77]	59	1			T55	5		T406	1		T742	1
values[78]	50	1			T55	5		T406	1		T742	1
values[79]	45	1			T55	7		T406	1		T742	1
values[80]	39	1			T55	2		T406	1		T742	1
values[81]	40	1			T55	2		T406	1		T742	1
values[82]	43	1			T55	2		T406	1		T742	1
values[83]	44	1			T55	2		T406	1		T742	1
values[84]	43	1			T55	1		T406	1		T742	1
values[85]	57	1			T55	5		T406	1		T742	1
values[86]	48	1			T55	5		T406	1		T742	1
values[87]	49	1			T55	1		T406	1		T742	1
values[88]	50	1			T55	1		T406	1		T742	1
values[89]	53	1			T55	7		T406	1		T742	1
values[90]	35	1			T55	1		T406	1		T742	1
values[91]	56	1			T55	1		T406	1		T742	1
values[92]	71	1			T55	5		T406	1		T742	1
values[93]	45	1			T55	1		T406	1		T742	1
values[94]	66	1			T55	3		T406	1		T742	1
values[95]	52	1			T55	3		T406	1		T742	1
values[96]	40	1			T55	2		T406	1		T742	1
values[97]	49	1			T55	3		T406	1		T742	1
values[98]	46	1			T55	5		T406	1		T742	1
values[99]	46	1			T55	4		T406	1		T742	1
values[100]	61	1			T55	4		T406	1		T742	1
values[101]	50	1			T55	8		T406	1		T742	1
values[102]	46	1			T55	1		T406	1		T742	1
values[103]	52	1			T55	2		T406	1		T742	2
values[104]	47	1			T55	4		T406	1		T742	2
values[105]	50	1			T55	5		T406	1		T742	5
values[106]	62	1			T55	3		T406	1		T742	2
values[107]	58	1			T55	7		T406	1		T742	3
values[108]	54	1			T55	3		T406	1		T742	1
values[109]	66	1			T55	2		T406	1		T742	2
values[110]	55	1			T55	4		T406	1		T742	1
values[111]	56	1			T55	6		T406	1		T742	2
values[112]	53	1			T55	6		T406	1		T742	1
values[113]	60	1			T55	5		T406	1		T742	3
values[114]	43	1			T55	4		T406	1		T742	7
values[115]	56	1			T55	4		T406	1		T742	2
values[116]	70	1			T55	8		T406	2		T742	7
values[117]	58	1			T55	9		T406	1		T742	1
values[118]	58	1			T55	10		T406	3		T742	1
values[119]	53	1			T55	6		T406	2		T742	1
values[120]	56	1			T55	2		T406	1		T742	2
values[121]	72	1			T55	6		T406	2		T742	1
values[122]	72	1			T55	8		T406	3		T742	1
values[123]	81	1			T55	10		T406	1		T742	1
values[124]	129	1			T55	11		T406	2		T742	1
values[125]	305	1			T55	41		T406	1		T742	4
values[126]	572	1			T55	62		T406	13		T742	24
values[127]	1451	1			T55	39		T406	123		T742	145
values[128]	2441	1			T55	3		T406	267		T742	236