Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	138824	1			T32	3		T33	50		T34	5
values[2]	9921	1			T33	3		T55	117		T104	455
values[3]	4014	1			T55	112		T104	175		T105	31
values[4]	2415	1			T55	61		T104	70		T105	12
values[5]	1575	1			T55	60		T104	48		T105	13
values[6]	1135	1			T55	29		T104	42		T105	13
values[7]	811	1			T55	16		T104	33		T105	7
values[8]	584	1			T55	23		T104	38		T105	11
values[9]	497	1			T55	8		T104	51		T105	4
values[10]	457	1			T55	7		T104	50		T105	6
values[11]	370	1			T104	40		T105	4		T573	3
values[12]	320	1			T104	13		T105	3		T573	3
values[13]	344	1			T104	5		T105	15		T573	2
values[14]	318	1			T104	3		T105	4		T573	4
values[15]	339	1			T105	7		T573	3		T742	1
values[16]	338	1			T105	4		T573	5		T742	1
values[17]	302	1			T105	10		T573	3		T742	1
values[18]	254	1			T105	7		T573	7		T742	1
values[19]	273	1			T105	8		T573	2		T742	1
values[20]	328	1			T105	3		T573	3		T742	1
values[21]	299	1			T105	3		T573	2		T742	1
values[22]	286	1			T105	9		T573	2		T742	1
values[23]	239	1			T105	8		T573	2		T742	1
values[24]	267	1			T105	10		T573	6		T742	1
values[25]	276	1			T105	12		T573	5		T742	1
values[26]	260	1			T105	4		T573	1		T742	1
values[27]	253	1			T105	8		T573	1		T742	1
values[28]	281	1			T105	15		T573	3		T742	1
values[29]	291	1			T105	15		T573	2		T742	1
values[30]	255	1			T105	4		T573	2		T742	1
values[31]	247	1			T105	14		T573	1		T742	1
values[32]	266	1			T105	5		T573	5		T742	1
values[33]	200	1			T105	5		T573	3		T742	1
values[34]	235	1			T105	5		T573	8		T742	1
values[35]	243	1			T105	12		T573	3		T742	1
values[36]	239	1			T105	6		T573	3		T742	1
values[37]	236	1			T105	6		T573	1		T742	1
values[38]	238	1			T105	10		T573	2		T742	1
values[39]	244	1			T105	16		T573	2		T742	1
values[40]	273	1			T105	5		T573	2		T742	1
values[41]	206	1			T105	9		T573	1		T742	1
values[42]	197	1			T105	4		T573	2		T742	1
values[43]	223	1			T105	6		T573	1		T742	1
values[44]	214	1			T105	3		T573	4		T742	1
values[45]	243	1			T105	6		T573	7		T742	1
values[46]	242	1			T105	4		T573	7		T742	1
values[47]	270	1			T105	4		T573	2		T742	1
values[48]	255	1			T105	7		T573	1		T742	1
values[49]	251	1			T105	5		T573	3		T742	1
values[50]	241	1			T105	22		T573	1		T742	1
values[51]	222	1			T105	4		T573	2		T742	1
values[52]	246	1			T105	10		T573	1		T742	1
values[53]	194	1			T105	9		T573	2		T742	1
values[54]	207	1			T105	6		T573	1		T742	1
values[55]	220	1			T105	3		T573	3		T742	1
values[56]	186	1			T105	7		T573	3		T742	1
values[57]	215	1			T105	2		T573	12		T742	1
values[58]	202	1			T105	17		T573	10		T742	1
values[59]	166	1			T105	3		T573	11		T742	1
values[60]	175	1			T105	11		T573	3		T742	1
values[61]	177	1			T105	4		T573	6		T742	1
values[62]	151	1			T105	7		T573	1		T742	1
values[63]	147	1			T105	11		T573	5		T742	1
values[64]	115	1			T105	19		T573	1		T742	1
values[65]	134	1			T105	6		T573	2		T742	1
values[66]	138	1			T105	4		T573	1		T742	1
values[67]	177	1			T105	6		T573	5		T742	1
values[68]	131	1			T573	5		T742	1		T739	1
values[69]	103	1			T573	5		T742	1		T739	1
values[70]	120	1			T573	1		T742	1		T739	1
values[71]	132	1			T573	4		T742	1		T739	1
values[72]	154	1			T573	1		T742	1		T739	1
values[73]	129	1			T573	1		T742	1		T739	1
values[74]	178	1			T573	2		T742	1		T739	1
values[75]	146	1			T573	1		T742	1		T739	1
values[76]	117	1			T573	5		T742	1		T739	1
values[77]	100	1			T573	7		T742	1		T739	1
values[78]	92	1			T573	7		T742	1		T739	1
values[79]	84	1			T573	9		T742	1		T739	1
values[80]	94	1			T573	3		T742	1		T739	1
values[81]	81	1			T573	5		T742	1		T739	1
values[82]	81	1			T573	2		T742	1		T739	1
values[83]	90	1			T573	1		T742	1		T739	1
values[84]	100	1			T573	2		T742	1		T739	1
values[85]	92	1			T573	3		T742	2		T739	1
values[86]	122	1			T573	8		T742	1		T739	1
values[87]	108	1			T573	2		T742	1		T739	1
values[88]	88	1			T573	4		T742	1		T739	1
values[89]	74	1			T573	3		T742	1		T739	1
values[90]	76	1			T573	3		T742	1		T739	1
values[91]	88	1			T573	3		T742	1		T739	1
values[92]	79	1			T573	4		T742	1		T739	1
values[93]	78	1			T573	7		T742	1		T739	1
values[94]	86	1			T573	7		T742	1		T739	1
values[95]	94	1			T573	9		T742	2		T739	1
values[96]	84	1			T573	7		T742	2		T739	1
values[97]	94	1			T573	6		T742	4		T739	1
values[98]	86	1			T573	8		T742	1		T739	1
values[99]	80	1			T573	6		T742	1		T739	1
values[100]	91	1			T573	1		T742	2		T739	1
values[101]	82	1			T742	1		T739	1		T756	6
values[102]	91	1			T742	3		T739	1		T756	12
values[103]	104	1			T742	1		T739	2		T756	13
values[104]	75	1			T742	1		T739	1		T756	7
values[105]	74	1			T742	4		T739	3		T756	12
values[106]	75	1			T742	2		T739	3		T756	13
values[107]	79	1			T742	7		T739	1		T756	15
values[108]	82	1			T742	2		T739	2		T756	13
values[109]	68	1			T742	5		T739	1		T756	8
values[110]	65	1			T742	1		T739	2		T756	8
values[111]	86	1			T742	2		T739	1		T756	9
values[112]	58	1			T742	1		T739	2		T756	11
values[113]	54	1			T742	1		T739	1		T756	4
values[114]	54	1			T742	1		T739	1		T756	4
values[115]	64	1			T742	4		T739	4		T756	5
values[116]	76	1			T742	1		T739	1		T756	8
values[117]	76	1			T742	6		T739	3		T756	4
values[118]	56	1			T742	1		T739	1		T756	1
values[119]	99	1			T742	2		T739	1		T756	8
values[120]	87	1			T742	2		T739	6		T756	10
values[121]	79	1			T742	2		T739	4		T756	16
values[122]	54	1			T742	5		T739	1		T756	4
values[123]	46	1			T742	3		T739	1		T756	2
values[124]	50	1			T742	1		T739	1		T764	3
values[125]	63	1			T742	6		T739	1		T764	4
values[126]	120	1			T742	1		T739	3		T764	3
values[127]	520	1			T742	32		T739	44		T764	43
values[128]	3905	1			T742	297		T739	364		T764	300