Unified Coverage Report :: Group Instance : sensor_ctrl

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T32	1	T301	1	T370	1
small_delay	645	1		T33	1	T55	1	T104	1
zero	655	1		T34	1	T56	1	T186	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T301	1	T370	1	T378	1
small_delay	945	1		T32	1	T33	1	T55	1
zero	655	1		T34	1	T56	1	T186	1