Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	462	1			T104	3		T422	1		T573	2
all_values[1]	474	1			T104	1		T105	1		T360	2
all_values[2]	475	1			T55	1		T105	2		T741	1
all_values[3]	494	1			T55	1		T105	1		T360	3
all_values[4]	469	1			T55	1		T104	2		T105	1
all_values[5]	469	1			T104	2		T105	2		T380	1
all_values[6]	489	1			T55	1		T104	1		T105	3
all_values[7]	459	1			T55	1		T104	1		T105	4
all_values[8]	477	1			T55	1		T105	2		T360	2
all_values[9]	445	1			T432	1		T573	4		T788	3
all_values[10]	453	1			T104	1		T105	1		T360	3
all_values[11]	453	1			T55	1		T104	1		T105	3
all_values[12]	471	1			T105	3		T432	1		T422	3
all_values[13]	458	1			T104	3		T105	1		T367	2
all_values[14]	500	1			T104	1		T105	2		T422	4
all_values[15]	436	1			T105	3		T360	1		T432	2
all_values[16]	432	1			T55	1		T104	1		T105	2
all_values[17]	471	1			T105	1		T380	1		T348	1
all_values[18]	411	1			T105	2		T360	1		T730	1
all_values[19]	439	1			T105	3		T348	1		T741	1
all_values[20]	444	1			T105	3		T360	2		T380	1
all_values[21]	463	1			T55	1		T105	3		T360	1
all_values[22]	462	1			T104	1		T105	5		T360	1
all_values[23]	440	1			T105	1		T348	1		T422	2
all_values[24]	446	1			T104	2		T105	1		T360	3
all_values[25]	431	1			T104	2		T360	1		T348	1
all_values[26]	417	1			T55	1		T104	1		T105	4
all_values[27]	479	1			T55	4		T104	3		T105	1
all_values[28]	435	1			T104	2		T105	1		T360	1
all_values[29]	433	1			T104	2		T105	1		T348	1
all_values[30]	452	1			T105	2		T360	2		T348	4
all_values[31]	444	1			T55	1		T104	2		T360	2
all_values[32]	439	1			T104	2		T348	1		T740	1
all_values[33]	469	1			T104	1		T105	2		T730	1
all_values[34]	445	1			T104	1		T105	2		T348	1
all_values[35]	452	1			T55	2		T104	1		T105	1
all_values[36]	453	1			T55	1		T104	1		T360	1
all_values[37]	425	1			T104	2		T740	1		T741	1
all_values[38]	448	1			T105	1		T422	7		T573	4
all_values[39]	483	1			T104	1		T105	3		T360	1
all_values[40]	446	1			T104	2		T105	3		T360	1
all_values[41]	464	1			T380	1		T348	2		T432	1
all_values[42]	481	1			T104	2		T432	1		T422	1
all_values[43]	464	1			T105	1		T360	1		T348	2
all_values[44]	470	1			T104	1		T105	1		T348	1
all_values[45]	458	1			T55	1		T104	4		T105	3
all_values[46]	455	1			T104	2		T105	2		T360	1
all_values[47]	418	1			T55	1		T105	1		T348	1
all_values[48]	487	1			T104	2		T360	1		T730	1
all_values[49]	416	1			T104	2		T105	1		T360	1