Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3390	1			T56	2		T104	1		T105	19
all_values[1]	3397	1			T56	1		T104	2		T105	23
all_values[2]	3325	1			T56	3		T104	3		T105	27
all_values[3]	3275	1			T56	1		T104	6		T105	21
all_values[4]	3369	1			T56	2		T104	5		T105	12
all_values[5]	3454	1			T56	2		T104	2		T105	20
all_values[6]	3388	1			T56	4		T104	1		T105	17
all_values[7]	3335	1			T56	6		T104	5		T105	23
all_values[8]	3319	1			T56	2		T104	2		T105	24
all_values[9]	3358	1			T56	4		T104	8		T105	26
all_values[10]	3263	1			T56	3		T104	7		T105	18
all_values[11]	3302	1			T56	2		T104	2		T105	27
all_values[12]	3377	1			T56	1		T104	4		T105	19
all_values[13]	3359	1			T56	4		T104	2		T105	26
all_values[14]	3390	1			T56	2		T104	2		T105	30
all_values[15]	3336	1			T56	1		T104	3		T105	22
all_values[16]	3405	1			T56	2		T104	5		T105	26
all_values[17]	3327	1			T56	1		T104	2		T105	15
all_values[18]	3295	1			T56	2		T104	1		T105	24
all_values[19]	3350	1			T56	2		T104	5		T105	31
all_values[20]	3368	1			T56	3		T104	6		T105	27
all_values[21]	3346	1			T56	1		T104	4		T105	33
all_values[22]	3306	1			T56	1		T104	5		T105	28
all_values[23]	3308	1			T56	4		T104	2		T105	24
all_values[24]	3373	1			T56	3		T104	2		T105	21
all_values[25]	3391	1			T56	3		T104	6		T105	25
all_values[26]	3307	1			T104	4		T105	18		T360	6
all_values[27]	3198	1			T56	2		T104	6		T105	19
all_values[28]	3355	1			T56	1		T104	4		T105	24
all_values[29]	3305	1			T56	3		T104	3		T105	16
all_values[30]	3374	1			T56	4		T104	4		T105	23
all_values[31]	3310	1			T56	2		T104	4		T105	21
all_values[32]	3394	1			T56	3		T104	6		T105	19
all_values[33]	3327	1			T56	3		T104	3		T105	20
all_values[34]	3255	1			T104	1		T105	21		T360	7
all_values[35]	3412	1			T56	2		T104	3		T105	16
all_values[36]	3376	1			T56	4		T104	4		T105	15
all_values[37]	3359	1			T56	3		T104	1		T105	21
all_values[38]	3323	1			T56	2		T104	5		T105	12
all_values[39]	3371	1			T56	2		T104	7		T105	18
all_values[40]	3285	1			T56	2		T104	6		T105	26
all_values[41]	3335	1			T56	2		T104	6		T105	22
all_values[42]	3425	1			T56	3		T104	3		T105	29
all_values[43]	3362	1			T56	2		T104	6		T105	23
all_values[44]	3362	1			T56	1		T104	2		T105	16
all_values[45]	3364	1			T56	2		T104	4		T105	22
all_values[46]	3451	1			T56	3		T104	4		T105	30
all_values[47]	3384	1			T56	3		T104	2		T105	24
all_values[48]	3312	1			T56	1		T104	6		T105	33
all_values[49]	3367	1			T56	2		T104	4		T105	21
all_values[50]	3398	1			T56	7		T104	7		T105	26
all_values[51]	3435	1			T56	1		T104	7		T105	22
all_values[52]	3344	1			T56	2		T104	3		T105	22
all_values[53]	3359	1			T56	2		T104	5		T105	25
all_values[54]	3301	1			T104	2		T105	22		T360	8
all_values[55]	3337	1			T56	4		T104	3		T105	23
all_values[56]	3406	1			T56	3		T104	5		T105	23
all_values[57]	3390	1			T105	24		T360	5		T368	4
all_values[58]	3274	1			T56	1		T104	4		T105	22
all_values[59]	3319	1			T56	1		T104	2		T105	19
all_values[60]	3339	1			T56	2		T104	5		T105	17
all_values[61]	3287	1			T56	4		T104	2		T105	28
all_values[62]	3282	1			T56	3		T104	2		T105	18
all_values[63]	3367	1			T56	4		T104	4		T105	34