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 LINE       31973
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T56
1	1	Covered	T32,T33,T34

 LINE       31973
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T34,T56
1	1	Covered	T32,T33,T34

 LINE       31973
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T34,T56
1	1	Covered	T32,T33,T34

 LINE       31973
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T56
1	1	Covered	T32,T33,T34

 LINE       31973
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T34,T56
1	1	Covered	T32,T33,T34

 LINE       31973
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T34
1	1	Covered	T32,T33,T34

 LINE       31973
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T34
1	1	Covered	T32,T33,T34

 LINE       31973
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T34
1	1	Covered	T32,T33,T34

 LINE       31973
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T34
1	1	Covered	T32,T33,T34

 LINE       31973
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T56
1	1	Covered	T32,T33,T34

 LINE       31973
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T56
1	1	Covered	T33,T34,T56

 LINE       31973
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T34,T56
1	1	Covered	T32,T33,T34

 LINE       31973
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T34
1	1	Covered	T32,T33,T34

 LINE       31973
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T34
1	1	Covered	T32,T33,T34

 LINE       31973
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T56,T55
1	1	Covered	T33,T34,T56

 LINE       31973
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T34,T56
1	1	Covered	T32,T33,T34

 LINE       31973
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T34,T56
1	1	Covered	T32,T33,T56

 LINE       31973
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T34,T56
1	1	Covered	T32,T33,T34

 LINE       31973
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T56
1	1	Covered	T32,T33,T34

 LINE       31973
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T56,T55
1	1	Covered	T33,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T34
1	1	Covered	T32,T33,T56

 LINE       31973
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T56,T55
1	1	Covered	T33,T34,T56

 LINE       31973
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T34,T56
1	1	Covered	T32,T33,T56

 LINE       31973
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T34
1	1	Covered	T32,T33,T34

 LINE       31973
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T56
1	1	Covered	T33,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T34,T56
1	1	Covered	T32,T33,T56

 LINE       31973
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T34,T56
1	1	Covered	T32,T33,T56

 LINE       31973
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T34
1	1	Covered	T32,T33,T34

 LINE       31973
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T34,T56
1	1	Covered	T32,T33,T34

 LINE       31973
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T34
1	1	Covered	T32,T33,T56

 LINE       31973
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T34,T56
1	1	Covered	T33,T34,T56

 LINE       31973
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T56,T55
1	1	Covered	T33,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T34,T56
1	1	Covered	T56,T55,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T56,T104
1	1	Covered	T33,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T56,T104
1	1	Covered	T33,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T55,T104
1	1	Covered	T32,T33,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T55,T104
1	1	Covered	T56,T55,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T55,T104,T186
1	1	Covered	T33,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T56,T55
1	1	Covered	T33,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T55,T104
1	1	Covered	T33,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T55,T104,T187
1	1	Covered	T56,T55,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T34,T56,T55
1	1	Covered	T33,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T56,T55
1	1	Covered	T33,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[43] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T56,T55
1	1	Covered	T56,T55,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[44] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T56,T55
1	1	Covered	T33,T55,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[45] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T104,T187
1	1	Covered	T33,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[46] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T56,T55
1	1	Covered	T33,T34,T56

 LINE       31973
 SUB-EXPRESSION (addr_hit[47] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T56,T55
1	1	Covered	T32,T34,T56

 LINE       31973
 SUB-EXPRESSION (addr_hit[48] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T55,T104
1	1	Covered	T32,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[49] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T55,T104
1	1	Covered	T32,T33,T56

 LINE       31973
 SUB-EXPRESSION (addr_hit[50] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T56,T55
1	1	Covered	T33,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[51] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T104,T186
1	1	Covered	T56,T55,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[52] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T56,T55
1	1	Covered	T33,T34,T56

 LINE       31973
 SUB-EXPRESSION (addr_hit[53] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T34,T55
1	1	Covered	T33,T34,T56

 LINE       31973
 SUB-EXPRESSION (addr_hit[54] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T55,T104
1	1	Covered	T33,T55,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[55] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T55,T104
1	1	Covered	T33,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[56] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T56,T55
1	1	Covered	T33,T34,T56

 LINE       31973
 SUB-EXPRESSION (addr_hit[57] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T55,T104
1	1	Covered	T33,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[58] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T34,T56
1	1	Covered	T33,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[59] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T55,T104
1	1	Covered	T56,T55,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[60] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T104,T370
1	1	Covered	T33,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[61] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T55,T104
1	1	Covered	T33,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[62] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T104,T186
1	1	Covered	T56,T55,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[63] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T55,T104
1	1	Covered	T33,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[64] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T104,T370
1	1	Covered	T56,T104,T186

 LINE       31973
 SUB-EXPRESSION (addr_hit[65] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T55,T104,T105
1	1	Covered	T33,T56,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[66] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T186,T370
1	1	Covered	T55,T104,T186

 LINE       31973
 SUB-EXPRESSION (addr_hit[67] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T187,T29
1	1	Covered	T33,T104,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[68] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T104,T29
1	1	Covered	T33,T104,T186

 LINE       31973
 SUB-EXPRESSION (addr_hit[69] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T104,T187
1	1	Covered	T32,T33,T56

 LINE       31973
 SUB-EXPRESSION (addr_hit[70] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T29,T105
1	1	Covered	T104,T29,T105

 LINE       31973
 SUB-EXPRESSION (addr_hit[71] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T104,T29
1	1	Covered	T33,T104,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[72] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T104,T186
1	1	Covered	T33,T104,T187

 LINE       31973
 SUB-EXPRESSION (addr_hit[73] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T55,T104
1	1	Covered	T55,T104,T187

 LINE       31973
 SUB-EXPRESSION (addr_hit[74] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T104,T370
1	1	Covered	T56,T104,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[75] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T104,T29
1	1	Covered	T33,T55,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[76] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T104,T105
1	1	Covered	T56,T104,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[77] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T104,T105
1	1	Covered	T56,T104,T186

 LINE       31973
 SUB-EXPRESSION (addr_hit[78] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T56,T104
1	1	Covered	T56,T55,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[79] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T370,T105
1	1	Covered	T56,T104,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[80] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T376,T105
1	1	Covered	T33,T104,T187

 LINE       31973
 SUB-EXPRESSION (addr_hit[81] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T55,T104,T105
1	1	Covered	T33,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[82] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T186,T187
1	1	Covered	T33,T55,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[83] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T370,T105
1	1	Covered	T55,T104,T187

 LINE       31973
 SUB-EXPRESSION (addr_hit[84] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T56,T104
1	1	Covered	T32,T33,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[85] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T186,T187
1	1	Covered	T33,T56,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[86] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T29,T105
1	1	Covered	T55,T104,T187

 LINE       31973
 SUB-EXPRESSION (addr_hit[87] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T104,T301
1	1	Covered	T56,T55,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[88] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T104,T105
1	1	Covered	T56,T104,T301

 LINE       31973
 SUB-EXPRESSION (addr_hit[89] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T186,T187
1	1	Covered	T33,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[90] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T55,T104,T186
1	1	Covered	T32,T33,T56

 LINE       31973
 SUB-EXPRESSION (addr_hit[91] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T187,T105
1	1	Covered	T33,T55,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[92] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T370,T105
1	1	Covered	T33,T104,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[93] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T104,T186
1	1	Covered	T33,T104,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[94] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T55,T104,T364
1	1	Covered	T56,T104,T187

 LINE       31973
 SUB-EXPRESSION (addr_hit[95] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T105,T360
1	1	Covered	T104,T29,T370

 LINE       31973
 SUB-EXPRESSION (addr_hit[96] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T104,T186
1	1	Covered	T55,T104,T186

 LINE       31973
 SUB-EXPRESSION (addr_hit[97] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T186,T105
1	1	Covered	T33,T34,T56

 LINE       31973
 SUB-EXPRESSION (addr_hit[98] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T55,T104,T105
1	1	Covered	T33,T104,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[99] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T187,T370
1	1	Covered	T104,T29,T364

 LINE       31973
 SUB-EXPRESSION (addr_hit[100] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T104,T105
1	1	Covered	T33,T55,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[101] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T55,T104,T186
1	1	Covered	T104,T187,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[102] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T104,T105
1	1	Covered	T56,T104,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[103] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T104,T187
1	1	Covered	T33,T56,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[104] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T105,T360
1	1	Covered	T56,T104,T186

 LINE       31973
 SUB-EXPRESSION (addr_hit[105] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T56,T104
1	1	Covered	T32,T33,T56

 LINE       31973
 SUB-EXPRESSION (addr_hit[106] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T186,T370
1	1	Covered	T56,T55,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[107] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T104,T187
1	1	Covered	T32,T33,T56

 LINE       31973
 SUB-EXPRESSION (addr_hit[108] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T364,T105
1	1	Covered	T33,T56,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[109] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T55,T104,T187
1	1	Covered	T104,T186,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[110] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T301,T187
1	1	Covered	T56,T104,T186

 LINE       31973
 SUB-EXPRESSION (addr_hit[111] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T104,T105
1	1	Covered	T33,T56,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[112] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T104,T187
1	1	Covered	T55,T104,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[113] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T56,T104
1	1	Covered	T33,T104,T187

 LINE       31973
 SUB-EXPRESSION (addr_hit[114] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T186,T187
1	1	Covered	T33,T56,T55

 LINE       31973
 SUB-EXPRESSION (addr_hit[115] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T186,T187
1	1	Covered	T104,T186,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[116] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T186,T187
1	1	Covered	T56,T104,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[117] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T186,T187
1	1	Covered	T33,T56,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[118] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T105,T378
1	1	Covered	T55,T104,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[119] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T56,T104
1	1	Covered	T33,T56,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[120] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T104,T186
1	1	Covered	T34,T56,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[121] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T56
1	1	Covered	T56,T104,T187

 LINE       31973
 SUB-EXPRESSION (addr_hit[122] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T55,T104,T187
1	1	Covered	T56,T104,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[123] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T104,T187
1	1	Covered	T33,T55,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[124] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T187,T105
1	1	Covered	T56,T104,T187

 LINE       31973
 SUB-EXPRESSION (addr_hit[125] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T55,T104,T186
1	1	Covered	T33,T56,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[126] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T105,T360
1	1	Covered	T33,T55,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[127] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T186,T187
1	1	Covered	T33,T56,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[128] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T29,T105
1	1	Covered	T33,T55,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[129] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T104,T29
1	1	Covered	T56,T104,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[130] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T104,T187
1	1	Covered	T33,T56,T104

 LINE       31973
 SUB-EXPRESSION (addr_hit[131] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T29,T105
1	1	Covered	T55,T104,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[132] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T29,T105
1	1	Covered	T56,T104,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[133] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T55,T187,T105
1	1	Covered	T56,T104,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[134] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T105,T361
1	1	Covered	T33,T104,T187

 LINE       31973
 SUB-EXPRESSION (addr_hit[135] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T104,T360
1	1	Covered	T104,T29,T105

 LINE       31973
 SUB-EXPRESSION (addr_hit[136] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T104,T370
1	1	Covered	T55,T104,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[137] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T104,T370,T105
1	1	Covered	T33,T104,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[138] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T33,T104,T186
1	1	Covered	T56,T104,T29

 LINE       31973
 SUB-EXPRESSION (addr_hit[139] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T56,T104,T187
1	1	Covered	T33,T56,T104