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LINE 31786
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T44,T8 |
LINE 31787
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T44,T8 |
LINE 31788
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T44,T8 |
LINE 31789
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T44,T8 |
LINE 31790
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T44,T8 |
LINE 31791
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31792
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31793
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31794
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31795
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31796
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31797
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31798
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31799
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31800
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31801
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31802
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31803
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31804
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31805
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31806
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31807
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31808
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31809
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31810
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31811
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31812
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31813
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31814
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31815
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31816
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31817
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31818
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31819
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31820
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31821
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31822
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31823
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31824
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31825
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31826
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31827
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31828
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31829
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31830
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T44,T8 |
LINE 31831
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T44,T8 |
LINE 31832
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T44,T8 |
LINE 31833
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T44,T8 |
LINE 31834
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T44,T8 |
LINE 31835
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T44,T8 |
LINE 31836
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T44,T8 |
LINE 31837
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T44,T8 |
LINE 31838
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31839
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31840
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31841
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31842
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31843
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31844
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31845
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31846
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31847
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31848
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31849
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31850
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31851
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31852
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31853
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31854
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31855
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31856
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31857
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31858
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31859
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31860
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31861
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31862
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31863
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31864
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31865
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31866
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31867
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31868
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31869
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31870
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31871
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31872
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31873
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31874
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31875
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31876
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31877
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T258 |
LINE 31878
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31879
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31880
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31881
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31882
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31883
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31884
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31885
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31886
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31887
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31888
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET)
---------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31889
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET)
---------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31890
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET)
---------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31891
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET)
---------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31892
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET)
---------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31893
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET)
---------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31894
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31895
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31896
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31897
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31898
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31899
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31900
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31901
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31902
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T8,T9 |
LINE 31903
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T105,T8 |
LINE 31904
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T105,T8 |
LINE 31905
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T105,T8 |
LINE 31906
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T105,T8 |
LINE 31907
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T105,T8 |
LINE 31908
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T105,T8 |
LINE 31909
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T7,T105,T8 |
LINE 31910
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31911
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T21,T59,T62 |
LINE 31912
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T21,T59,T62 |
LINE 31913
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T21,T62,T60 |
LINE 31914
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T60,T170,T368 |
LINE 31915
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T21,T62,T75 |
LINE 31916
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T21,T62,T75 |
LINE 31917
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T21,T62,T75 |
LINE 31918
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T75,T60,T170 |
LINE 31919
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T60,T170,T368 |
LINE 31920
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T60,T170,T368 |
LINE 31921
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T60,T170,T368 |
LINE 31922
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T60,T170,T368 |
LINE 31923
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T60,T170,T368 |
LINE 31924
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T60,T170,T368 |
LINE 31925
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T60,T170,T368 |
LINE 31926
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T60,T170,T368 |
LINE 31927
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31928
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31929
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31930
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31931
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31932
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31933
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31934
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_0_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31935
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_1_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31936
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_2_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31937
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_3_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31938
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_4_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31939
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_5_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31940
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_6_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31941
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_7_OFFSET)
-------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31942
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_0_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31943
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_1_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31944
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_2_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31945
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_3_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31946
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_4_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31947
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_5_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31948
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_6_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31949
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_7_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31950
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31951
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31952
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31953
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31954
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31955
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31956
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31957
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31958
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31959
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31960
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31961
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31962
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31963
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31964
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31965
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET)
---------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31966
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_CAUSE_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31969
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 31969
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 31973
EXPRESSION
Number Term
1 reg_we &
2 ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1 & (~reg_be))))) | (addr_hit[37] & ((|(4'b1 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1 & (~reg_be))))) | (addr_hit[42] & ((|(4'b1 & (~reg_be))))) | (addr_hit[43] & ((|(4'b1 & (~reg_be))))) | (addr_hit[44] & ((|(4'b1 & (~reg_be))))) | (addr_hit[45] & ((|(4'b1 & (~reg_be))))) | (addr_hit[46] & ((|(4'b1 & (~reg_be))))) | (addr_hit[47] & ((|(4'b1 & (~reg_be))))) | (addr_hit[48] & ((|(4'b1 & (~reg_be))))) | (addr_hit[49] & ((|(4'b1 & (~reg_be))))) | (addr_hit[50] & ((|(4'b1 & (~reg_be))))) | (addr_hit[51] & ((|(4'b1 & (~reg_be))))) | (addr_hit[52] & ((|(4'b1 & (~reg_be))))) | (addr_hit[53] & ((|(4'b1 & (~reg_be))))) | (addr_hit[54] & ((|(4'b1 & (~reg_be))))) | (addr_hit[55] & ((|(4'b1 & (~reg_be))))) | (addr_hit[56] & ((|(4'b1 & (~reg_be))))) | (addr_hit[57] & ((|(4'b1 & (~reg_be))))) | (addr_hit[58] & ((|(4'b1 & (~reg_be))))) | (addr_hit[59] & ((|(4'b1 & (~reg_be))))) | (addr_hit[60] & ((|(4'b1 & (~reg_be))))) | (addr_hit[61] & ((|(4'b1 & (~reg_be))))) | (addr_hit[62] & ((|(4'b1 & (~reg_be))))) | (addr_hit[63] & ((|(4'b1 & (~reg_be))))) | (addr_hit[64] & ((|(4'b1 & (~reg_be))))) | (addr_hit[65] & ((|(4'b1 & (~reg_be))))) | (addr_hit[66] & ((|(4'b1 & (~reg_be))))) | (addr_hit[67] & ((|(4'b1 & (~reg_be))))) | (addr_hit[68] & ((|(4'b1 & (~reg_be))))) | (addr_hit[69] & ((|(4'b1 & (~reg_be))))) | (addr_hit[70] & ((|(4'b1 & (~reg_be))))) | (addr_hit[71] & ((|(4'b1 & (~reg_be))))) | (addr_hit[72] & ((|(4'b1 & (~reg_be))))) | (addr_hit[73] & ((|(4'b1 & (~reg_be))))) | (addr_hit[74] & ((|(4'b1 & (~reg_be))))) | (addr_hit[75] & ((|(4'b1 & (~reg_be))))) | (addr_hit[76] & ((|(4'b1 & (~reg_be))))) | (addr_hit[77] & ((|(4'b1 & (~reg_be))))) | (addr_hit[78] & ((|(4'b1 & (~reg_be))))) | (addr_hit[79] & ((|(4'b1 & (~reg_be))))) | (addr_hit[80] & ((|(4'b1 & (~reg_be))))) | (addr_hit[81] & ((|(4'b1 & (~reg_be))))) | (addr_hit[82] & ((|(4'b1 & (~reg_be))))) | (addr_hit[83] & ((|(4'b1 & (~reg_be))))) | (addr_hit[84] & ((|(4'b1 & (~reg_be))))) | (addr_hit[85] & ((|(4'b1 & (~reg_be))))) | (addr_hit[86] & ((|(4'b1 & (~reg_be))))) | (addr_hit[87] & ((|(4'b1 & (~reg_be))))) | (addr_hit[88] & ((|(4'b1 & (~reg_be))))) | (addr_hit[89] & ((|(4'b1 & (~reg_be))))) | (addr_hit[90] & ((|(4'b1 & (~reg_be))))) | (addr_hit[91] & ((|(4'b1 & (~reg_be))))) | (addr_hit[92] & ((|(4'b1 & (~reg_be))))) | (addr_hit[93] & ((|(4'b1 & (~reg_be))))) | (addr_hit[94] & ((|(4'b1 & (~reg_be))))) | (addr_hit[95] & ((|(4'b1 & (~reg_be))))) | (addr_hit[96] & ((|(4'b1 & (~reg_be))))) | (addr_hit[97] & ((|(4'b1 & (~reg_be))))) | (addr_hit[98] & ((|(4'b1 & (~reg_be))))) | (addr_hit[99] & ((|(4'b1 & (~reg_be))))) | (addr_hit[100] & ((|(4'b1 & (~reg_be))))) | (addr_hit[101] & ((|(4'b1 & (~reg_be))))) | (addr_hit[102] & ((|(4'b1 & (~reg_be))))) | (addr_hit[103] & ((|(4'b1 & (~reg_be))))) | (addr_hit[104] & ((|(4'b1 & (~reg_be))))) | (addr_hit[105] & ((|(4'b1 & (~reg_be))))) | (addr_hit[106] & ((|(4'b1 & (~reg_be))))) | (addr_hit[107] & ((|(4'b1 & (~reg_be))))) | (addr_hit[108] & ((|(4'b1 & (~reg_be))))) | (addr_hit[109] & ((|(4'b1 & (~reg_be))))) | (addr_hit[110] & ((|(4'b1 & (~reg_be))))) | (addr_hit[111] & ((|(4'b1 & (~reg_be))))) | (addr_hit[112] & ((|(4'b1 & (~reg_be))))) | (addr_hit[113] & ((|(4'b1 & (~reg_be))))) | (addr_hit[114] & ((|(4'b1 & (~reg_be))))) | (addr_hit[115] & ((|(4'b1 & (~reg_be))))) | (addr_hit[116] & ((|(4'b1 & (~reg_be))))) | (addr_hit[117] & ((|(4'b1 & (~reg_be))))) | (addr_hit[118] & ((|(4'b1 & (~reg_be))))) | (addr_hit[119] & ((|(4'b1 & (~reg_be))))) | (addr_hit[120] & ((|(4'b1 & (~reg_be))))) | (addr_hit[121] & ((|(4'b1 & (~reg_be))))) | (addr_hit[122] & ((|(4'b1 & (~reg_be))))) | (addr_hit[123] & ((|(4'b1 & (~reg_be))))) | (addr_hit[124] & ((|(4'b1 & (~reg_be))))) | (addr_hit[125] & ((|(4'b1 & (~reg_be))))) | (addr_hit[126] & ((|(4'b1 & (~reg_be))))) | (addr_hit[127] & ((|(4'b1 & (~reg_be))))) | (addr_hit[128] & ((|(4'b1 & (~reg_be))))) | (addr_hit[129] & ((|(4'b1 & (~reg_be))))) | (addr_hit[130] & ((|(4'b1 & (~reg_be))))) | (addr_hit[131] & ((|(4'b1 & (~reg_be))))) | (addr_hit[132] & ((|(4'b1 & (~reg_be))))) | (addr_hit[133] & ((|(4'b1 & (~reg_be))))) | (addr_hit[134] & ((|(4'b1 & (~reg_be))))) | (addr_hit[135] & ((|(4'b1 & (~reg_be))))) | (addr_hit[136] & ((|(4'b1 & (~reg_be))))) | (addr_hit[137] & ((|(4'b1 & (~reg_be))))) | (addr_hit[138] & ((|(4'b1 & (~reg_be))))) | (addr_hit[139] & ((|(4'b1 & (~reg_be))))) | (addr_hit[140] & ((|(4'b1 & (~reg_be))))) | (addr_hit[141] & ((|(4'b1 & (~reg_be))))) | (addr_hit[142] & ((|(4'b1 & (~reg_be))))) | (addr_hit[143] & ((|(4'b1 & (~reg_be))))) | (addr_hit[144] & ((|(4'b1 & (~reg_be))))) | (addr_hit[145] & ((|(4'b1 & (~reg_be))))) | (addr_hit[146] & ((|(4'b1 & (~reg_be))))) | (addr_hit[147] & ((|(4'b1 & (~reg_be))))) | (addr_hit[148] & ((|(4'b1 & (~reg_be))))) | (addr_hit[149] & ((|(4'b1 & (~reg_be))))) | (addr_hit[150] & ((|(4'b1 & (~reg_be))))) | (addr_hit[151] & ((|(4'b1 & (~reg_be))))) | (addr_hit[152] & ((|(4'b1 & (~reg_be))))) | (addr_hit[153] & ((|(4'b1 & (~reg_be))))) | (addr_hit[154] & ((|(4'b1 & (~reg_be))))) | (addr_hit[155] & ((|(4'b1 & (~reg_be))))) | (addr_hit[156] & ((|(4'b1 & (~reg_be))))) | (addr_hit[157] & ((|(4'b1 & (~reg_be))))) | (addr_hit[158] & ((|(4'b1 & (~reg_be))))) | (addr_hit[159] & ((|(4'b1 & (~reg_be))))) | (addr_hit[160] & ((|(4'b1 & (~reg_be))))) | (addr_hit[161] & ((|(4'b1 & (~reg_be))))) | (addr_hit[162] & ((|(4'b1 & (~reg_be))))) | (addr_hit[163] & ((|(4'b1 & (~reg_be))))) | (addr_hit[164] & ((|(4'b1 & (~reg_be))))) | (addr_hit[165] & ((|(4'b1 & (~reg_be))))) | (addr_hit[166] & ((|(4'b1 & (~reg_be))))) | (addr_hit[167] & ((|(4'b1 & (~reg_be))))) | (addr_hit[168] & ((|(4'b1 & (~reg_be))))) | (addr_hit[169] & ((|(4'b1 & (~reg_be))))) | (addr_hit[170] & ((|(4'b1 & (~reg_be))))) | (addr_hit[171] & ((|(4'b1 & (~reg_be))))) | (addr_hit[172] & ((|(4'b1 & (~reg_be))))) | (addr_hit[173] & ((|(4'b1 & (~reg_be))))) | (addr_hit[174] & ((|(4'b1 & (~reg_be))))) | (addr_hit[175] & ((|(4'b1 & (~reg_be))))) | (addr_hit[176] & ((|(4'b1 & (~reg_be))))) | (addr_hit[177] & ((|(4'b1 & (~reg_be))))) | (addr_hit[178] & ((|(4'b1 & (~reg_be))))) | (addr_hit[179] & ((|(4'b1 & (~reg_be))))) | (addr_hit[180] & ((|(4'b1 & (~reg_be))))) | (addr_hit[181] & ((|(4'b1 & (~reg_be))))) | (addr_hit[182] & ((|(4'b1 & (~reg_be))))) | (addr_hit[183] & ((|(4'b1 & (~reg_be))))) | (addr_hit[184] & ((|(4'b1 & (~reg_be))))) | (addr_hit[185] & ((|(4'b1 & (~reg_be))))) | (addr_hit[186] & ((|(4'b1 & (~reg_be))))) | (addr_hit[187] & ((|(4'b1 & (~reg_be))))) | (addr_hit[188] & ((|(4'b1 & (~reg_be))))) | (addr_hit[189] & ((|(4'b1 & (~reg_be))))) | (addr_hit[190] & ((|(4'b1 & (~reg_be))))) | (addr_hit[191] & ((|(4'b1 & (~reg_be))))) | (addr_hit[192] & ((|(4'b1 & (~reg_be))))) | (addr_hit[193] & ((|(4'b1 & (~reg_be))))) | (addr_hit[194] & ((|(4'b1 & (~reg_be))))) | (addr_hit[195] & ((|(4'b1 & (~reg_be))))) | (addr_hit[196] & ((|(4'b1 & (~reg_be))))) | (addr_hit[197] & ((|(4'b1 & (~reg_be))))) | (addr_hit[198] & ((|(4'b1 & (~reg_be))))) | (addr_hit[199] & ((|(4'b1 & (~reg_be))))) | (addr_hit[200] & ((|(4'b1 & (~reg_be))))) | (addr_hit[201] & ((|(4'b1 & (~reg_be))))) | (addr_hit[202] & ((|(4'b1 & (~reg_be))))) | (addr_hit[203] & ((|(4'b1 & (~reg_be))))) | (addr_hit[204] & ((|(4'b1 & (~reg_be))))) | (addr_hit[205] & ((|(4'b1 & (~reg_be))))) | (addr_hit[206] & ((|(4'b1 & (~reg_be))))) | (addr_hit[207] & ((|(4'b1 & (~reg_be))))) | (addr_hit[208] & ((|(4'b1 & (~reg_be))))) | (addr_hit[209] & ((|(4'b1 & (~reg_be))))) | (addr_hit[210] & ((|(4'b1 & (~reg_be))))) | (addr_hit[211] & ((|(4'b1 & (~reg_be))))) | (addr_hit[212] & ((|(4'b1 & (~reg_be))))) | (addr_hit[213] & ((|(4'b1 & (~reg_be))))) | (addr_hit[214] & ((|(4'b1 & (~reg_be))))) | (addr_hit[215] & ((|(4'b1 & (~reg_be))))) | (addr_hit[216] & ((|(4'b1 & (~reg_be))))) | (addr_hit[217] & ((|(4'b1 & (~reg_be))))) | (addr_hit[218] & ((|(4'b1 & (~reg_be))))) | (addr_hit[219] & ((|(4'b1 & (~reg_be))))) | (addr_hit[220] & ((|(4'b1 & (~reg_be))))) | (addr_hit[221] & ((|(4'b1 & (~reg_be))))) | (addr_hit[222] & ((|(4'b1 & (~reg_be))))) | (addr_hit[223] & ((|(4'b1 & (~reg_be))))) | (addr_hit[224] & ((|(4'b1 & (~reg_be))))) | (addr_hit[225] & ((|(4'b1 & (~reg_be))))) | (addr_hit[226] & ((|(4'b1 & (~reg_be))))) | (addr_hit[227] & ((|(4'b1 & (~reg_be))))) | (addr_hit[228] & ((|(4'b1 & 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(addr_hit[564] & ((|(4'b1 & (~reg_be))))) | (addr_hit[565] & ((|(4'b1 & (~reg_be))))) | (addr_hit[566] & ((|(4'b1 & (~reg_be))))) | (addr_hit[567] & ((|(4'b1 & (~reg_be)))))))
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Not Covered | |