| SCORE |
LINE |
COND |
TOGGLE |
FSM |
BRANCH |
ASSERT |
GROUP |
|
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
| 41.63 |
41.63 |
45.64 |
45.64 |
43.18 |
43.18 |
32.22 |
32.22 |
|
|
58.31 |
58.31 |
63.15 |
63.15 |
7.25 |
7.25 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2379218467 |
| 52.26 |
10.64 |
46.78 |
1.14 |
45.58 |
2.40 |
38.76 |
6.54 |
|
|
60.00 |
1.69 |
63.33 |
0.19 |
59.12 |
51.87 |
/workspace/coverage/default/2.chip_sw_alert_test.1510830379 |
| 58.51 |
6.25 |
60.09 |
13.31 |
52.73 |
7.15 |
44.65 |
5.88 |
|
|
63.91 |
3.90 |
63.33 |
0.00 |
66.37 |
7.25 |
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2042721396 |
| 64.22 |
5.70 |
70.86 |
10.77 |
63.41 |
10.68 |
46.91 |
2.26 |
|
|
74.41 |
10.50 |
63.33 |
0.00 |
66.37 |
0.00 |
/workspace/coverage/default/1.chip_jtag_csr_rw.779085221 |
| 67.66 |
3.44 |
70.86 |
0.00 |
63.41 |
0.00 |
67.56 |
20.65 |
|
|
74.41 |
0.00 |
63.33 |
0.00 |
66.37 |
0.00 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.882421493 |
| 70.23 |
2.57 |
77.02 |
6.17 |
66.88 |
3.47 |
68.30 |
0.75 |
|
|
79.47 |
5.06 |
63.33 |
0.00 |
66.37 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.3027288926 |
| 72.45 |
2.21 |
80.04 |
3.02 |
71.73 |
4.85 |
68.39 |
0.09 |
|
|
84.62 |
5.16 |
63.52 |
0.19 |
66.37 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2303287723 |
| 73.84 |
1.39 |
81.57 |
1.53 |
72.55 |
0.82 |
73.38 |
4.99 |
|
|
85.26 |
0.63 |
63.89 |
0.37 |
66.37 |
0.00 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.1389325695 |
| 75.22 |
1.39 |
84.03 |
2.46 |
74.65 |
2.10 |
74.73 |
1.35 |
|
|
87.66 |
2.40 |
63.89 |
0.00 |
66.37 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.2803996446 |
| 76.44 |
1.22 |
85.19 |
1.16 |
75.54 |
0.89 |
75.04 |
0.31 |
|
|
88.71 |
1.05 |
67.78 |
3.89 |
66.37 |
0.00 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.216044051 |
| 77.48 |
1.05 |
86.24 |
1.05 |
76.08 |
0.55 |
75.06 |
0.02 |
|
|
89.30 |
0.58 |
71.85 |
4.07 |
66.37 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3678151429 |
| 78.25 |
0.77 |
86.27 |
0.03 |
76.08 |
0.00 |
79.65 |
4.59 |
|
|
89.30 |
0.00 |
71.85 |
0.00 |
66.37 |
0.00 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.176471645 |
| 78.92 |
0.67 |
87.46 |
1.19 |
77.08 |
1.00 |
80.31 |
0.66 |
|
|
90.45 |
1.15 |
71.85 |
0.00 |
66.37 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.3063533628 |
| 79.49 |
0.57 |
87.79 |
0.33 |
77.55 |
0.47 |
80.33 |
0.02 |
|
|
90.86 |
0.41 |
74.07 |
2.22 |
66.37 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.373964562 |
| 79.99 |
0.49 |
88.05 |
0.26 |
77.81 |
0.27 |
80.34 |
0.01 |
|
|
91.06 |
0.21 |
76.30 |
2.22 |
66.37 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3412547145 |
| 80.42 |
0.43 |
88.09 |
0.04 |
77.84 |
0.03 |
81.07 |
0.74 |
|
|
91.10 |
0.03 |
76.48 |
0.19 |
67.91 |
1.54 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1031411378 |
| 80.68 |
0.26 |
88.10 |
0.01 |
77.84 |
0.00 |
81.75 |
0.67 |
|
|
91.10 |
0.00 |
76.48 |
0.00 |
68.79 |
0.88 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1096093649 |
| 80.92 |
0.25 |
88.39 |
0.29 |
78.29 |
0.46 |
82.49 |
0.75 |
|
|
91.10 |
0.00 |
76.48 |
0.00 |
68.79 |
0.00 |
/workspace/coverage/default/0.chip_jtag_csr_rw.2966608434 |
| 81.15 |
0.23 |
88.86 |
0.47 |
78.49 |
0.20 |
82.79 |
0.29 |
|
|
91.27 |
0.18 |
76.48 |
0.00 |
69.01 |
0.22 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2246204232 |
| 81.35 |
0.20 |
88.97 |
0.11 |
78.57 |
0.08 |
82.82 |
0.03 |
|
|
91.35 |
0.08 |
77.41 |
0.93 |
69.01 |
0.00 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.4043769937 |
| 81.55 |
0.20 |
88.98 |
0.01 |
78.58 |
0.01 |
84.00 |
1.18 |
|
|
91.35 |
0.00 |
77.41 |
0.00 |
69.01 |
0.00 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.2667936474 |
| 81.73 |
0.17 |
88.98 |
0.00 |
78.58 |
0.00 |
85.03 |
1.03 |
|
|
91.35 |
0.00 |
77.41 |
0.00 |
69.01 |
0.00 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.630416500 |
| 81.89 |
0.17 |
89.21 |
0.23 |
78.91 |
0.33 |
85.46 |
0.43 |
|
|
91.35 |
0.00 |
77.41 |
0.00 |
69.01 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2219989735 |
| 82.04 |
0.15 |
89.26 |
0.05 |
79.30 |
0.39 |
85.46 |
0.00 |
|
|
91.78 |
0.43 |
77.41 |
0.00 |
69.01 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.42140363 |
| 82.16 |
0.12 |
89.28 |
0.01 |
79.32 |
0.02 |
85.95 |
0.49 |
|
|
91.79 |
0.01 |
77.41 |
0.00 |
69.23 |
0.22 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3919102723 |
| 82.28 |
0.12 |
89.44 |
0.16 |
79.39 |
0.07 |
85.95 |
0.01 |
|
|
91.86 |
0.07 |
77.59 |
0.19 |
69.45 |
0.22 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1182365441 |
| 82.38 |
0.10 |
89.48 |
0.04 |
79.43 |
0.04 |
86.24 |
0.29 |
|
|
91.89 |
0.03 |
77.59 |
0.00 |
69.67 |
0.22 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2661763248 |
| 82.48 |
0.10 |
89.48 |
0.00 |
79.43 |
0.00 |
86.82 |
0.57 |
|
|
91.89 |
0.00 |
77.59 |
0.00 |
69.67 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.253841759 |
| 82.57 |
0.09 |
89.93 |
0.45 |
79.48 |
0.05 |
86.87 |
0.06 |
|
|
91.89 |
0.00 |
77.59 |
0.00 |
69.67 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2011539799 |
| 82.66 |
0.09 |
89.93 |
0.00 |
79.48 |
0.00 |
87.38 |
0.51 |
|
|
91.89 |
0.00 |
77.59 |
0.00 |
69.67 |
0.00 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.22984586 |
| 82.74 |
0.08 |
89.94 |
0.01 |
79.50 |
0.02 |
87.40 |
0.02 |
|
|
91.92 |
0.03 |
77.78 |
0.19 |
69.89 |
0.22 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.1572938080 |
| 82.81 |
0.08 |
89.94 |
0.00 |
79.50 |
0.00 |
87.86 |
0.45 |
|
|
91.92 |
0.00 |
77.78 |
0.00 |
69.89 |
0.00 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2030601291 |
| 82.89 |
0.07 |
89.94 |
0.01 |
79.51 |
0.01 |
87.86 |
0.01 |
|
|
91.92 |
0.01 |
77.96 |
0.19 |
70.11 |
0.22 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.964098597 |
| 82.96 |
0.07 |
89.95 |
0.01 |
79.52 |
0.01 |
87.87 |
0.01 |
|
|
91.93 |
0.01 |
78.15 |
0.19 |
70.33 |
0.22 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.1899992526 |
| 83.03 |
0.07 |
89.95 |
0.01 |
79.71 |
0.19 |
87.87 |
0.00 |
|
|
92.15 |
0.22 |
78.15 |
0.00 |
70.33 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2225978534 |
| 83.09 |
0.07 |
90.02 |
0.07 |
79.81 |
0.10 |
87.90 |
0.03 |
|
|
92.17 |
0.03 |
78.33 |
0.19 |
70.33 |
0.00 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2249548213 |
| 83.16 |
0.07 |
90.02 |
0.00 |
79.81 |
0.00 |
88.08 |
0.18 |
|
|
92.17 |
0.00 |
78.33 |
0.00 |
70.55 |
0.22 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1699764084 |
| 83.21 |
0.05 |
90.07 |
0.05 |
79.82 |
0.01 |
88.12 |
0.04 |
|
|
92.17 |
0.00 |
78.33 |
0.00 |
70.77 |
0.22 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2036030453 |
| 83.26 |
0.05 |
90.07 |
0.00 |
79.82 |
0.00 |
88.18 |
0.06 |
|
|
92.17 |
0.00 |
78.33 |
0.00 |
70.99 |
0.22 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.3682567064 |
| 83.30 |
0.04 |
90.07 |
0.00 |
79.82 |
0.00 |
88.20 |
0.02 |
|
|
92.17 |
0.00 |
78.33 |
0.00 |
71.21 |
0.22 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.3470616037 |
| 83.34 |
0.04 |
90.16 |
0.09 |
79.90 |
0.08 |
88.26 |
0.06 |
|
|
92.17 |
0.00 |
78.33 |
0.00 |
71.21 |
0.00 |
/workspace/coverage/default/0.chip_sw_gpio.2382764971 |
| 83.38 |
0.04 |
90.20 |
0.04 |
79.91 |
0.01 |
88.42 |
0.16 |
|
|
92.19 |
0.02 |
78.33 |
0.00 |
71.21 |
0.00 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2410312843 |
| 83.42 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.01 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
71.43 |
0.22 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.1938057400 |
| 83.45 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
71.65 |
0.22 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.1700719393 |
| 83.49 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
71.87 |
0.22 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1131471929 |
| 83.53 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
72.09 |
0.22 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.2156442364 |
| 83.56 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
72.31 |
0.22 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2481268365 |
| 83.60 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
72.53 |
0.22 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.1895147235 |
| 83.64 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
72.75 |
0.22 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.710943109 |
| 83.67 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
72.97 |
0.22 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.1600744656 |
| 83.71 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
73.19 |
0.22 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.161520880 |
| 83.75 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
73.41 |
0.22 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.2450796471 |
| 83.78 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
73.63 |
0.22 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3230447277 |
| 83.82 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
73.85 |
0.22 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2179744779 |
| 83.86 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
74.07 |
0.22 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.2575879210 |
| 83.89 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
74.29 |
0.22 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.883859340 |
| 83.93 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
74.51 |
0.22 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.95678510 |
| 83.96 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
74.73 |
0.22 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3838490738 |
| 84.00 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
74.95 |
0.22 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.16041625 |
| 84.04 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
75.16 |
0.22 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.4170317685 |
| 84.07 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
75.38 |
0.22 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.174805589 |
| 84.11 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
75.60 |
0.22 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3270171907 |
| 84.15 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
75.82 |
0.22 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3799953929 |
| 84.18 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
76.04 |
0.22 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.103031026 |
| 84.22 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
76.26 |
0.22 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3793066223 |
| 84.26 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
76.48 |
0.22 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2687371479 |
| 84.29 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
76.70 |
0.22 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.3678194910 |
| 84.33 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
76.92 |
0.22 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.1838391994 |
| 84.37 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
77.14 |
0.22 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1451678723 |
| 84.40 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
77.36 |
0.22 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.2339530614 |
| 84.44 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
77.58 |
0.22 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.328782418 |
| 84.48 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
77.80 |
0.22 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.511284641 |
| 84.51 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
78.02 |
0.22 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2076636104 |
| 84.55 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
78.24 |
0.22 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.3064222226 |
| 84.59 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
78.46 |
0.22 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2205548241 |
| 84.62 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
78.68 |
0.22 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.4014840383 |
| 84.66 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
78.90 |
0.22 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.1865286192 |
| 84.70 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
79.12 |
0.22 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2676023172 |
| 84.73 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
79.34 |
0.22 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2305636000 |
| 84.77 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
79.56 |
0.22 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3589350163 |
| 84.81 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
79.78 |
0.22 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.1470703052 |
| 84.84 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
80.00 |
0.22 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1131890078 |
| 84.88 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
80.22 |
0.22 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.1744005990 |
| 84.92 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
80.44 |
0.22 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.279001849 |
| 84.95 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
80.66 |
0.22 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.4180442893 |
| 84.99 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
80.88 |
0.22 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.4181989218 |
| 85.03 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
81.10 |
0.22 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.247381442 |
| 85.06 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
81.32 |
0.22 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.914025615 |
| 85.10 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
81.54 |
0.22 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2218531128 |
| 85.14 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
81.76 |
0.22 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2132454599 |
| 85.17 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
81.98 |
0.22 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1547423082 |
| 85.21 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
82.20 |
0.22 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.2012726788 |
| 85.25 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
82.42 |
0.22 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.825840988 |
| 85.28 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
82.64 |
0.22 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.36418727 |
| 85.32 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
82.86 |
0.22 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.625024414 |
| 85.36 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
83.08 |
0.22 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1638396094 |
| 85.39 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
83.30 |
0.22 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3224129440 |
| 85.43 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
83.52 |
0.22 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1816688377 |
| 85.47 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
83.74 |
0.22 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.4227912698 |
| 85.50 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
83.96 |
0.22 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.3892172647 |
| 85.54 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
84.18 |
0.22 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2736478143 |
| 85.58 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
84.40 |
0.22 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2607476524 |
| 85.61 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.42 |
0.00 |
|
|
92.19 |
0.00 |
78.33 |
0.00 |
84.62 |
0.22 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.50146133 |
| 85.65 |
0.04 |
90.20 |
0.00 |
79.91 |
0.00 |
88.46 |
0.03 |
|
|
92.19 |
0.00 |
78.52 |
0.19 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.4049690631 |
| 85.69 |
0.04 |
90.23 |
0.03 |
79.93 |
0.02 |
88.62 |
0.17 |
|
|
92.19 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_power_idle_load.1779641775 |
| 85.72 |
0.03 |
90.23 |
0.00 |
79.93 |
0.00 |
88.82 |
0.19 |
|
|
92.19 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1267526989 |
| 85.75 |
0.03 |
90.23 |
0.00 |
79.93 |
0.00 |
89.01 |
0.19 |
|
|
92.19 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3941728935 |
| 85.78 |
0.03 |
90.31 |
0.08 |
79.93 |
0.00 |
89.11 |
0.10 |
|
|
92.20 |
0.01 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.3299329418 |
| 85.81 |
0.03 |
90.31 |
0.00 |
80.00 |
0.07 |
89.18 |
0.07 |
|
|
92.22 |
0.03 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.4195739101 |
| 85.83 |
0.03 |
90.31 |
0.00 |
80.16 |
0.16 |
89.18 |
0.00 |
|
|
92.22 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.306436993 |
| 85.86 |
0.03 |
90.38 |
0.07 |
80.20 |
0.04 |
89.18 |
0.00 |
|
|
92.27 |
0.05 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.688549576 |
| 85.88 |
0.02 |
90.44 |
0.06 |
80.20 |
0.01 |
89.25 |
0.07 |
|
|
92.27 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.1350094407 |
| 85.90 |
0.02 |
90.45 |
0.01 |
80.21 |
0.01 |
89.36 |
0.11 |
|
|
92.27 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2023291137 |
| 85.92 |
0.02 |
90.45 |
0.00 |
80.21 |
0.00 |
89.47 |
0.11 |
|
|
92.27 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.48544387 |
| 85.94 |
0.02 |
90.45 |
0.00 |
80.21 |
0.00 |
89.57 |
0.10 |
|
|
92.27 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.2960086146 |
| 85.96 |
0.02 |
90.45 |
0.01 |
80.27 |
0.07 |
89.59 |
0.02 |
|
|
92.28 |
0.01 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3969225493 |
| 85.97 |
0.02 |
90.46 |
0.01 |
80.29 |
0.01 |
89.64 |
0.05 |
|
|
92.30 |
0.02 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.147763310 |
| 85.98 |
0.01 |
90.46 |
0.00 |
80.29 |
0.00 |
89.72 |
0.08 |
|
|
92.30 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/2.chip_sw_flash_init.659501513 |
| 86.00 |
0.01 |
90.49 |
0.03 |
80.31 |
0.02 |
89.72 |
0.01 |
|
|
92.32 |
0.03 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.2880844126 |
| 86.01 |
0.01 |
90.49 |
0.00 |
80.31 |
0.00 |
89.80 |
0.07 |
|
|
92.32 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.rom_raw_unlock.3465654392 |
| 86.02 |
0.01 |
90.52 |
0.03 |
80.32 |
0.01 |
89.80 |
0.00 |
|
|
92.34 |
0.02 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1339992791 |
| 86.03 |
0.01 |
90.55 |
0.03 |
80.33 |
0.01 |
89.80 |
0.00 |
|
|
92.36 |
0.02 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.602183347 |
| 86.04 |
0.01 |
90.55 |
0.00 |
80.34 |
0.01 |
89.85 |
0.05 |
|
|
92.36 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2256088393 |
| 86.05 |
0.01 |
90.55 |
0.00 |
80.34 |
0.00 |
89.90 |
0.05 |
|
|
92.36 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2877150544 |
| 86.05 |
0.01 |
90.55 |
0.00 |
80.39 |
0.05 |
89.90 |
0.00 |
|
|
92.36 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.1765145208 |
| 86.06 |
0.01 |
90.57 |
0.02 |
80.40 |
0.01 |
89.90 |
0.00 |
|
|
92.37 |
0.02 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.471397822 |
| 86.07 |
0.01 |
90.59 |
0.02 |
80.41 |
0.01 |
89.90 |
0.00 |
|
|
92.39 |
0.02 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1779818259 |
| 86.08 |
0.01 |
90.61 |
0.01 |
80.41 |
0.00 |
89.93 |
0.03 |
|
|
92.39 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.253275696 |
| 86.09 |
0.01 |
90.61 |
0.00 |
80.46 |
0.05 |
89.93 |
0.00 |
|
|
92.39 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.2346303344 |
| 86.09 |
0.01 |
90.61 |
0.00 |
80.50 |
0.05 |
89.93 |
0.00 |
|
|
92.39 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.416597378 |
| 86.10 |
0.01 |
90.64 |
0.03 |
80.51 |
0.01 |
89.93 |
0.00 |
|
|
92.39 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.959714135 |
| 86.11 |
0.01 |
90.64 |
0.00 |
80.51 |
0.00 |
89.97 |
0.03 |
|
|
92.39 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2712318422 |
| 86.11 |
0.01 |
90.64 |
0.00 |
80.54 |
0.03 |
89.97 |
0.00 |
|
|
92.39 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.4124152402 |
| 86.12 |
0.01 |
90.64 |
0.00 |
80.56 |
0.03 |
89.97 |
0.00 |
|
|
92.39 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.939823191 |
| 86.12 |
0.01 |
90.64 |
0.01 |
80.58 |
0.02 |
89.97 |
0.01 |
|
|
92.39 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3619221101 |
| 86.12 |
0.01 |
90.64 |
0.00 |
80.58 |
0.00 |
89.99 |
0.02 |
|
|
92.39 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.2547881074 |
| 86.13 |
0.01 |
90.64 |
0.00 |
80.60 |
0.02 |
89.99 |
0.00 |
|
|
92.39 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.1207827344 |
| 86.13 |
0.01 |
90.65 |
0.01 |
80.62 |
0.01 |
90.00 |
0.01 |
|
|
92.39 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.4179201948 |
| 86.13 |
0.01 |
90.65 |
0.01 |
80.62 |
0.00 |
90.01 |
0.01 |
|
|
92.39 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/2.chip_jtag_csr_rw.875298068 |
| 86.14 |
0.01 |
90.65 |
0.00 |
80.62 |
0.00 |
90.02 |
0.01 |
|
|
92.40 |
0.01 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2249254032 |
| 86.14 |
0.01 |
90.67 |
0.02 |
80.62 |
0.00 |
90.02 |
0.00 |
|
|
92.40 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.1857061395 |
| 86.14 |
0.01 |
90.67 |
0.01 |
80.63 |
0.01 |
90.02 |
0.01 |
|
|
92.40 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2137593723 |
| 86.14 |
0.01 |
90.67 |
0.00 |
80.64 |
0.01 |
90.02 |
0.00 |
|
|
92.40 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3630738012 |
| 86.15 |
0.01 |
90.67 |
0.00 |
80.64 |
0.00 |
90.03 |
0.01 |
|
|
92.40 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_jtag_mem_access.3623462028 |
| 86.15 |
0.01 |
90.67 |
0.00 |
80.64 |
0.00 |
90.05 |
0.01 |
|
|
92.40 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.4235660441 |
| 86.15 |
0.01 |
90.68 |
0.01 |
80.64 |
0.00 |
90.05 |
0.01 |
|
|
92.40 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.454961615 |
| 86.15 |
0.01 |
90.68 |
0.00 |
80.64 |
0.00 |
90.06 |
0.01 |
|
|
92.40 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3784908397 |
| 86.16 |
0.01 |
90.68 |
0.00 |
80.64 |
0.00 |
90.08 |
0.01 |
|
|
92.40 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3939651664 |
| 86.16 |
0.01 |
90.68 |
0.00 |
80.65 |
0.01 |
90.08 |
0.00 |
|
|
92.40 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sival_flash_info_access.96483084 |
| 86.16 |
0.01 |
90.68 |
0.00 |
80.66 |
0.01 |
90.08 |
0.00 |
|
|
92.40 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1473714447 |
| 86.16 |
0.01 |
90.68 |
0.00 |
80.67 |
0.01 |
90.08 |
0.00 |
|
|
92.40 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3570317508 |
| 86.16 |
0.01 |
90.68 |
0.00 |
80.68 |
0.01 |
90.08 |
0.01 |
|
|
92.40 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1232516745 |
| 86.16 |
0.01 |
90.69 |
0.01 |
80.68 |
0.01 |
90.09 |
0.01 |
|
|
92.40 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.4272842663 |
| 86.17 |
0.01 |
90.69 |
0.00 |
80.68 |
0.00 |
90.10 |
0.01 |
|
|
92.40 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.4280385970 |
| 86.17 |
0.01 |
90.69 |
0.00 |
80.68 |
0.00 |
90.11 |
0.01 |
|
|
92.40 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.282128188 |
| 86.17 |
0.01 |
90.69 |
0.00 |
80.68 |
0.00 |
90.11 |
0.01 |
|
|
92.40 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4285628928 |
| 86.17 |
0.01 |
90.69 |
0.00 |
80.68 |
0.00 |
90.11 |
0.00 |
|
|
92.41 |
0.01 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_tap_straps_dev.1208256165 |
| 86.17 |
0.01 |
90.69 |
0.00 |
80.69 |
0.01 |
90.11 |
0.00 |
|
|
92.41 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.4173433248 |
| 86.17 |
0.01 |
90.69 |
0.00 |
80.70 |
0.01 |
90.11 |
0.00 |
|
|
92.41 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.3943766712 |
| 86.17 |
0.01 |
90.69 |
0.00 |
80.70 |
0.01 |
90.11 |
0.00 |
|
|
92.41 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.1963670236 |
| 86.18 |
0.01 |
90.69 |
0.00 |
80.71 |
0.01 |
90.11 |
0.00 |
|
|
92.41 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/2.chip_sw_gpio.291818235 |
| 86.18 |
0.01 |
90.69 |
0.00 |
80.71 |
0.00 |
90.12 |
0.01 |
|
|
92.41 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.49148355 |
| 86.18 |
0.01 |
90.69 |
0.00 |
80.71 |
0.01 |
90.12 |
0.01 |
|
|
92.41 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3730274779 |
| 86.18 |
0.01 |
90.69 |
0.01 |
80.71 |
0.00 |
90.13 |
0.01 |
|
|
92.41 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.968584553 |
| 86.18 |
0.01 |
90.69 |
0.01 |
80.71 |
0.00 |
90.13 |
0.01 |
|
|
92.41 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2670725271 |
| 86.18 |
0.01 |
90.69 |
0.00 |
80.71 |
0.00 |
90.13 |
0.01 |
|
|
92.41 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.3972397734 |
| 86.18 |
0.01 |
90.69 |
0.00 |
80.71 |
0.00 |
90.14 |
0.01 |
|
|
92.41 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_init.1587417836 |
| 86.18 |
0.01 |
90.69 |
0.00 |
80.71 |
0.00 |
90.14 |
0.01 |
|
|
92.41 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_hmac_enc.2792683797 |
| 86.18 |
0.01 |
90.69 |
0.00 |
80.71 |
0.00 |
90.15 |
0.01 |
|
|
92.41 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3412238405 |
| 86.18 |
0.01 |
90.69 |
0.00 |
80.71 |
0.00 |
90.15 |
0.01 |
|
|
92.41 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2902134966 |
| 86.18 |
0.01 |
90.69 |
0.00 |
80.71 |
0.00 |
90.16 |
0.01 |
|
|
92.41 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3964262178 |
| 86.19 |
0.01 |
90.69 |
0.00 |
80.72 |
0.01 |
90.16 |
0.00 |
|
|
92.41 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.1791675027 |
| 86.19 |
0.01 |
90.69 |
0.00 |
80.72 |
0.01 |
90.16 |
0.00 |
|
|
92.41 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3810107461 |
| 86.19 |
0.01 |
90.69 |
0.00 |
80.72 |
0.00 |
90.16 |
0.01 |
|
|
92.41 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1808818457 |
| 86.19 |
0.01 |
90.69 |
0.00 |
80.72 |
0.00 |
90.16 |
0.01 |
|
|
92.41 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_tap_straps_rma.2248052664 |
| 86.19 |
0.01 |
90.69 |
0.00 |
80.72 |
0.00 |
90.17 |
0.01 |
|
|
92.41 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1447237745 |
| 86.19 |
0.01 |
90.69 |
0.00 |
80.72 |
0.00 |
90.17 |
0.01 |
|
|
92.41 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2084805687 |
| 86.19 |
0.01 |
90.69 |
0.00 |
80.72 |
0.00 |
90.17 |
0.01 |
|
|
92.41 |
0.00 |
78.52 |
0.00 |
84.62 |
0.00 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2974607582 |
| Name |
| /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3804522675 |
| /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.670480585 |
| /workspace/coverage/default/0.chip_sw_aes_enc.4258800576 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3115448959 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3521527468 |
| /workspace/coverage/default/0.chip_sw_aes_entropy.3872629368 |
| /workspace/coverage/default/0.chip_sw_aes_idle.2840295445 |
| /workspace/coverage/default/0.chip_sw_aes_masking_off.1018121454 |
| /workspace/coverage/default/0.chip_sw_aes_smoketest.702049648 |
| /workspace/coverage/default/0.chip_sw_alert_handler_entropy.2627131777 |
| /workspace/coverage/default/0.chip_sw_alert_handler_escalation.4233351933 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.976000667 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2119886834 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1647463992 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.703713080 |
| /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2842501691 |
| /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3228939388 |
| /workspace/coverage/default/0.chip_sw_alert_test.1498820879 |
| /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2280149485 |
| /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2321272082 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1839116387 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1759085990 |
| /workspace/coverage/default/0.chip_sw_ast_clk_outputs.4163890982 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2505070277 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2796884064 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3674903224 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1603970873 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4139176305 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.788394563 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter.2792908948 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3769306228 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1326663981 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.450588045 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2632595195 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3309672682 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1762588979 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2002294978 |
| /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3832643128 |
| /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2161929146 |
| /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.4289031031 |
| /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.4185442253 |
| /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3890916174 |
| /workspace/coverage/default/0.chip_sw_csrng_kat_test.2296105735 |
| /workspace/coverage/default/0.chip_sw_csrng_smoketest.3180087603 |
| /workspace/coverage/default/0.chip_sw_edn_auto_mode.2503733508 |
| /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2648102027 |
| /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.666863129 |
| /workspace/coverage/default/0.chip_sw_edn_kat.373652339 |
| /workspace/coverage/default/0.chip_sw_edn_sw_mode.721517962 |
| /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2084860284 |
| /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2161686245 |
| /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2371638375 |
| /workspace/coverage/default/0.chip_sw_example_concurrency.569485954 |
| /workspace/coverage/default/0.chip_sw_example_flash.2471151868 |
| /workspace/coverage/default/0.chip_sw_example_manufacturer.4072252005 |
| /workspace/coverage/default/0.chip_sw_example_rom.1997398074 |
| /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2444009224 |
| /workspace/coverage/default/0.chip_sw_flash_crash_alert.1028335060 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_access.548443927 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3239459441 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3239654965 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2113015088 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2843245620 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1228098047 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2746233151 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.4001157776 |
| /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1161553144 |
| /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.4238473993 |
| /workspace/coverage/default/0.chip_sw_gpio_smoketest.3505345438 |
| /workspace/coverage/default/0.chip_sw_hmac_enc_idle.3467556980 |
| /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3402518688 |
| /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2951979213 |
| /workspace/coverage/default/0.chip_sw_hmac_smoketest.1445885101 |
| /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.695370210 |
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| /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2701661585 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3113247246 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2630452543 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3420682299 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1935854767 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1272338528 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1803269526 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1306852549 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3571867086 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1127747046 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1800761439 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3690774181 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2166509175 |
| /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.646221196 |
| /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2943386948 |
| /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2092808105 |
| /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2122826826 |
| /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1987669882 |
| /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.728657972 |
| /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2173272456 |
| /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1084553552 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1685914863 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.4286998548 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.544816209 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.4261361943 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.213368678 |
| /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3066139451 |
| /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.4037021625 |
| /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1285102193 |
| /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.97977289 |
| /workspace/coverage/default/2.chip_sw_rv_timer_irq.2305237245 |
| /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.320051107 |
| /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2591534827 |
| /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.351710710 |
| /workspace/coverage/default/2.chip_sw_sleep_pin_retention.4070178426 |
| /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3709272309 |
| /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1426753267 |
| /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1562658926 |
| /workspace/coverage/default/2.chip_sw_spi_device_pass_through.1709828143 |
| /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.865133569 |
| /workspace/coverage/default/2.chip_sw_spi_device_tpm.2429036639 |
| /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1421793406 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2136060496 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.277799883 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1759334573 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1821546780 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3001925648 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2059029384 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.4266125583 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1652803780 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.4158220065 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2290467355 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1239360246 |
| /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3626884520 |
| /workspace/coverage/default/2.chip_sw_uart_smoketest.2279518307 |
| /workspace/coverage/default/2.chip_sw_uart_smoketest_signed.3662478691 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.480723824 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4290951249 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1517294986 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.380266306 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3621039815 |
| /workspace/coverage/default/2.chip_tap_straps_dev.1381195498 |
| /workspace/coverage/default/2.chip_tap_straps_prod.2115144211 |
| /workspace/coverage/default/2.chip_tap_straps_rma.2682211752 |
| /workspace/coverage/default/2.chip_tap_straps_testunlock0.2122206846 |
| /workspace/coverage/default/2.rom_e2e_asm_init_dev.2925538041 |
| /workspace/coverage/default/2.rom_e2e_asm_init_prod.2598319407 |
| /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2049489081 |
| /workspace/coverage/default/2.rom_e2e_asm_init_rma.3900084658 |
| /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1045388349 |
| /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.526122485 |
| /workspace/coverage/default/2.rom_e2e_shutdown_output.1120517007 |
| /workspace/coverage/default/2.rom_e2e_smoke.1844120924 |
| /workspace/coverage/default/2.rom_e2e_static_critical.577249601 |
| /workspace/coverage/default/2.rom_keymgr_functest.783948277 |
| /workspace/coverage/default/2.rom_raw_unlock.210859491 |
| /workspace/coverage/default/2.rom_volatile_raw_unlock.568782827 |
| /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.395794775 |
| /workspace/coverage/default/24.chip_sw_all_escalation_resets.237237981 |
| /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2443427139 |
| /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2839818057 |
| /workspace/coverage/default/27.chip_sw_all_escalation_resets.316241143 |
| /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2282952121 |
| /workspace/coverage/default/28.chip_sw_all_escalation_resets.2335457563 |
| /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.725542295 |
| /workspace/coverage/default/29.chip_sw_all_escalation_resets.2180007120 |
| /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2581076923 |
| /workspace/coverage/default/3.chip_sw_data_integrity_escalation.2623804368 |
| /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3527588485 |
| /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3824346640 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx.3654938455 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1832753725 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.867744845 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2101151688 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.430074215 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3675638846 |
| /workspace/coverage/default/3.chip_tap_straps_dev.2235974831 |
| /workspace/coverage/default/3.chip_tap_straps_prod.408756718 |
| /workspace/coverage/default/3.chip_tap_straps_rma.3879883438 |
| /workspace/coverage/default/3.chip_tap_straps_testunlock0.963861877 |
| /workspace/coverage/default/31.chip_sw_all_escalation_resets.3519162576 |
| /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.140260073 |
| /workspace/coverage/default/32.chip_sw_all_escalation_resets.4208603608 |
| /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2571794584 |
| /workspace/coverage/default/34.chip_sw_all_escalation_resets.4187925143 |
| /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2345431895 |
| /workspace/coverage/default/35.chip_sw_all_escalation_resets.1655328468 |
| /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1906211646 |
| /workspace/coverage/default/37.chip_sw_all_escalation_resets.2153549593 |
| /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3789065173 |
| /workspace/coverage/default/38.chip_sw_all_escalation_resets.1664600484 |
| /workspace/coverage/default/39.chip_sw_all_escalation_resets.2199861702 |
| /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2421593631 |
| /workspace/coverage/default/4.chip_sw_all_escalation_resets.892169351 |
| /workspace/coverage/default/4.chip_sw_data_integrity_escalation.1398313205 |
| /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1502748926 |
| /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.4171640447 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx.3335540855 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3781893154 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2425997102 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3888019905 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1373293126 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1022601779 |
| /workspace/coverage/default/4.chip_tap_straps_dev.348992108 |
| /workspace/coverage/default/4.chip_tap_straps_prod.871390197 |
| /workspace/coverage/default/4.chip_tap_straps_rma.3761577726 |
| /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.178824363 |
| /workspace/coverage/default/41.chip_sw_all_escalation_resets.2012590684 |
| /workspace/coverage/default/42.chip_sw_all_escalation_resets.2111631905 |
| /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.625683282 |
| /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2706585573 |
| /workspace/coverage/default/44.chip_sw_all_escalation_resets.1074801095 |
| /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3567170159 |
| /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.354842079 |
| /workspace/coverage/default/47.chip_sw_all_escalation_resets.2468883847 |
| /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.512801638 |
| /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.527716963 |
| /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.214595664 |
| /workspace/coverage/default/5.chip_sw_all_escalation_resets.2640149818 |
| /workspace/coverage/default/5.chip_sw_data_integrity_escalation.4127145469 |
| /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1345020324 |
| /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3412464489 |
| /workspace/coverage/default/50.chip_sw_all_escalation_resets.2226483588 |
| /workspace/coverage/default/51.chip_sw_all_escalation_resets.60864919 |
| /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2667698395 |
| /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.982125699 |
| /workspace/coverage/default/53.chip_sw_all_escalation_resets.1070895487 |
| /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.562910075 |
| /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2446721495 |
| /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.4183888427 |
| /workspace/coverage/default/57.chip_sw_all_escalation_resets.1858973741 |
| /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.448058715 |
| /workspace/coverage/default/58.chip_sw_all_escalation_resets.1979118309 |
| /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1371448999 |
| /workspace/coverage/default/59.chip_sw_all_escalation_resets.90724281 |
| /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2026722460 |
| /workspace/coverage/default/6.chip_sw_all_escalation_resets.578323055 |
| /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.648938969 |
| /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3816822249 |
| /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.958908983 |
| /workspace/coverage/default/61.chip_sw_all_escalation_resets.2834067674 |
| /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2655974635 |
| /workspace/coverage/default/62.chip_sw_all_escalation_resets.3741212341 |
| /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2557212915 |
| /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.4150881637 |
| /workspace/coverage/default/65.chip_sw_all_escalation_resets.3031196860 |
| /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1160957466 |
| /workspace/coverage/default/66.chip_sw_all_escalation_resets.2570677688 |
| /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3350771255 |
| /workspace/coverage/default/67.chip_sw_all_escalation_resets.2723579198 |
| /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.676223986 |
| /workspace/coverage/default/68.chip_sw_all_escalation_resets.2704022980 |
| /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3926275197 |
| /workspace/coverage/default/7.chip_sw_all_escalation_resets.3169840235 |
| /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.343082533 |
| /workspace/coverage/default/70.chip_sw_all_escalation_resets.1205550520 |
| /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1978500155 |
| /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2346158314 |
| /workspace/coverage/default/72.chip_sw_all_escalation_resets.1985832605 |
| /workspace/coverage/default/73.chip_sw_all_escalation_resets.792182236 |
| /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3355318754 |
| /workspace/coverage/default/74.chip_sw_all_escalation_resets.487131731 |
| /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.761083051 |
| /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1181622216 |
| /workspace/coverage/default/77.chip_sw_all_escalation_resets.62402985 |
| /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3159793205 |
| /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2410323401 |
| /workspace/coverage/default/79.chip_sw_all_escalation_resets.2010538767 |
| /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4120404692 |
| /workspace/coverage/default/8.chip_sw_all_escalation_resets.1764431392 |
| /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3011076866 |
| /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2452500256 |
| /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3036970862 |
| /workspace/coverage/default/80.chip_sw_all_escalation_resets.606893950 |
| /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2267756180 |
| /workspace/coverage/default/81.chip_sw_all_escalation_resets.3390169183 |
| /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2793097259 |
| /workspace/coverage/default/82.chip_sw_all_escalation_resets.2222396194 |
| /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3451518316 |
| /workspace/coverage/default/84.chip_sw_all_escalation_resets.948956224 |
| /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1438874182 |
| /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.4153579566 |
| /workspace/coverage/default/87.chip_sw_all_escalation_resets.2993601018 |
| /workspace/coverage/default/88.chip_sw_all_escalation_resets.513168398 |
| /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2166213004 |
| /workspace/coverage/default/89.chip_sw_all_escalation_resets.799372075 |
| /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.371290509 |
| /workspace/coverage/default/9.chip_sw_all_escalation_resets.727950239 |
| /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.965954691 |
| /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.441948352 |
| /workspace/coverage/default/90.chip_sw_all_escalation_resets.2821037557 |
| /workspace/coverage/default/91.chip_sw_all_escalation_resets.2005399359 |
| /workspace/coverage/default/93.chip_sw_all_escalation_resets.4045929358 |
| /workspace/coverage/default/94.chip_sw_all_escalation_resets.1202838099 |
| /workspace/coverage/default/95.chip_sw_all_escalation_resets.3844874977 |
| /workspace/coverage/default/96.chip_sw_all_escalation_resets.3754303440 |
| /workspace/coverage/default/97.chip_sw_all_escalation_resets.853675237 |
| /workspace/coverage/default/98.chip_sw_all_escalation_resets.267435166 |
| /workspace/coverage/default/99.chip_sw_all_escalation_resets.3014014054 |
| /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2817995864 |
| /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3801791030 |
| /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3761320210 |
| /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2998278555 |
| /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2669961504 |
| /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1062660689 |
| /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1362207223 |
| /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.4261807045 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/1.chip_sw_edn_kat.1444441654 |
|
|
Feb 04 03:51:22 PM PST 24 |
Feb 04 04:02:52 PM PST 24 |
3479124644 ps |
| T2 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1031411378 |
|
|
Feb 04 03:45:14 PM PST 24 |
Feb 04 03:54:21 PM PST 24 |
4835765824 ps |
| T3 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.646221196 |
|
|
Feb 04 04:01:14 PM PST 24 |
Feb 04 04:10:58 PM PST 24 |
4855631128 ps |
| T21 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2661763248 |
|
|
Feb 04 04:21:37 PM PST 24 |
Feb 04 04:34:00 PM PST 24 |
4593362180 ps |
| T50 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1445100633 |
|
|
Feb 04 03:50:58 PM PST 24 |
Feb 04 04:55:36 PM PST 24 |
17124878040 ps |
| T59 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.448058715 |
|
|
Feb 04 04:18:53 PM PST 24 |
Feb 04 04:28:22 PM PST 24 |
3820560090 ps |
| T62 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2379218467 |
|
|
Feb 04 04:21:25 PM PST 24 |
Feb 04 04:31:33 PM PST 24 |
5523580784 ps |
| T74 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1044432477 |
|
|
Feb 04 03:42:55 PM PST 24 |
Feb 04 03:56:08 PM PST 24 |
5699778558 ps |
| T4 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.176471645 |
|
|
Feb 04 04:12:29 PM PST 24 |
Feb 04 04:21:33 PM PST 24 |
6773606020 ps |
| T75 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1109224877 |
|
|
Feb 04 03:54:30 PM PST 24 |
Feb 04 04:24:07 PM PST 24 |
13070512316 ps |
| T113 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.882421493 |
|
|
Feb 04 03:56:16 PM PST 24 |
Feb 04 05:02:57 PM PST 24 |
14002182560 ps |
| T295 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.1350094407 |
|
|
Feb 04 03:59:13 PM PST 24 |
Feb 04 04:19:29 PM PST 24 |
5175906594 ps |
| T64 |
/workspace/coverage/default/3.chip_tap_straps_testunlock0.963861877 |
|
|
Feb 04 04:10:50 PM PST 24 |
Feb 04 04:14:18 PM PST 24 |
4170131525 ps |
| T166 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.1862387241 |
|
|
Feb 04 04:10:18 PM PST 24 |
Feb 04 04:37:07 PM PST 24 |
8175701500 ps |
| T60 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1562658926 |
|
|
Feb 04 04:07:51 PM PST 24 |
Feb 04 04:23:27 PM PST 24 |
6230610886 ps |
| T28 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2084805687 |
|
|
Feb 04 03:49:05 PM PST 24 |
Feb 04 04:45:08 PM PST 24 |
12569572140 ps |
| T233 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.1791675027 |
|
|
Feb 04 03:40:55 PM PST 24 |
Feb 04 03:47:46 PM PST 24 |
3208260896 ps |
| T67 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1603970873 |
|
|
Feb 04 03:43:17 PM PST 24 |
Feb 04 03:54:14 PM PST 24 |
4498099600 ps |
| T5 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.630416500 |
|
|
Feb 04 03:45:00 PM PST 24 |
Feb 04 03:53:02 PM PST 24 |
5354674544 ps |
| T212 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2101151688 |
|
|
Feb 04 04:11:07 PM PST 24 |
Feb 04 04:25:58 PM PST 24 |
5777962638 ps |
| T63 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.3470616037 |
|
|
Feb 04 04:13:11 PM PST 24 |
Feb 04 04:24:54 PM PST 24 |
5835787168 ps |
| T29 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.48544387 |
|
|
Feb 04 03:41:42 PM PST 24 |
Feb 04 03:48:34 PM PST 24 |
4901781046 ps |
| T348 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.657149594 |
|
|
Feb 04 03:58:28 PM PST 24 |
Feb 04 04:14:15 PM PST 24 |
4374961532 ps |
| T153 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1699764084 |
|
|
Feb 04 04:20:42 PM PST 24 |
Feb 04 04:31:08 PM PST 24 |
5146117580 ps |
| T373 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1228098047 |
|
|
Feb 04 03:42:24 PM PST 24 |
Feb 04 04:02:16 PM PST 24 |
6008540008 ps |
| T216 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.950287737 |
|
|
Feb 04 03:58:56 PM PST 24 |
Feb 04 04:04:31 PM PST 24 |
2897449968 ps |
| T210 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2246204232 |
|
|
Feb 04 04:19:00 PM PST 24 |
Feb 04 04:27:13 PM PST 24 |
3987741800 ps |
| T236 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.4208603608 |
|
|
Feb 04 04:15:49 PM PST 24 |
Feb 04 04:26:20 PM PST 24 |
4686582386 ps |
| T175 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1293165207 |
|
|
Feb 04 03:42:56 PM PST 24 |
Feb 04 04:48:48 PM PST 24 |
16872395432 ps |
| T294 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2036030453 |
|
|
Feb 04 04:19:07 PM PST 24 |
Feb 04 04:29:40 PM PST 24 |
4686625008 ps |
| T154 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2701611060 |
|
|
Feb 04 03:58:44 PM PST 24 |
Feb 04 04:16:44 PM PST 24 |
6584068950 ps |
| T68 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.1326333066 |
|
|
Feb 04 03:54:16 PM PST 24 |
Feb 04 03:55:58 PM PST 24 |
2451537627 ps |
| T106 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3933439771 |
|
|
Feb 04 03:54:27 PM PST 24 |
Feb 04 04:03:54 PM PST 24 |
4855720200 ps |
| T211 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.436343888 |
|
|
Feb 04 03:59:35 PM PST 24 |
Feb 04 04:12:10 PM PST 24 |
5004740800 ps |
| T196 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.976000667 |
|
|
Feb 04 03:40:31 PM PST 24 |
Feb 04 04:05:53 PM PST 24 |
6702062952 ps |
| T142 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1453992833 |
|
|
Feb 04 03:59:51 PM PST 24 |
Feb 04 04:04:34 PM PST 24 |
3449640530 ps |
| T242 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3939651664 |
|
|
Feb 04 04:06:26 PM PST 24 |
Feb 04 04:14:42 PM PST 24 |
4051555899 ps |
| T157 |
/workspace/coverage/default/1.chip_sw_aes_entropy.86769203 |
|
|
Feb 04 03:50:34 PM PST 24 |
Feb 04 03:54:59 PM PST 24 |
2569812740 ps |
| T176 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.865608033 |
|
|
Feb 04 03:44:38 PM PST 24 |
Feb 04 03:50:43 PM PST 24 |
3005293820 ps |
| T99 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1239360246 |
|
|
Feb 04 04:02:15 PM PST 24 |
Feb 04 04:10:53 PM PST 24 |
4974606850 ps |
| T6 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.1389325695 |
|
|
Feb 04 03:57:16 PM PST 24 |
Feb 04 04:36:17 PM PST 24 |
15873080369 ps |
| T101 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4285628928 |
|
|
Feb 04 04:07:33 PM PST 24 |
Feb 04 04:15:40 PM PST 24 |
4354089467 ps |
| T17 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.826680400 |
|
|
Feb 04 03:39:23 PM PST 24 |
Feb 04 03:46:34 PM PST 24 |
3793240176 ps |
| T10 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1655963884 |
|
|
Feb 04 03:43:27 PM PST 24 |
Feb 04 03:53:33 PM PST 24 |
4605705622 ps |
| T102 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1267526989 |
|
|
Feb 04 04:03:54 PM PST 24 |
Feb 04 04:22:38 PM PST 24 |
4993073951 ps |
| T100 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2256088393 |
|
|
Feb 04 03:49:53 PM PST 24 |
Feb 04 03:56:31 PM PST 24 |
19334378728 ps |
| T170 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3561538413 |
|
|
Feb 04 03:41:33 PM PST 24 |
Feb 04 03:45:28 PM PST 24 |
2608365820 ps |
| T150 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.1445885101 |
|
|
Feb 04 03:41:25 PM PST 24 |
Feb 04 03:47:58 PM PST 24 |
3405651096 ps |
| T177 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.22984586 |
|
|
Feb 04 03:40:03 PM PST 24 |
Feb 04 03:51:04 PM PST 24 |
4682093156 ps |
| T128 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3412464489 |
|
|
Feb 04 04:11:56 PM PST 24 |
Feb 04 04:54:30 PM PST 24 |
13735111800 ps |
| T129 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.946347266 |
|
|
Feb 04 03:43:37 PM PST 24 |
Feb 04 04:00:19 PM PST 24 |
5732708066 ps |
| T97 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.282128188 |
|
|
Feb 04 03:45:18 PM PST 24 |
Feb 04 03:54:14 PM PST 24 |
7192670510 ps |
| T156 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3661281887 |
|
|
Feb 04 03:54:14 PM PST 24 |
Feb 04 04:02:37 PM PST 24 |
4816694460 ps |
| T138 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2010538767 |
|
|
Feb 04 04:21:16 PM PST 24 |
Feb 04 04:34:59 PM PST 24 |
5355993696 ps |
| T353 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.1838391994 |
|
|
Feb 04 04:15:13 PM PST 24 |
Feb 04 04:26:08 PM PST 24 |
5964808200 ps |
| T368 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2187177511 |
|
|
Feb 04 03:53:27 PM PST 24 |
Feb 04 04:07:48 PM PST 24 |
6650460800 ps |
| T532 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2336827570 |
|
|
Feb 04 03:44:54 PM PST 24 |
Feb 04 03:52:12 PM PST 24 |
4404785416 ps |
| T158 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.2385554956 |
|
|
Feb 04 04:02:42 PM PST 24 |
Feb 04 04:20:41 PM PST 24 |
6089048980 ps |
| T237 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.2880844126 |
|
|
Feb 04 04:13:37 PM PST 24 |
Feb 04 04:24:21 PM PST 24 |
5785433752 ps |
| T130 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1809454296 |
|
|
Feb 04 04:05:57 PM PST 24 |
Feb 04 04:15:38 PM PST 24 |
4794129496 ps |
| T389 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3832643128 |
|
|
Feb 04 03:42:59 PM PST 24 |
Feb 04 03:50:54 PM PST 24 |
3624373418 ps |
| T148 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1790234767 |
|
|
Feb 04 03:48:41 PM PST 24 |
Feb 04 03:56:28 PM PST 24 |
4059619924 ps |
| T234 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.895162614 |
|
|
Feb 04 03:46:02 PM PST 24 |
Feb 04 03:52:06 PM PST 24 |
3637307364 ps |
| T36 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.2627131777 |
|
|
Feb 04 03:41:43 PM PST 24 |
Feb 04 03:47:09 PM PST 24 |
3628585952 ps |
| T374 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2071651498 |
|
|
Feb 04 03:57:05 PM PST 24 |
Feb 04 04:15:58 PM PST 24 |
5502270160 ps |
| T61 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3295663773 |
|
|
Feb 04 03:47:13 PM PST 24 |
Feb 04 03:50:07 PM PST 24 |
3447344528 ps |
| T103 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2927951203 |
|
|
Feb 04 04:07:47 PM PST 24 |
Feb 04 04:13:40 PM PST 24 |
2413849627 ps |
| T18 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2059029384 |
|
|
Feb 04 04:03:04 PM PST 24 |
Feb 04 04:57:28 PM PST 24 |
21117317088 ps |
| T25 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.4232305612 |
|
|
Feb 04 03:47:05 PM PST 24 |
Feb 04 04:14:18 PM PST 24 |
7030918680 ps |
| T11 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2011539799 |
|
|
Feb 04 03:41:10 PM PST 24 |
Feb 04 03:46:17 PM PST 24 |
2801144532 ps |
| T332 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.982442226 |
|
|
Feb 04 03:44:07 PM PST 24 |
Feb 04 03:56:18 PM PST 24 |
5972094672 ps |
| T325 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2410312843 |
|
|
Feb 04 04:00:32 PM PST 24 |
Feb 04 04:24:19 PM PST 24 |
10142842056 ps |
| T26 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3919102723 |
|
|
Feb 04 03:47:28 PM PST 24 |
Feb 04 04:19:31 PM PST 24 |
8227815446 ps |
| T22 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1421793406 |
|
|
Feb 04 04:00:42 PM PST 24 |
Feb 04 04:06:39 PM PST 24 |
3206952744 ps |
| T367 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2443427139 |
|
|
Feb 04 04:15:08 PM PST 24 |
Feb 04 04:21:45 PM PST 24 |
4167777296 ps |
| T53 |
/workspace/coverage/default/2.chip_sw_alert_test.1510830379 |
|
|
Feb 04 04:04:39 PM PST 24 |
Feb 04 04:08:47 PM PST 24 |
3318562890 ps |
| T147 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2002294978 |
|
|
Feb 04 03:40:59 PM PST 24 |
Feb 04 03:58:07 PM PST 24 |
8435588770 ps |
| T357 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.2012590684 |
|
|
Feb 04 04:16:33 PM PST 24 |
Feb 04 04:25:53 PM PST 24 |
5344211056 ps |
| T334 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1978500155 |
|
|
Feb 04 04:20:28 PM PST 24 |
Feb 04 04:27:44 PM PST 24 |
4127759082 ps |
| T27 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1675115384 |
|
|
Feb 04 03:47:13 PM PST 24 |
Feb 04 04:20:33 PM PST 24 |
8683603085 ps |
| T207 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.4135463821 |
|
|
Feb 04 04:12:12 PM PST 24 |
Feb 04 04:27:45 PM PST 24 |
13540568373 ps |
| T372 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2487173629 |
|
|
Feb 04 03:38:54 PM PST 24 |
Feb 04 03:48:17 PM PST 24 |
5037864800 ps |
| T191 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2303155152 |
|
|
Feb 04 03:55:26 PM PST 24 |
Feb 04 03:59:50 PM PST 24 |
3145205321 ps |
| T282 |
/workspace/coverage/default/1.chip_sw_uart_smoketest_signed.667633567 |
|
|
Feb 04 04:00:17 PM PST 24 |
Feb 04 04:34:17 PM PST 24 |
8834095226 ps |
| T143 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2943386948 |
|
|
Feb 04 04:04:18 PM PST 24 |
Feb 04 04:13:02 PM PST 24 |
8708786476 ps |
| T13 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.780662321 |
|
|
Feb 04 03:39:17 PM PST 24 |
Feb 04 03:59:48 PM PST 24 |
5399975590 ps |
| T152 |
/workspace/coverage/default/1.rom_keymgr_functest.768190329 |
|
|
Feb 04 03:57:17 PM PST 24 |
Feb 04 04:04:35 PM PST 24 |
4363586984 ps |
| T155 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.2547881074 |
|
|
Feb 04 03:59:35 PM PST 24 |
Feb 04 04:03:47 PM PST 24 |
3083268896 ps |
| T283 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1711713086 |
|
|
Feb 04 04:00:02 PM PST 24 |
Feb 04 04:13:31 PM PST 24 |
5138641773 ps |
| T284 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.2450796471 |
|
|
Feb 04 04:13:38 PM PST 24 |
Feb 04 04:26:35 PM PST 24 |
5374848244 ps |
| T139 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1484093834 |
|
|
Feb 04 03:48:15 PM PST 24 |
Feb 04 04:16:57 PM PST 24 |
13643488095 ps |
| T285 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1106155671 |
|
|
Feb 04 04:10:42 PM PST 24 |
Feb 04 05:18:46 PM PST 24 |
17407983954 ps |
| T110 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.2334298964 |
|
|
Feb 04 04:07:52 PM PST 24 |
Feb 04 04:17:39 PM PST 24 |
9503332630 ps |
| T98 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3942130365 |
|
|
Feb 04 03:41:00 PM PST 24 |
Feb 04 03:44:28 PM PST 24 |
2455021074 ps |
| T162 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3716048212 |
|
|
Feb 04 03:55:12 PM PST 24 |
Feb 04 03:58:54 PM PST 24 |
2893980624 ps |
| T380 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3270171907 |
|
|
Feb 04 04:14:26 PM PST 24 |
Feb 04 04:22:11 PM PST 24 |
3909186320 ps |
| T349 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3406893791 |
|
|
Feb 04 03:45:04 PM PST 24 |
Feb 04 04:04:13 PM PST 24 |
5102073784 ps |
| T381 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.1018121454 |
|
|
Feb 04 03:39:07 PM PST 24 |
Feb 04 03:44:03 PM PST 24 |
2664169042 ps |
| T328 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.2012726788 |
|
|
Feb 04 04:20:01 PM PST 24 |
Feb 04 04:30:38 PM PST 24 |
3887824080 ps |
| T111 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2061470723 |
|
|
Feb 04 03:52:03 PM PST 24 |
Feb 04 04:59:49 PM PST 24 |
16054342870 ps |
| T331 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.2993601018 |
|
|
Feb 04 04:24:45 PM PST 24 |
Feb 04 04:34:13 PM PST 24 |
4603443122 ps |
| T16 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.986066573 |
|
|
Feb 04 03:54:58 PM PST 24 |
Feb 04 04:24:58 PM PST 24 |
21338096922 ps |
| T89 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.625024414 |
|
|
Feb 04 04:21:11 PM PST 24 |
Feb 04 04:26:49 PM PST 24 |
4084512308 ps |
| T90 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3595656254 |
|
|
Feb 04 03:53:15 PM PST 24 |
Feb 04 03:58:29 PM PST 24 |
3136036674 ps |
| T19 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2039158534 |
|
|
Feb 04 03:48:47 PM PST 24 |
Feb 04 04:17:05 PM PST 24 |
21152300184 ps |
| T91 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.1440066553 |
|
|
Feb 04 03:56:49 PM PST 24 |
Feb 04 04:03:04 PM PST 24 |
3290583368 ps |
| T92 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2092808105 |
|
|
Feb 04 04:01:30 PM PST 24 |
Feb 04 04:31:04 PM PST 24 |
12313861048 ps |
| T93 |
/workspace/coverage/default/1.chip_sw_flash_init.3062163029 |
|
|
Feb 04 03:43:22 PM PST 24 |
Feb 04 04:11:34 PM PST 24 |
20255995117 ps |
| T94 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.36386766 |
|
|
Feb 04 03:46:54 PM PST 24 |
Feb 04 04:42:16 PM PST 24 |
12479828959 ps |
| T95 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1348865364 |
|
|
Feb 04 03:45:39 PM PST 24 |
Feb 04 04:24:31 PM PST 24 |
8689431380 ps |
| T96 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3015011830 |
|
|
Feb 04 03:55:26 PM PST 24 |
Feb 04 04:19:43 PM PST 24 |
4940890980 ps |
| T287 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1272338528 |
|
|
Feb 04 04:00:59 PM PST 24 |
Feb 04 04:04:26 PM PST 24 |
2699006272 ps |
| T125 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1473714447 |
|
|
Feb 04 03:41:36 PM PST 24 |
Feb 04 03:50:59 PM PST 24 |
5649314904 ps |
| T359 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.4171264764 |
|
|
Feb 04 03:42:13 PM PST 24 |
Feb 04 03:48:50 PM PST 24 |
3080241432 ps |
| T7 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2303287723 |
|
|
Feb 04 03:41:43 PM PST 24 |
Feb 04 03:45:21 PM PST 24 |
2931445639 ps |
| T341 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.583847609 |
|
|
Feb 04 03:40:24 PM PST 24 |
Feb 04 03:48:21 PM PST 24 |
5511950120 ps |
| T12 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.2073210581 |
|
|
Feb 04 03:40:52 PM PST 24 |
Feb 04 03:54:34 PM PST 24 |
6414590374 ps |
| T243 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.544816209 |
|
|
Feb 04 04:07:34 PM PST 24 |
Feb 04 04:08:21 PM PST 24 |
1190438340 ps |
| T168 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.964298003 |
|
|
Feb 04 03:45:12 PM PST 24 |
Feb 04 04:04:11 PM PST 24 |
8380723784 ps |
| T533 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.2376409704 |
|
|
Feb 04 03:57:37 PM PST 24 |
Feb 04 04:39:53 PM PST 24 |
10132384596 ps |
| T534 |
/workspace/coverage/default/2.chip_sw_aes_entropy.3720840283 |
|
|
Feb 04 04:03:10 PM PST 24 |
Feb 04 04:06:49 PM PST 24 |
3017137564 ps |
| T333 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.1038161745 |
|
|
Feb 04 03:38:35 PM PST 24 |
Feb 04 03:56:31 PM PST 24 |
5792818690 ps |
| T24 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.1664715975 |
|
|
Feb 04 03:45:29 PM PST 24 |
Feb 04 03:51:06 PM PST 24 |
3739600413 ps |
| T297 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2055005929 |
|
|
Feb 04 04:03:22 PM PST 24 |
Feb 04 04:14:49 PM PST 24 |
4899032448 ps |
| T403 |
/workspace/coverage/default/2.rom_e2e_static_critical.577249601 |
|
|
Feb 04 04:11:12 PM PST 24 |
Feb 04 04:45:36 PM PST 24 |
11291068622 ps |
| T289 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1429824479 |
|
|
Feb 04 04:04:10 PM PST 24 |
Feb 04 04:13:59 PM PST 24 |
5247617940 ps |
| T213 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3395800693 |
|
|
Feb 04 04:12:09 PM PST 24 |
Feb 04 04:56:02 PM PST 24 |
14359899496 ps |
| T184 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.3472153064 |
|
|
Feb 04 04:06:29 PM PST 24 |
Feb 04 04:17:16 PM PST 24 |
5064681290 ps |
| T535 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2902134966 |
|
|
Feb 04 03:38:48 PM PST 24 |
Feb 04 03:45:11 PM PST 24 |
6065852978 ps |
| T536 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.1732213499 |
|
|
Feb 04 04:09:27 PM PST 24 |
Feb 04 04:13:56 PM PST 24 |
2261158730 ps |
| T427 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.1925650325 |
|
|
Feb 04 03:46:18 PM PST 24 |
Feb 04 04:28:40 PM PST 24 |
9285555783 ps |
| T133 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1404902714 |
|
|
Feb 04 03:50:35 PM PST 24 |
Feb 04 04:15:12 PM PST 24 |
7505730824 ps |
| T436 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.3678194910 |
|
|
Feb 04 04:22:49 PM PST 24 |
Feb 04 04:35:00 PM PST 24 |
5684089680 ps |
| T40 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3412547145 |
|
|
Feb 04 03:59:37 PM PST 24 |
Feb 04 04:05:30 PM PST 24 |
5303082012 ps |
| T413 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2574117879 |
|
|
Feb 04 04:04:39 PM PST 24 |
Feb 04 04:14:35 PM PST 24 |
4724831234 ps |
| T215 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.4200663430 |
|
|
Feb 04 03:41:10 PM PST 24 |
Feb 04 03:47:33 PM PST 24 |
3160086690 ps |
| T126 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.665883677 |
|
|
Feb 04 03:55:15 PM PST 24 |
Feb 04 04:04:21 PM PST 24 |
5710852890 ps |
| T414 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2026722460 |
|
|
Feb 04 04:12:17 PM PST 24 |
Feb 04 04:19:34 PM PST 24 |
4002288940 ps |
| T415 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.140260073 |
|
|
Feb 04 04:16:16 PM PST 24 |
Feb 04 04:23:31 PM PST 24 |
3574000528 ps |
| T416 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3728957038 |
|
|
Feb 04 03:56:22 PM PST 24 |
Feb 04 04:05:29 PM PST 24 |
3564482120 ps |
| T311 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1839116387 |
|
|
Feb 04 03:39:53 PM PST 24 |
Feb 04 03:55:51 PM PST 24 |
9911699690 ps |
| T537 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.834723272 |
|
|
Feb 04 04:00:13 PM PST 24 |
Feb 04 04:07:14 PM PST 24 |
3838603316 ps |
| T214 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.867744845 |
|
|
Feb 04 04:10:50 PM PST 24 |
Feb 04 04:22:16 PM PST 24 |
5726557763 ps |
| T231 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.2271931751 |
|
|
Feb 04 03:38:32 PM PST 24 |
Feb 04 03:42:37 PM PST 24 |
3464529840 ps |
| T382 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2974607582 |
|
|
Feb 04 03:56:10 PM PST 24 |
Feb 04 03:59:02 PM PST 24 |
2486275972 ps |
| T538 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.258907784 |
|
|
Feb 04 03:40:57 PM PST 24 |
Feb 04 03:45:17 PM PST 24 |
2848848202 ps |
| T135 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.3027288926 |
|
|
Feb 04 03:40:24 PM PST 24 |
Feb 04 03:53:18 PM PST 24 |
4230888596 ps |
| T288 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.565533628 |
|
|
Feb 04 03:52:39 PM PST 24 |
Feb 04 04:01:04 PM PST 24 |
4573111864 ps |
| T244 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.4041821008 |
|
|
Feb 04 03:47:38 PM PST 24 |
Feb 04 04:19:45 PM PST 24 |
8398551496 ps |
| T14 |
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1062660689 |
|
|
Feb 04 12:42:29 PM PST 24 |
Feb 04 12:46:32 PM PST 24 |
4262986602 ps |
| T15 |
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1362207223 |
|
|
Feb 04 12:42:11 PM PST 24 |
Feb 04 12:45:15 PM PST 24 |
4928948770 ps |
| T20 |
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2042721396 |
|
|
Feb 04 12:42:21 PM PST 24 |
Feb 04 12:46:23 PM PST 24 |
3807671470 ps |
| T23 |
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.4261807045 |
|
|
Feb 04 12:42:21 PM PST 24 |
Feb 04 12:45:48 PM PST 24 |
4416994188 ps |
| T195 |
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2998278555 |
|
|
Feb 04 12:42:29 PM PST 24 |
Feb 04 12:47:24 PM PST 24 |
5242306434 ps |
| T140 |
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.4195739101 |
|
|
Feb 04 12:42:28 PM PST 24 |
Feb 04 12:45:04 PM PST 24 |
4057317929 ps |
| T539 |
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3801791030 |
|
|
Feb 04 12:42:17 PM PST 24 |
Feb 04 12:46:26 PM PST 24 |
5602818800 ps |
| T197 |
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2817995864 |
|
|
Feb 04 12:42:34 PM PST 24 |
Feb 04 12:45:54 PM PST 24 |
4677332634 ps |
| T375 |
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3761320210 |
|
|
Feb 04 12:42:17 PM PST 24 |
Feb 04 12:46:09 PM PST 24 |
5553000271 ps |
| T376 |
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2669961504 |
|
|
Feb 04 12:42:18 PM PST 24 |
Feb 04 12:46:32 PM PST 24 |
5437358760 ps |
| T112 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.2667936474 |
|
|
Feb 04 03:52:41 PM PST 24 |
Feb 04 04:13:47 PM PST 24 |
5122165176 ps |
| T540 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.3180087603 |
|
|
Feb 04 03:42:56 PM PST 24 |
Feb 04 03:47:18 PM PST 24 |
2632534416 ps |
| T73 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3327901321 |
|
|
Feb 04 04:05:14 PM PST 24 |
Feb 04 04:09:43 PM PST 24 |
3417132770 ps |
| T37 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1096093649 |
|
|
Feb 04 03:52:42 PM PST 24 |
Feb 04 04:15:09 PM PST 24 |
11781471480 ps |
| T428 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.725542295 |
|
|
Feb 04 04:14:54 PM PST 24 |
Feb 04 04:21:28 PM PST 24 |
3900727102 ps |
| T330 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1181622216 |
|
|
Feb 04 04:20:47 PM PST 24 |
Feb 04 04:26:29 PM PST 24 |
3133335700 ps |
| T541 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.4252481295 |
|
|
Feb 04 03:39:12 PM PST 24 |
Feb 04 03:42:44 PM PST 24 |
2477268900 ps |
| T181 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.4178944915 |
|
|
Feb 04 03:39:28 PM PST 24 |
Feb 04 04:23:32 PM PST 24 |
44012984837 ps |
| T542 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.697911134 |
|
|
Feb 04 03:58:14 PM PST 24 |
Feb 04 04:13:44 PM PST 24 |
5941056473 ps |
| T500 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2839818057 |
|
|
Feb 04 04:15:20 PM PST 24 |
Feb 04 04:22:28 PM PST 24 |
4486364280 ps |
| T76 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.513168398 |
|
|
Feb 04 04:24:22 PM PST 24 |
Feb 04 04:34:19 PM PST 24 |
4704216760 ps |
| T79 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.964098597 |
|
|
Feb 04 04:14:11 PM PST 24 |
Feb 04 04:26:44 PM PST 24 |
5369771760 ps |
| T80 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1076999456 |
|
|
Feb 04 03:46:38 PM PST 24 |
Feb 04 03:54:42 PM PST 24 |
8347279092 ps |
| T81 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1317224388 |
|
|
Feb 04 03:45:30 PM PST 24 |
Feb 04 04:07:48 PM PST 24 |
5611039314 ps |
| T82 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2607863392 |
|
|
Feb 04 03:57:49 PM PST 24 |
Feb 04 04:00:53 PM PST 24 |
2074798000 ps |
| T83 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.527716963 |
|
|
Feb 04 04:17:30 PM PST 24 |
Feb 04 04:23:52 PM PST 24 |
3530715070 ps |
| T84 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1725472325 |
|
|
Feb 04 03:47:53 PM PST 24 |
Feb 04 04:25:24 PM PST 24 |
8812586200 ps |
| T38 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.4263616436 |
|
|
Feb 04 03:50:51 PM PST 24 |
Feb 04 03:54:59 PM PST 24 |
3397878814 ps |
| T85 |
/workspace/coverage/default/2.chip_sw_flash_init.659501513 |
|
|
Feb 04 03:58:40 PM PST 24 |
Feb 04 04:33:57 PM PST 24 |
23564307941 ps |
| T30 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1285102193 |
|
|
Feb 04 04:06:45 PM PST 24 |
Feb 04 04:14:03 PM PST 24 |
3520494088 ps |
| T235 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.2503733508 |
|
|
Feb 04 03:42:22 PM PST 24 |
Feb 04 04:15:15 PM PST 24 |
6251209050 ps |
| T144 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3027121098 |
|
|
Feb 04 03:40:14 PM PST 24 |
Feb 04 03:50:54 PM PST 24 |
8256695907 ps |
| T511 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.710943109 |
|
|
Feb 04 04:13:16 PM PST 24 |
Feb 04 04:19:37 PM PST 24 |
4128882894 ps |
| T543 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2269643515 |
|
|
Feb 04 03:48:10 PM PST 24 |
Feb 04 04:11:24 PM PST 24 |
12029134241 ps |
| T163 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2030601291 |
|
|
Feb 04 03:39:18 PM PST 24 |
Feb 04 03:48:45 PM PST 24 |
6351741221 ps |
| T296 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.905108702 |
|
|
Feb 04 03:42:34 PM PST 24 |
Feb 04 04:09:10 PM PST 24 |
9129183264 ps |
| T315 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.869178343 |
|
|
Feb 04 03:44:37 PM PST 24 |
Feb 04 04:01:30 PM PST 24 |
5983910588 ps |
| T544 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.1028335060 |
|
|
Feb 04 03:41:53 PM PST 24 |
Feb 04 03:53:20 PM PST 24 |
5071770748 ps |
| T545 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.2122124961 |
|
|
Feb 04 03:57:59 PM PST 24 |
Feb 04 04:02:24 PM PST 24 |
2661246456 ps |
| T117 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1232516745 |
|
|
Feb 04 03:40:38 PM PST 24 |
Feb 04 04:47:20 PM PST 24 |
25504892639 ps |
| T70 |
/workspace/coverage/default/3.chip_tap_straps_dev.2235974831 |
|
|
Feb 04 04:10:54 PM PST 24 |
Feb 04 04:25:21 PM PST 24 |
7361283150 ps |
| T220 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3810107461 |
|
|
Feb 04 03:44:21 PM PST 24 |
Feb 04 04:16:00 PM PST 24 |
12498358248 ps |
| T546 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.213368678 |
|
|
Feb 04 04:01:26 PM PST 24 |
Feb 04 04:18:37 PM PST 24 |
5201277264 ps |
| T122 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.471397822 |
|
|
Feb 04 03:39:03 PM PST 24 |
Feb 04 03:46:47 PM PST 24 |
4178574038 ps |
| T547 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2701661585 |
|
|
Feb 04 04:00:02 PM PST 24 |
Feb 04 04:13:27 PM PST 24 |
6018811753 ps |
| T169 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.599888507 |
|
|
Feb 04 03:45:04 PM PST 24 |
Feb 04 04:01:23 PM PST 24 |
6903050536 ps |
| T151 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1064539120 |
|
|
Feb 04 04:07:12 PM PST 24 |
Feb 04 04:11:42 PM PST 24 |
2616448301 ps |
| T449 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2706585573 |
|
|
Feb 04 04:17:37 PM PST 24 |
Feb 04 04:25:08 PM PST 24 |
3796067796 ps |
| T312 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.547712540 |
|
|
Feb 04 03:48:58 PM PST 24 |
Feb 04 03:59:13 PM PST 24 |
3577913676 ps |
| T31 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.4043769937 |
|
|
Feb 04 03:54:40 PM PST 24 |
Feb 04 03:59:57 PM PST 24 |
4453903700 ps |
| T548 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3829545862 |
|
|
Feb 04 03:47:19 PM PST 24 |
Feb 04 04:19:49 PM PST 24 |
18614987149 ps |
| T224 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2110603628 |
|
|
Feb 04 03:49:14 PM PST 24 |
Feb 04 04:39:29 PM PST 24 |
10214900600 ps |
| T131 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.4105073075 |
|
|
Feb 04 03:40:11 PM PST 24 |
Feb 04 03:43:13 PM PST 24 |
2459152498 ps |
| T549 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1843108392 |
|
|
Feb 04 03:52:18 PM PST 24 |
Feb 04 03:57:55 PM PST 24 |
2886242072 ps |
| T550 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.548443927 |
|
|
Feb 04 03:38:31 PM PST 24 |
Feb 04 03:53:43 PM PST 24 |
5402645500 ps |
| T429 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2346158314 |
|
|
Feb 04 04:20:01 PM PST 24 |
Feb 04 04:26:36 PM PST 24 |
3777681730 ps |
| T208 |
/workspace/coverage/default/2.chip_tap_straps_dev.1381195498 |
|
|
Feb 04 04:06:05 PM PST 24 |
Feb 04 04:36:39 PM PST 24 |
17696919138 ps |
| T226 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1378000440 |
|
|
Feb 04 03:47:41 PM PST 24 |
Feb 04 04:23:08 PM PST 24 |
8680526539 ps |
| T42 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.304690151 |
|
|
Feb 04 04:06:31 PM PST 24 |
Feb 04 04:15:09 PM PST 24 |
4511803776 ps |
| T377 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.1572938080 |
|
|
Feb 04 04:16:24 PM PST 24 |
Feb 04 04:25:45 PM PST 24 |
5454570472 ps |
| T319 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.968584553 |
|
|
Feb 04 03:40:57 PM PST 24 |
Feb 04 03:54:36 PM PST 24 |
4892223846 ps |
| T291 |
/workspace/coverage/default/2.chip_sw_power_idle_load.1710503220 |
|
|
Feb 04 04:07:26 PM PST 24 |
Feb 04 04:18:33 PM PST 24 |
4678773362 ps |
| T394 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1407316544 |
|
|
Feb 04 03:59:49 PM PST 24 |
Feb 04 04:13:55 PM PST 24 |
7766355186 ps |
| T395 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2805330906 |
|
|
Feb 04 03:44:09 PM PST 24 |
Feb 04 03:56:18 PM PST 24 |
5889967768 ps |
| T378 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.1655328468 |
|
|
Feb 04 04:16:39 PM PST 24 |
Feb 04 04:26:32 PM PST 24 |
5820517340 ps |
| T314 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2137593723 |
|
|
Feb 04 03:43:00 PM PST 24 |
Feb 04 04:31:21 PM PST 24 |
14011161206 ps |
| T396 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1326663981 |
|
|
Feb 04 03:40:28 PM PST 24 |
Feb 04 03:42:48 PM PST 24 |
2517739478 ps |
| T292 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.4173433248 |
|
|
Feb 04 03:39:11 PM PST 24 |
Feb 04 03:51:34 PM PST 24 |
4578780408 ps |
| T397 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1371448999 |
|
|
Feb 04 04:18:41 PM PST 24 |
Feb 04 04:24:13 PM PST 24 |
2999109940 ps |
| T551 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.3191936816 |
|
|
Feb 04 03:51:04 PM PST 24 |
Feb 04 04:00:16 PM PST 24 |
4262590104 ps |
| T225 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.4120475334 |
|
|
Feb 04 03:48:31 PM PST 24 |
Feb 04 04:38:51 PM PST 24 |
11140082186 ps |
| T552 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.1461237501 |
|
|
Feb 04 03:43:30 PM PST 24 |
Feb 04 04:00:00 PM PST 24 |
5974124024 ps |
| T41 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.216044051 |
|
|
Feb 04 03:55:01 PM PST 24 |
Feb 04 04:25:58 PM PST 24 |
18184106488 ps |
| T132 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2023291137 |
|
|
Feb 04 03:40:42 PM PST 24 |
Feb 04 03:48:58 PM PST 24 |
4499197420 ps |
| T553 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3847381655 |
|
|
Feb 04 03:49:11 PM PST 24 |
Feb 04 04:47:13 PM PST 24 |
11660587838 ps |
| T438 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.4170317685 |
|
|
Feb 04 04:14:20 PM PST 24 |
Feb 04 04:21:49 PM PST 24 |
4086241080 ps |
| T526 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.1985832605 |
|
|
Feb 04 04:20:40 PM PST 24 |
Feb 04 04:29:58 PM PST 24 |
5485562392 ps |
| T445 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.3064222226 |
|
|
Feb 04 04:15:30 PM PST 24 |
Feb 04 04:27:17 PM PST 24 |
5511173640 ps |
| T554 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.927457336 |
|
|
Feb 04 03:48:45 PM PST 24 |
Feb 04 03:55:44 PM PST 24 |
5288838888 ps |
| T32 |
/workspace/coverage/default/0.rom_raw_unlock.3465654392 |
|
|
Feb 04 03:42:49 PM PST 24 |
Feb 04 04:19:49 PM PST 24 |
15358228330 ps |
| T355 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2640149818 |
|
|
Feb 04 04:11:19 PM PST 24 |
Feb 04 04:20:28 PM PST 24 |
4401390296 ps |
| T444 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.161520880 |
|
|
Feb 04 04:19:38 PM PST 24 |
Feb 04 04:27:23 PM PST 24 |
4286058200 ps |
| T555 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1373293126 |
|
|
Feb 04 04:10:05 PM PST 24 |
Feb 04 04:25:57 PM PST 24 |
5037770516 ps |
| T518 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.1865286192 |
|
|
Feb 04 04:17:01 PM PST 24 |
Feb 04 04:28:53 PM PST 24 |
6290809282 ps |
| T556 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.251506047 |
|
|
Feb 04 03:56:55 PM PST 24 |
Feb 04 04:00:14 PM PST 24 |
1979517584 ps |
| T557 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2894221947 |
|
|
Feb 04 03:59:35 PM PST 24 |
Feb 04 04:04:05 PM PST 24 |
2669415816 ps |
| T558 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2327779970 |
|
|
Feb 04 03:59:57 PM PST 24 |
Feb 04 04:22:48 PM PST 24 |
7199796584 ps |
| T187 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.6176535 |
|
|
Feb 04 03:45:28 PM PST 24 |
Feb 04 03:49:48 PM PST 24 |
3539591450 ps |
| T559 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.990030130 |
|
|
Feb 04 03:47:19 PM PST 24 |
Feb 04 04:21:55 PM PST 24 |
7987678288 ps |
| T308 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.49148355 |
|
|
Feb 04 04:10:18 PM PST 24 |
Feb 04 04:14:49 PM PST 24 |
6510245912 ps |
| T524 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.2575879210 |
|
|
Feb 04 04:14:38 PM PST 24 |
Feb 04 04:23:35 PM PST 24 |
4947127164 ps |
| T560 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2049489081 |
|
|
Feb 04 04:12:23 PM PST 24 |
Feb 04 04:40:29 PM PST 24 |
9439001838 ps |
| T561 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.3335540855 |
|
|
Feb 04 04:10:51 PM PST 24 |
Feb 04 04:23:55 PM PST 24 |
5097051864 ps |
| T562 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.916916312 |
|
|
Feb 04 03:49:26 PM PST 24 |
Feb 04 04:40:57 PM PST 24 |
11835599092 ps |
| T563 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.724602864 |
|
|
Feb 04 03:55:12 PM PST 24 |
Feb 04 04:06:55 PM PST 24 |
4422842600 ps |
| T33 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3066139451 |
|
|
Feb 04 04:07:04 PM PST 24 |
Feb 04 04:16:59 PM PST 24 |
5020138218 ps |
| T198 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.3063533628 |
|
|
Feb 04 04:04:46 PM PST 24 |
Feb 04 04:17:10 PM PST 24 |
3980374144 ps |
| T442 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.1470703052 |
|
|
Feb 04 04:17:15 PM PST 24 |
Feb 04 04:25:59 PM PST 24 |
5471653200 ps |
| T564 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.343082533 |
|
|
Feb 04 04:12:56 PM PST 24 |
Feb 04 04:28:22 PM PST 24 |
5137182880 ps |
| T439 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.3754303440 |
|
|
Feb 04 04:22:17 PM PST 24 |
Feb 04 04:32:01 PM PST 24 |
5421806168 ps |
| T447 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1638396094 |
|
|
Feb 04 04:19:44 PM PST 24 |
Feb 04 04:26:03 PM PST 24 |
3866605632 ps |