Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	135697	1			T77	59		T78	4		T79	3
values[2]	10180	1			T404	1		T502	1		T443	118
values[3]	3990	1			T443	3		T421	1		T499	39
values[4]	2199	1			T499	10		T398	5		T422	2
values[5]	1342	1			T499	8		T398	13		T422	1
values[6]	955	1			T499	2		T398	8		T422	2
values[7]	690	1			T398	2		T422	2		T395	20
values[8]	615	1			T398	6		T422	1		T417	32
values[9]	550	1			T398	13		T422	4		T417	25
values[10]	545	1			T398	4		T422	6		T417	31
values[11]	414	1			T398	5		T422	3		T417	7
values[12]	382	1			T398	10		T422	2		T417	5
values[13]	392	1			T398	4		T422	2		T832	1
values[14]	366	1			T398	5		T422	2		T832	1
values[15]	374	1			T398	4		T422	1		T832	1
values[16]	282	1			T398	8		T422	4		T832	1
values[17]	383	1			T398	11		T422	3		T832	1
values[18]	357	1			T398	7		T422	1		T832	1
values[19]	319	1			T398	6		T422	3		T832	1
values[20]	349	1			T398	15		T422	3		T832	1
values[21]	328	1			T398	6		T422	1		T832	1
values[22]	316	1			T398	10		T422	3		T832	1
values[23]	321	1			T398	6		T422	3		T832	1
values[24]	340	1			T398	5		T422	2		T832	1
values[25]	314	1			T398	3		T422	5		T832	1
values[26]	274	1			T398	8		T422	5		T832	1
values[27]	300	1			T398	3		T422	6		T832	1
values[28]	316	1			T398	3		T422	4		T832	1
values[29]	302	1			T398	5		T422	3		T832	1
values[30]	382	1			T398	18		T422	5		T832	1
values[31]	358	1			T398	11		T422	7		T832	1
values[32]	306	1			T398	5		T422	3		T832	1
values[33]	317	1			T398	5		T422	2		T832	1
values[34]	304	1			T398	11		T422	2		T832	1
values[35]	273	1			T398	8		T422	5		T832	1
values[36]	284	1			T398	5		T422	7		T832	1
values[37]	297	1			T398	10		T422	3		T832	1
values[38]	282	1			T398	6		T422	1		T832	1
values[39]	311	1			T398	6		T422	3		T832	1
values[40]	361	1			T398	9		T422	3		T832	1
values[41]	330	1			T398	20		T422	4		T832	1
values[42]	377	1			T398	16		T422	2		T832	1
values[43]	336	1			T398	6		T422	10		T832	1
values[44]	313	1			T398	6		T422	12		T832	1
values[45]	285	1			T398	5		T422	9		T832	1
values[46]	273	1			T398	3		T422	5		T832	1
values[47]	310	1			T398	8		T422	3		T832	1
values[48]	304	1			T398	5		T422	3		T832	1
values[49]	319	1			T398	4		T422	2		T832	1
values[50]	278	1			T398	6		T422	1		T832	1
values[51]	270	1			T398	2		T422	3		T832	1
values[52]	281	1			T398	10		T422	1		T832	1
values[53]	240	1			T398	4		T422	2		T832	1
values[54]	248	1			T398	10		T422	4		T832	1
values[55]	212	1			T398	4		T422	5		T832	1
values[56]	258	1			T398	9		T422	9		T832	1
values[57]	254	1			T398	10		T422	10		T832	1
values[58]	225	1			T398	8		T422	2		T832	1
values[59]	211	1			T398	16		T422	3		T832	1
values[60]	210	1			T398	5		T422	7		T832	1
values[61]	177	1			T398	6		T422	1		T832	1
values[62]	223	1			T398	3		T422	3		T832	1
values[63]	232	1			T398	12		T422	2		T832	1
values[64]	230	1			T398	7		T422	12		T832	1
values[65]	203	1			T398	18		T422	12		T832	1
values[66]	130	1			T398	2		T422	15		T832	1
values[67]	212	1			T398	11		T422	28		T832	1
values[68]	180	1			T398	9		T422	21		T832	1
values[69]	148	1			T398	11		T422	14		T832	1
values[70]	137	1			T398	3		T422	14		T832	1
values[71]	125	1			T398	2		T422	15		T832	1
values[72]	126	1			T422	5		T832	1		T853	1
values[73]	113	1			T422	9		T832	1		T853	1
values[74]	105	1			T422	7		T832	1		T853	1
values[75]	104	1			T422	8		T832	1		T853	1
values[76]	118	1			T422	6		T832	1		T853	1
values[77]	101	1			T422	8		T832	1		T853	1
values[78]	97	1			T422	3		T832	1		T853	1
values[79]	87	1			T422	4		T832	1		T853	1
values[80]	92	1			T422	5		T832	1		T853	1
values[81]	104	1			T422	16		T832	1		T853	1
values[82]	108	1			T422	7		T832	1		T853	1
values[83]	91	1			T422	6		T832	1		T853	1
values[84]	104	1			T422	5		T832	1		T853	1
values[85]	104	1			T422	8		T832	1		T853	1
values[86]	141	1			T422	21		T832	1		T853	1
values[87]	122	1			T422	13		T832	1		T853	1
values[88]	75	1			T422	4		T832	1		T853	1
values[89]	83	1			T422	2		T832	1		T853	1
values[90]	84	1			T422	2		T832	1		T853	1
values[91]	78	1			T422	3		T832	1		T853	2
values[92]	78	1			T422	1		T832	1		T853	2
values[93]	85	1			T422	1		T832	1		T853	8
values[94]	97	1			T832	1		T853	3		T472	2
values[95]	77	1			T832	1		T853	2		T472	2
values[96]	83	1			T832	1		T853	2		T472	5
values[97]	79	1			T832	1		T853	6		T472	4
values[98]	97	1			T832	1		T853	3		T472	2
values[99]	96	1			T832	2		T853	2		T472	12
values[100]	110	1			T832	1		T853	3		T472	5
values[101]	67	1			T832	1		T853	3		T472	6
values[102]	71	1			T832	1		T853	5		T472	2
values[103]	86	1			T832	1		T853	2		T472	4
values[104]	76	1			T832	1		T853	3		T472	1
values[105]	69	1			T832	1		T853	2		T472	4
values[106]	61	1			T832	1		T853	1		T472	6
values[107]	71	1			T832	1		T853	2		T472	8
values[108]	65	1			T832	2		T853	3		T472	1
values[109]	54	1			T832	2		T853	1		T472	2
values[110]	61	1			T832	6		T853	2		T472	4
values[111]	54	1			T832	1		T853	3		T472	6
values[112]	65	1			T832	1		T853	11		T472	10
values[113]	58	1			T832	1		T853	1		T472	12
values[114]	70	1			T832	2		T853	2		T472	12
values[115]	77	1			T832	2		T853	1		T472	9
values[116]	88	1			T832	3		T853	1		T472	9
values[117]	54	1			T832	4		T853	1		T472	4
values[118]	69	1			T832	1		T853	2		T472	3
values[119]	73	1			T832	1		T853	3		T472	3
values[120]	65	1			T832	4		T853	2		T472	8
values[121]	51	1			T832	2		T853	3		T472	5
values[122]	56	1			T832	2		T853	2		T472	1
values[123]	49	1			T832	1		T853	2		T846	1
values[124]	76	1			T832	1		T853	3		T846	2
values[125]	87	1			T832	3		T853	1		T846	1
values[126]	139	1			T832	3		T853	2		T846	3
values[127]	552	1			T832	36		T853	31		T846	30
values[128]	3523	1			T832	332		T853	236		T846	246