Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.29	95.43	94.62	95.05		95.30	97.75	99.59

Total tests in report: 2846

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
42.73	42.73	55.22	55.22	48.79	48.79	23.36	23.36			66.57	66.57	62.34	62.34	0.13	0.13	/workspace/coverage/default/1.chip_sw_plic_sw_irq.236866136
51.90	9.17	63.16	7.94	57.05	8.26	26.38	3.01			74.24	7.67	90.17	27.83	0.42	0.29	/workspace/coverage/default/1.chip_jtag_csr_rw.1594894949
58.35	6.45	63.55	0.39	62.02	4.96	26.47	0.09			75.20	0.96	90.17	0.00	32.70	32.28	/workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.3349142328
62.61	4.26	74.07	10.53	62.68	0.66	33.88	7.41			75.41	0.21	90.17	0.00	39.46	6.76	/workspace/coverage/cover_reg_top/85.xbar_error_random.3840723014
65.98	3.37	75.79	1.71	65.21	2.53	46.36	12.48			77.36	1.95	91.09	0.93	40.08	0.62	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2780080726
68.99	3.01	79.10	3.31	73.02	7.81	46.96	0.60			82.65	5.30	91.09	0.00	41.14	1.06	/workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.1243851513
71.59	2.59	79.10	0.00	73.02	0.00	62.47	15.51			82.65	0.00	91.09	0.00	41.19	0.05	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2820277971
74.18	2.59	79.10	0.00	73.05	0.03	62.47	0.00			82.65	0.00	91.09	0.00	56.69	15.50	/workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.2376717893
76.50	2.32	84.30	5.20	76.85	3.80	65.91	3.44			84.16	1.51	91.09	0.00	56.69	0.00	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3627591598
78.75	2.25	84.54	0.24	77.01	0.16	78.44	12.53			84.35	0.18	91.47	0.37	56.69	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3001136871
80.59	1.84	84.54	0.00	77.01	0.00	78.44	0.00			84.35	0.00	91.47	0.00	67.74	11.06	/workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.237627770
82.06	1.47	86.82	2.29	79.21	2.20	80.23	1.79			86.87	2.52	91.47	0.00	67.74	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.1615420723
83.24	1.18	86.82	0.00	79.75	0.54	80.23	0.00			87.06	0.19	91.47	0.00	74.11	6.37	/workspace/coverage/cover_reg_top/62.xbar_stress_all.1645210813
84.24	1.00	88.34	1.52	81.98	2.23	80.50	0.27			89.04	1.98	91.47	0.00	74.11	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3186764552
85.06	0.82	89.30	0.96	82.37	0.39	83.65	3.15			89.29	0.25	91.65	0.19	74.11	0.00	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1654299578
85.88	0.82	89.31	0.01	82.67	0.30	83.65	0.00			89.30	0.01	91.65	0.00	78.72	4.61	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.2029991635
86.68	0.79	89.98	0.68	83.22	0.55	86.04	2.39			89.92	0.62	91.84	0.19	79.05	0.33	/workspace/coverage/default/0.chip_jtag_csr_rw.3050907304
87.46	0.79	89.98	0.00	83.22	0.00	86.04	0.00			89.92	0.00	91.84	0.00	83.76	4.71	/workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.3094994556
88.21	0.75	90.16	0.18	83.34	0.12	86.06	0.02			90.04	0.12	95.92	4.08	83.76	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2934720499
88.80	0.59	90.17	0.01	86.46	3.12	86.06	0.00			90.04	0.00	95.92	0.00	84.17	0.41	/workspace/coverage/cover_reg_top/28.chip_tl_errors.1595210442
89.38	0.58	91.37	1.20	87.38	0.92	86.32	0.26			91.14	1.10	95.92	0.00	84.17	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.1624795496
89.92	0.54	91.37	0.00	87.67	0.29	86.32	0.00			91.22	0.08	95.92	0.00	87.02	2.84	/workspace/coverage/cover_reg_top/99.xbar_stress_all.3164782399
90.41	0.49	92.09	0.71	88.65	0.98	86.75	0.43			92.04	0.82	95.92	0.00	87.02	0.00	/workspace/coverage/default/1.chip_sw_gpio.1076205672
90.88	0.46	92.89	0.81	89.55	0.90	86.97	0.21			92.71	0.67	96.10	0.19	87.03	0.01	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3999566197
91.33	0.46	92.89	0.00	89.57	0.03	86.97	0.00			92.71	0.00	96.10	0.00	89.74	2.71	/workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.8513703
91.71	0.38	92.89	0.00	89.57	0.00	86.97	0.00			92.71	0.00	96.10	0.00	92.00	2.26	/workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.545198242
92.07	0.37	93.31	0.42	89.93	0.36	87.42	0.45			93.13	0.42	96.66	0.56	92.00	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2375321324
92.41	0.34	93.31	0.00	89.93	0.00	88.44	1.03			93.13	0.00	96.66	0.00	93.01	1.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1997957084
92.66	0.25	93.33	0.01	89.93	0.01	89.88	1.44			93.13	0.00	96.66	0.00	93.04	0.04	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2447673792
92.91	0.24	93.80	0.48	90.38	0.44	90.00	0.11			93.55	0.42	96.66	0.00	93.04	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.1765980877
93.14	0.24	93.80	0.00	90.38	0.00	90.00	0.00			93.55	0.00	96.66	0.00	94.47	1.42	/workspace/coverage/cover_reg_top/85.xbar_access_same_device.861396765
93.36	0.22	93.93	0.12	90.88	0.51	90.12	0.13			94.09	0.54	96.66	0.00	94.47	0.00	/workspace/coverage/default/2.chip_jtag_csr_rw.3783749749
93.57	0.21	93.93	0.00	90.90	0.01	90.12	0.00			94.09	0.00	96.66	0.00	95.71	1.25	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.810267862
93.73	0.16	94.16	0.23	91.23	0.33	90.55	0.43			94.09	0.00	96.66	0.00	95.71	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1492016117
93.88	0.14	94.16	0.00	91.23	0.01	90.55	0.00			94.09	0.00	96.66	0.00	96.57	0.86	/workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1012413024
94.02	0.14	94.16	0.00	91.25	0.01	90.57	0.02			94.09	0.00	96.66	0.00	97.39	0.82	/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3045782440
94.14	0.12	94.19	0.03	91.34	0.09	90.93	0.36			94.14	0.05	96.85	0.19	97.40	0.01	/workspace/coverage/default/93.chip_sw_all_escalation_resets.2336984968
94.25	0.11	94.19	0.00	91.34	0.00	91.61	0.68			94.14	0.00	96.85	0.00	97.40	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3400976911
94.35	0.10	94.19	0.01	91.60	0.27	91.63	0.02			94.43	0.28	96.85	0.00	97.40	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3368542172
94.44	0.09	94.27	0.08	91.96	0.36	91.63	0.00			94.55	0.12	96.85	0.00	97.40	0.00	/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3194916865
94.53	0.08	94.31	0.03	91.98	0.02	92.06	0.42			94.58	0.02	96.85	0.00	97.40	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3274196219
94.61	0.08	94.41	0.10	92.16	0.18	92.15	0.10			94.68	0.10	96.85	0.00	97.40	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.1520968385
94.69	0.08	94.41	0.00	92.16	0.00	92.63	0.47			94.68	0.00	96.85	0.00	97.40	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1463772475
94.76	0.07	94.41	0.00	92.60	0.44	92.63	0.00			94.68	0.00	96.85	0.00	97.40	0.00	/workspace/coverage/cover_reg_top/4.chip_tl_errors.1400158832
94.83	0.07	94.41	0.00	92.67	0.07	92.63	0.00			94.68	0.00	96.85	0.00	97.77	0.36	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1316601418
94.90	0.07	94.58	0.17	92.82	0.15	92.63	0.00			94.77	0.09	96.85	0.00	97.77	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3877833395
94.97	0.07	94.58	0.01	92.84	0.02	92.83	0.20			94.77	0.00	97.03	0.19	97.77	0.00	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.4093047460
95.03	0.06	94.69	0.11	92.93	0.09	92.88	0.05			94.87	0.10	97.03	0.00	97.77	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3415745918
95.08	0.05	94.72	0.03	92.96	0.03	92.91	0.03			94.89	0.02	97.22	0.19	97.78	0.01	/workspace/coverage/default/32.chip_sw_all_escalation_resets.322672310
95.13	0.05	94.72	0.00	92.96	0.00	92.91	0.00			94.89	0.00	97.22	0.00	98.06	0.28	/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.1427408078
95.17	0.04	94.72	0.00	92.96	0.00	93.18	0.26			94.89	0.00	97.22	0.00	98.06	0.00	/workspace/coverage/default/1.chip_sw_kmac_entropy.1920329835
95.22	0.04	94.72	0.00	92.96	0.00	93.18	0.00			94.89	0.00	97.22	0.00	98.32	0.26	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.4083417326
95.26	0.04	94.72	0.00	92.96	0.00	93.42	0.24			94.89	0.00	97.22	0.00	98.32	0.00	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.4271494557
95.30	0.04	94.73	0.01	92.97	0.01	93.44	0.02			94.90	0.01	97.40	0.19	98.33	0.01	/workspace/coverage/default/38.chip_sw_all_escalation_resets.1337726454
95.33	0.04	94.73	0.00	93.09	0.12	93.44	0.00			95.02	0.12	97.40	0.00	98.33	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2447082192
95.37	0.04	94.77	0.04	93.16	0.07	93.51	0.07			95.07	0.05	97.40	0.00	98.33	0.00	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.996876398
95.41	0.04	94.77	0.01	93.17	0.01	93.51	0.01			95.08	0.01	97.59	0.19	98.34	0.01	/workspace/coverage/default/67.chip_sw_all_escalation_resets.3012728406
95.45	0.04	94.85	0.08	93.17	0.00	93.66	0.14			95.08	0.01	97.59	0.00	98.34	0.00	/workspace/coverage/default/3.chip_tap_straps_testunlock0.2107740008
95.48	0.03	94.85	0.01	93.18	0.01	93.84	0.18			95.08	0.00	97.59	0.00	98.35	0.01	/workspace/coverage/default/1.rom_e2e_shutdown_output.2526351040
95.52	0.03	94.85	0.00	93.18	0.00	94.04	0.20			95.08	0.00	97.59	0.00	98.35	0.00	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3483004196
95.55	0.03	94.85	0.00	93.18	0.00	94.04	0.01			95.08	0.00	97.77	0.19	98.35	0.00	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.3338171896
95.58	0.03	94.85	0.00	93.37	0.19	94.04	0.00			95.08	0.00	97.77	0.00	98.35	0.00	/workspace/coverage/cover_reg_top/26.chip_tl_errors.1276648331
95.60	0.02	94.92	0.07	93.40	0.03	94.04	0.00			95.13	0.05	97.77	0.00	98.35	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2319189893
95.63	0.02	94.92	0.00	93.40	0.00	94.18	0.15			95.13	0.00	97.77	0.00	98.35	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2934306863
95.65	0.02	94.92	0.00	93.51	0.11	94.18	0.00			95.17	0.03	97.77	0.00	98.35	0.00	/workspace/coverage/cover_reg_top/91.xbar_stress_all.2696160607
95.68	0.02	94.92	0.00	93.51	0.00	94.32	0.14			95.17	0.00	97.77	0.00	98.35	0.00	/workspace/coverage/default/0.chip_sw_aes_entropy.1352938503
95.70	0.02	94.92	0.00	93.65	0.14	94.32	0.00			95.17	0.00	97.77	0.00	98.35	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.542555351
95.72	0.02	94.93	0.01	93.67	0.01	94.33	0.01			95.18	0.02	97.77	0.00	98.43	0.07	/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.421964673
95.74	0.02	94.96	0.03	93.70	0.03	94.37	0.03			95.20	0.02	97.77	0.00	98.43	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.10695388
95.75	0.02	94.96	0.00	93.70	0.00	94.45	0.09			95.20	0.00	97.77	0.00	98.44	0.01	/workspace/coverage/default/39.chip_sw_all_escalation_resets.1532529421
95.77	0.01	94.97	0.01	93.70	0.01	94.52	0.07			95.21	0.01	97.77	0.00	98.44	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.2983222886
95.78	0.01	94.97	0.00	93.71	0.01	94.60	0.08			95.21	0.00	97.77	0.00	98.44	0.00	/workspace/coverage/cover_reg_top/17.chip_csr_rw.3021378116
95.80	0.01	94.97	0.00	93.77	0.07	94.60	0.00			95.23	0.02	97.77	0.00	98.44	0.00	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.837394714
95.81	0.01	94.97	0.00	93.77	0.00	94.68	0.08			95.23	0.00	97.77	0.00	98.44	0.00	/workspace/coverage/default/0.rom_raw_unlock.4000224892
95.82	0.01	94.97	0.00	93.82	0.04	94.68	0.00			95.23	0.00	97.77	0.00	98.47	0.04	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.1305163520
95.83	0.01	94.97	0.00	93.88	0.06	94.68	0.00			95.23	0.00	97.77	0.00	98.48	0.01	/workspace/coverage/cover_reg_top/15.chip_tl_errors.109328283
95.85	0.01	94.97	0.00	93.95	0.07	94.68	0.00			95.23	0.00	97.77	0.00	98.48	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.3008749072
95.86	0.01	95.01	0.04	93.97	0.02	94.68	0.01			95.23	0.01	97.77	0.00	98.48	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3111576211
95.87	0.01	95.01	0.00	93.97	0.00	94.68	0.00			95.23	0.00	97.77	0.00	98.55	0.07	/workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.3351167101
95.88	0.01	95.04	0.04	94.00	0.03	94.68	0.00			95.24	0.01	97.77	0.00	98.55	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2406642804
95.89	0.01	95.04	0.00	94.03	0.03	94.68	0.00			95.24	0.00	97.77	0.00	98.59	0.04	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.1594854535
95.90	0.01	95.04	0.00	94.09	0.06	94.68	0.00			95.24	0.00	97.77	0.00	98.59	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.1217640964
95.91	0.01	95.04	0.00	94.14	0.05	94.68	0.00			95.24	0.00	97.77	0.00	98.59	0.00	/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.3357151096
95.92	0.01	95.04	0.00	94.15	0.01	94.69	0.01			95.24	0.00	97.77	0.00	98.63	0.04	/workspace/coverage/default/0.chip_sw_alert_test.3561436661
95.93	0.01	95.04	0.00	94.21	0.05	94.69	0.00			95.24	0.00	97.77	0.00	98.63	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3170691557
95.94	0.01	95.06	0.02	94.22	0.01	94.69	0.00			95.26	0.02	97.77	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3940430218
95.95	0.01	95.06	0.00	94.22	0.00	94.69	0.00			95.26	0.00	97.77	0.00	98.67	0.05	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.1886530513
95.95	0.01	95.07	0.01	94.23	0.01	94.71	0.02			95.26	0.00	97.77	0.00	98.67	0.00	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.818725539
95.96	0.01	95.07	0.00	94.27	0.04	94.71	0.00			95.26	0.00	97.77	0.00	98.67	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.1123142780
95.97	0.01	95.08	0.01	94.29	0.01	94.72	0.01			95.26	0.00	97.77	0.00	98.67	0.00	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3765062301
95.97	0.01	95.08	0.00	94.31	0.03	94.72	0.00			95.27	0.01	97.77	0.00	98.67	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2387179783
95.98	0.01	95.08	0.00	94.34	0.03	94.72	0.00			95.27	0.00	97.77	0.00	98.68	0.01	/workspace/coverage/cover_reg_top/2.chip_tl_errors.402050833
95.98	0.01	95.08	0.00	94.34	0.00	94.72	0.00			95.27	0.00	97.77	0.00	98.72	0.04	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.3023107943
95.99	0.01	95.08	0.00	94.34	0.01	94.75	0.03			95.27	0.00	97.77	0.00	98.72	0.00	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2888159840
95.99	0.01	95.08	0.00	94.34	0.00	94.78	0.03			95.27	0.00	97.77	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.626817207
96.00	0.01	95.08	0.00	94.38	0.03	94.78	0.00			95.27	0.00	97.77	0.00	98.72	0.00	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.1671341220
96.01	0.01	95.08	0.00	94.38	0.00	94.81	0.03			95.27	0.00	97.77	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1939340014
96.01	0.01	95.08	0.00	94.41	0.03	94.81	0.00			95.27	0.00	97.77	0.00	98.72	0.00	/workspace/coverage/cover_reg_top/24.xbar_stress_all.991473062
96.02	0.01	95.08	0.00	94.41	0.00	94.84	0.03			95.27	0.00	97.77	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2540836373
96.02	0.01	95.08	0.00	94.41	0.00	94.87	0.03			95.27	0.00	97.77	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.304529474
96.02	0.01	95.08	0.00	94.43	0.03	94.87	0.00			95.27	0.00	97.77	0.00	98.72	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.2399293520
96.03	0.01	95.08	0.00	94.43	0.00	94.88	0.01			95.27	0.00	97.77	0.00	98.73	0.01	/workspace/coverage/default/55.chip_sw_all_escalation_resets.308858421
96.03	0.01	95.08	0.00	94.43	0.00	94.90	0.02			95.27	0.00	97.77	0.00	98.73	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2045929132
96.04	0.01	95.08	0.00	94.43	0.00	94.90	0.00			95.27	0.00	97.77	0.00	98.75	0.02	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.3251421058
96.04	0.01	95.09	0.01	94.44	0.01	94.90	0.00			95.28	0.01	97.77	0.00	98.75	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3618185025
96.04	0.01	95.09	0.01	94.44	0.00	94.92	0.02			95.28	0.00	97.77	0.00	98.75	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.2662364269
96.05	0.01	95.09	0.00	94.44	0.00	94.94	0.02			95.28	0.00	97.77	0.00	98.75	0.00	/workspace/coverage/default/0.chip_sw_usbdev_config_host.1943551589
96.05	0.01	95.09	0.00	94.46	0.02	94.94	0.00			95.28	0.00	97.77	0.00	98.75	0.00	/workspace/coverage/cover_reg_top/17.chip_tl_errors.2085347850
96.05	0.01	95.09	0.00	94.46	0.00	94.94	0.01			95.28	0.00	97.77	0.00	98.77	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.38493097
96.05	0.01	95.09	0.00	94.46	0.00	94.95	0.01			95.28	0.00	97.77	0.00	98.78	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.3147248728
96.06	0.01	95.09	0.00	94.46	0.00	94.95	0.01			95.28	0.00	97.77	0.00	98.79	0.01	/workspace/coverage/default/35.chip_sw_all_escalation_resets.1227516417
96.06	0.01	95.09	0.00	94.46	0.01	94.96	0.01			95.28	0.00	97.77	0.00	98.79	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.3557063405
96.06	0.01	95.09	0.00	94.47	0.01	94.96	0.00			95.28	0.01	97.77	0.00	98.79	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2205178700
96.06	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	98.80	0.01	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.673333758
96.07	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	98.81	0.01	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.3694867993
96.07	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	98.82	0.01	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.2094459043
96.07	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	98.84	0.01	/workspace/coverage/cover_reg_top/31.xbar_stress_all.3450467826
96.07	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	98.85	0.01	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.944795862
96.07	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	98.86	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2272967210
96.07	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	98.87	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.3454417977
96.08	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	98.88	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1328422573
96.08	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	98.90	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.2789277184
96.08	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	98.91	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.496139392
96.08	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	98.92	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3588677987
96.08	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	98.93	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.4087867024
96.09	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	98.94	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.2044405688
96.09	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	98.95	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.2394192328
96.09	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	98.97	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3394236255
96.09	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	98.98	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1818482141
96.09	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	98.99	0.01	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.947273581
96.10	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.00	0.01	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3359027511
96.10	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.01	0.01	/workspace/coverage/default/2.chip_sw_all_escalation_resets.2857406690
96.10	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.02	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3825579378
96.10	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.04	0.01	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2788999954
96.10	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.05	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.1157644173
96.11	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.06	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2935426173
96.11	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.07	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.677475351
96.11	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.08	0.01	/workspace/coverage/default/23.chip_sw_all_escalation_resets.262679311
96.11	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.10	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.466550858
96.11	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.11	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.2732797361
96.12	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.12	0.01	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1811928524
96.12	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.13	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.2245276835
96.12	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.14	0.01	/workspace/coverage/default/28.chip_sw_all_escalation_resets.1470474866
96.12	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.15	0.01	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1056209418
96.12	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.17	0.01	/workspace/coverage/default/29.chip_sw_all_escalation_resets.1939675649
96.13	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.18	0.01	/workspace/coverage/default/30.chip_sw_all_escalation_resets.2262257903
96.13	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.19	0.01	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3522709377
96.13	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.20	0.01	/workspace/coverage/default/33.chip_sw_all_escalation_resets.2893533337
96.13	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.21	0.01	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1716283556
96.13	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.22	0.01	/workspace/coverage/default/34.chip_sw_all_escalation_resets.4078190459
96.14	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.24	0.01	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1913560728
96.14	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.25	0.01	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3398591300
96.14	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.26	0.01	/workspace/coverage/default/37.chip_sw_all_escalation_resets.3711012998
96.14	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.27	0.01	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3142554685
96.14	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.28	0.01	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3656946642
96.15	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.29	0.01	/workspace/coverage/default/41.chip_sw_all_escalation_resets.1180822181
96.15	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.31	0.01	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.71290280
96.15	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.32	0.01	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3255612765
96.15	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.33	0.01	/workspace/coverage/default/44.chip_sw_all_escalation_resets.1113277891
96.15	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.34	0.01	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.768287525
96.16	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.35	0.01	/workspace/coverage/default/47.chip_sw_all_escalation_resets.812445495
96.16	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.37	0.01	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.339909389
96.16	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.38	0.01	/workspace/coverage/default/50.chip_sw_all_escalation_resets.253576600
96.16	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.39	0.01	/workspace/coverage/default/51.chip_sw_all_escalation_resets.1080803233
96.16	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.40	0.01	/workspace/coverage/default/52.chip_sw_all_escalation_resets.3052956447
96.16	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.41	0.01	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1048760066
96.17	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.42	0.01	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1414943272
96.17	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.44	0.01	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2714319938
96.17	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.45	0.01	/workspace/coverage/default/61.chip_sw_all_escalation_resets.868210276
96.17	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.46	0.01	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.410377431
96.17	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.47	0.01	/workspace/coverage/default/66.chip_sw_all_escalation_resets.2949900496
96.18	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.48	0.01	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3320172071
96.18	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.49	0.01	/workspace/coverage/default/68.chip_sw_all_escalation_resets.4053519324
96.18	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.51	0.01	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2130458136
96.18	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.52	0.01	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.4209662747
96.18	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.53	0.01	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.550363024
96.19	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.54	0.01	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1739859516
96.19	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.55	0.01	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.884266249
96.19	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.57	0.01	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3662835781
96.19	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.58	0.01	/workspace/coverage/default/78.chip_sw_all_escalation_resets.982950014
96.19	0.01	95.09	0.00	94.47	0.00	94.96	0.00			95.28	0.00	97.77	0.00	99.59	0.01	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1708984229
96.20	0.01	95.09	0.00	94.48	0.01	94.96	0.00			95.28	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.399617778
96.20	0.01	95.09	0.00	94.49	0.01	94.96	0.00			95.28	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/21.chip_tl_errors.3600440570
96.20	0.01	95.09	0.00	94.50	0.01	94.96	0.00			95.28	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/28.xbar_stress_all.2204043839
96.20	0.01	95.09	0.00	94.51	0.01	94.96	0.00			95.28	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.3382615224
96.20	0.01	95.09	0.00	94.52	0.01	94.96	0.00			95.28	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2702123797
96.21	0.01	95.10	0.01	94.53	0.01	94.96	0.00			95.28	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3130929113
96.21	0.01	95.10	0.01	94.53	0.00	94.97	0.01			95.28	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/86.chip_sw_all_escalation_resets.174776323
96.21	0.01	95.11	0.01	94.53	0.00	94.97	0.01			95.28	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/1.chip_sw_pattgen_ios.599188874
96.21	0.01	95.11	0.00	94.53	0.00	94.98	0.01			95.28	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.1713934560
96.21	0.01	95.11	0.00	94.53	0.00	94.99	0.01			95.28	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.3645757711
96.21	0.01	95.11	0.00	94.53	0.00	95.00	0.01			95.28	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3529065397
96.21	0.01	95.11	0.00	94.53	0.00	95.01	0.01			95.28	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3815224402
96.22	0.01	95.11	0.00	94.53	0.00	95.02	0.01			95.28	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1772020306
96.22	0.01	95.11	0.00	94.53	0.00	95.02	0.00			95.29	0.01	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.924110423
96.22	0.01	95.11	0.00	94.53	0.00	95.02	0.00			95.30	0.01	97.77	0.00	99.59	0.00	/workspace/coverage/default/1.chip_tap_straps_dev.1611790372
96.22	0.01	95.11	0.00	94.53	0.01	95.02	0.00			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3228582869
96.22	0.01	95.11	0.00	94.54	0.01	95.02	0.00			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.2499507164
96.22	0.01	95.11	0.00	94.55	0.01	95.02	0.00			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.583982579
96.22	0.01	95.11	0.00	94.55	0.01	95.02	0.00			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/43.xbar_random.3605247408
96.23	0.01	95.11	0.00	94.56	0.01	95.02	0.00			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.1007137832
96.23	0.01	95.11	0.00	94.57	0.01	95.02	0.00			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2142676406
96.23	0.01	95.11	0.00	94.58	0.01	95.02	0.00			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1357553778
96.23	0.01	95.11	0.00	94.58	0.01	95.02	0.00			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.115742492
96.23	0.01	95.12	0.01	94.58	0.00	95.02	0.00			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3374971563
96.23	0.01	95.13	0.01	94.58	0.00	95.02	0.00			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1079567490
96.23	0.01	95.13	0.01	94.58	0.00	95.02	0.00			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.2545453658
96.23	0.01	95.14	0.01	94.58	0.00	95.02	0.00			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_power_idle_load.190117201
96.24	0.01	95.14	0.00	94.58	0.00	95.02	0.01			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3878002993
96.24	0.01	95.14	0.00	94.58	0.00	95.03	0.01			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1036284890
96.24	0.01	95.14	0.00	94.58	0.00	95.03	0.01			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3268066030
96.24	0.01	95.14	0.00	94.59	0.01	95.03	0.00			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.1187114710
96.24	0.01	95.14	0.00	94.59	0.01	95.03	0.00			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.861335113
96.24	0.01	95.14	0.00	94.59	0.01	95.03	0.00			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/24.chip_tl_errors.2182405485
96.24	0.01	95.14	0.00	94.60	0.01	95.03	0.00			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/29.chip_tl_errors.2286846159
96.24	0.01	95.14	0.00	94.60	0.01	95.03	0.00			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.84189107
96.24	0.01	95.14	0.00	94.61	0.01	95.03	0.00			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.1712586456
96.24	0.01	95.14	0.00	94.61	0.01	95.03	0.00			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.1551264651
96.24	0.01	95.14	0.00	94.61	0.01	95.03	0.00			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.2147279889
96.24	0.01	95.14	0.00	94.62	0.01	95.03	0.00			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1288508958
96.24	0.01	95.14	0.00	94.62	0.00	95.03	0.01			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1479315354
96.24	0.01	95.14	0.00	94.62	0.00	95.04	0.01			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_edn_auto_mode.3555595227
96.24	0.01	95.14	0.00	94.62	0.00	95.04	0.01			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2462686410
96.24	0.01	95.14	0.00	94.62	0.00	95.04	0.01			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2941164934
96.24	0.01	95.14	0.00	94.62	0.00	95.04	0.01			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.395143806
96.24	0.01	95.14	0.00	94.62	0.00	95.05	0.01			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1799833692
96.24	0.01	95.14	0.00	94.62	0.00	95.05	0.01			95.30	0.00	97.77	0.00	99.59	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4122427850

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3496842532
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2264303911
/workspace/coverage/cover_reg_top/0.chip_csr_rw.580068108
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2763074082
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2937260562
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3870820003
/workspace/coverage/cover_reg_top/0.chip_tl_errors.4146124351
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.3247512321
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1847212073
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.68200675
/workspace/coverage/cover_reg_top/0.xbar_error_random.2750907882
/workspace/coverage/cover_reg_top/0.xbar_random.2043489070
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2349016258
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.2959204736
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2913850095
/workspace/coverage/cover_reg_top/0.xbar_same_source.403435441
/workspace/coverage/cover_reg_top/0.xbar_smoke.682919510
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.406300139
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.74549343
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.839364431
/workspace/coverage/cover_reg_top/0.xbar_stress_all.1833231222
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2010060765
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3079263001
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.188978594
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.4189967117
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.4252696234
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2873408046
/workspace/coverage/cover_reg_top/1.chip_csr_rw.3393716856
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.3602886554
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.398175818
/workspace/coverage/cover_reg_top/1.chip_tl_errors.1190827632
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.3328402986
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.224453343
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3131901888
/workspace/coverage/cover_reg_top/1.xbar_error_random.2089294356
/workspace/coverage/cover_reg_top/1.xbar_random.233139541
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.3555199478
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1618651521
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3081623225
/workspace/coverage/cover_reg_top/1.xbar_same_source.3604548650
/workspace/coverage/cover_reg_top/1.xbar_smoke.3686203181
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.641192712
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.4184083823
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1677000138
/workspace/coverage/cover_reg_top/1.xbar_stress_all.353610731
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.2856282936
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3497185143
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1943825740
/workspace/coverage/cover_reg_top/10.chip_csr_rw.1225746678
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2410146148
/workspace/coverage/cover_reg_top/10.chip_tl_errors.1442719389
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.2632286819
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2672217285
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2794404798
/workspace/coverage/cover_reg_top/10.xbar_error_random.1302137946
/workspace/coverage/cover_reg_top/10.xbar_random.3135921991
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.841189346
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1450867562
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.2556991643
/workspace/coverage/cover_reg_top/10.xbar_same_source.320055565
/workspace/coverage/cover_reg_top/10.xbar_smoke.1791859284
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.4132911705
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.395601405
/workspace/coverage/cover_reg_top/10.xbar_stress_all.2627811570
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.4098820983
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3579542508
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3745709614
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.470730268
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2572118449
/workspace/coverage/cover_reg_top/11.chip_tl_errors.172127121
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.1465186490
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2989965335
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.716618955
/workspace/coverage/cover_reg_top/11.xbar_error_random.2183221236
/workspace/coverage/cover_reg_top/11.xbar_random.1974785900
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.2003983980
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.1432638457
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1020831442
/workspace/coverage/cover_reg_top/11.xbar_same_source.1518126880
/workspace/coverage/cover_reg_top/11.xbar_smoke.3252902965
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.82089575
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.1864711141
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2357056334
/workspace/coverage/cover_reg_top/11.xbar_stress_all.3679592462
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3987777460
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1533000040
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1597175660
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2125038759
/workspace/coverage/cover_reg_top/12.chip_csr_rw.4276368345
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.663061313
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2343870058
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.374668439
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1501522756
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.635231671
/workspace/coverage/cover_reg_top/12.xbar_error_random.3809740885
/workspace/coverage/cover_reg_top/12.xbar_random.2045572642
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1738992741
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3386081375
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.217672314
/workspace/coverage/cover_reg_top/12.xbar_same_source.2184722294
/workspace/coverage/cover_reg_top/12.xbar_smoke.1506977678
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3517103748
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.265783934
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.335802957
/workspace/coverage/cover_reg_top/12.xbar_stress_all.3798516357
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3267110148
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.228748912
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.661809625
/workspace/coverage/cover_reg_top/13.chip_csr_rw.4179660761
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1253930102
/workspace/coverage/cover_reg_top/13.chip_tl_errors.3418631995
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.3245024313
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1722279332
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3885630133
/workspace/coverage/cover_reg_top/13.xbar_error_random.278181876
/workspace/coverage/cover_reg_top/13.xbar_random.1731685729
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3799620173
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.666380723
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1334115054
/workspace/coverage/cover_reg_top/13.xbar_same_source.4065939464
/workspace/coverage/cover_reg_top/13.xbar_smoke.967180592
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.1434725209
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3493732426
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/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2370810613
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1263332924
/workspace/coverage/default/3.chip_sw_all_escalation_resets.954655368
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3087604668
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.1757870300
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3738037318
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.584394718
/workspace/coverage/default/3.chip_sw_uart_tx_rx.960259518
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1452798186
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.402585923
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.992153667
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1859543570
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.315566826
/workspace/coverage/default/3.chip_tap_straps_dev.2601569099
/workspace/coverage/default/3.chip_tap_straps_prod.614198706
/workspace/coverage/default/3.chip_tap_straps_rma.4030040489
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.488842254
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3336226162
/workspace/coverage/default/31.chip_sw_all_escalation_resets.3228586768
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2211552262
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2070083335
/workspace/coverage/default/36.chip_sw_all_escalation_resets.1581897667
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2838871116
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1421340687
/workspace/coverage/default/4.chip_sw_all_escalation_resets.2111852735
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3089392944
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1049315703
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1408738914
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2709517084
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2749152140
/workspace/coverage/default/4.chip_sw_uart_tx_rx.4157302137
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2200078083
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1063149610
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2075445431
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2579140855
/workspace/coverage/default/4.chip_tap_straps_dev.979838581
/workspace/coverage/default/4.chip_tap_straps_prod.452193813
/workspace/coverage/default/4.chip_tap_straps_rma.2254221907
/workspace/coverage/default/4.chip_tap_straps_testunlock0.545277163
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.482199554
/workspace/coverage/default/40.chip_sw_all_escalation_resets.3759538171
/workspace/coverage/default/42.chip_sw_all_escalation_resets.1966064747
/workspace/coverage/default/43.chip_sw_all_escalation_resets.1463720282
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2097614343
/workspace/coverage/default/45.chip_sw_all_escalation_resets.115525052
/workspace/coverage/default/46.chip_sw_all_escalation_resets.2390231711
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2556172160
/workspace/coverage/default/48.chip_sw_all_escalation_resets.1845915374
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1086585105
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1840503151
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3639774812
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2558748324
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2456504834
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.340107382
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1172070789
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.457442527
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.583130112
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3743761065
/workspace/coverage/default/53.chip_sw_all_escalation_resets.1096537536
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2541850782
/workspace/coverage/default/54.chip_sw_all_escalation_resets.306565405
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1410482813
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1508370245
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.808944971
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3132257649
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2120442368
/workspace/coverage/default/58.chip_sw_all_escalation_resets.4135315336
/workspace/coverage/default/59.chip_sw_all_escalation_resets.3531905236
/workspace/coverage/default/6.chip_sw_all_escalation_resets.1056659258
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.819060626
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3493939333
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1224281384
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1422254567
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3168389685
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1136850391
/workspace/coverage/default/63.chip_sw_all_escalation_resets.553220887
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2199763837
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3479205584
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.4016593949
/workspace/coverage/default/65.chip_sw_all_escalation_resets.234093689
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3822441188
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3683115027
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2850288679
/workspace/coverage/default/7.chip_sw_all_escalation_resets.2631528370
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3491782092
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2760180095
/workspace/coverage/default/70.chip_sw_all_escalation_resets.3479549444
/workspace/coverage/default/71.chip_sw_all_escalation_resets.178625579
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1528950875
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2158226142
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1614964724
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2920059810
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1952061838
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3417319897
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2612849365
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.720055669
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2962719970
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.4005326135
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2754803640
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2572883329
/workspace/coverage/default/8.chip_sw_all_escalation_resets.510458525
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1132476350
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.663413458
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3161379398
/workspace/coverage/default/80.chip_sw_all_escalation_resets.965376441
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.803970503
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2460371439
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2831693890
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1522171382
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.4231960449
/workspace/coverage/default/83.chip_sw_all_escalation_resets.551192373
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3351577925
/workspace/coverage/default/84.chip_sw_all_escalation_resets.3851254879
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3299954045
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2714640225
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3333449066
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.813921160
/workspace/coverage/default/87.chip_sw_all_escalation_resets.1398784745
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2854192982
/workspace/coverage/default/88.chip_sw_all_escalation_resets.903987681
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1446922091
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1633779007
/workspace/coverage/default/9.chip_sw_all_escalation_resets.2269935319
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2753556945
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3143299612
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3347383484
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3982083514
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3237962087
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2106544815
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2326338756
/workspace/coverage/default/96.chip_sw_all_escalation_resets.3935836103
/workspace/coverage/default/97.chip_sw_all_escalation_resets.513350731
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3004841171
/workspace/coverage/default/99.chip_sw_all_escalation_resets.3765285712
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1955468206
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1470065021
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3809037769
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.881898957
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3650982986
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3482291480
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3584242121
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2919325650

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Total test records in report: 2846

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tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2942678164			Feb 18 03:54:12 PM PST 24	Feb 18 04:19:13 PM PST 24	8198299856 ps
T2	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2402071072			Feb 18 03:58:53 PM PST 24	Feb 18 04:02:27 PM PST 24	2518120184 ps
T3	/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2114226324			Feb 18 04:07:09 PM PST 24	Feb 18 04:14:24 PM PST 24	4575897268 ps
T38	/workspace/coverage/default/2.chip_sw_spi_device_tpm.624101814			Feb 18 04:08:42 PM PST 24	Feb 18 04:16:10 PM PST 24	3277319008 ps
T67	/workspace/coverage/default/3.chip_tap_straps_testunlock0.2107740008			Feb 18 04:16:23 PM PST 24	Feb 18 04:19:23 PM PST 24	3201898229 ps
T87	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.927084297			Feb 18 04:10:13 PM PST 24	Feb 18 04:15:11 PM PST 24	2716654894 ps
T43	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1654299578			Feb 18 04:20:36 PM PST 24	Feb 18 04:51:16 PM PST 24	9004167092 ps
T88	/workspace/coverage/default/1.chip_sw_plic_sw_irq.236866136			Feb 18 04:03:19 PM PST 24	Feb 18 04:07:21 PM PST 24	2450380592 ps
T34	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3274196219			Feb 18 03:58:35 PM PST 24	Feb 18 04:18:07 PM PST 24	7803917420 ps
T54	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.818725539			Feb 18 04:17:54 PM PST 24	Feb 18 04:54:53 PM PST 24	14549896624 ps
T59	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1414943272			Feb 18 04:22:36 PM PST 24	Feb 18 04:29:16 PM PST 24	3925005812 ps
T4	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.47256298			Feb 18 04:00:00 PM PST 24	Feb 18 07:02:15 PM PST 24	64100936994 ps
T183	/workspace/coverage/default/0.chip_sw_pattgen_ios.2545453658			Feb 18 03:56:15 PM PST 24	Feb 18 04:01:35 PM PST 24	3226708450 ps
T16	/workspace/coverage/default/0.chip_sw_usbdev_vbus.3016997529			Feb 18 03:52:06 PM PST 24	Feb 18 03:55:01 PM PST 24	2879085000 ps
T5	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3001136871			Feb 18 03:59:53 PM PST 24	Feb 18 05:31:27 PM PST 24	49081892424 ps
T174	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3999566197			Feb 18 04:18:45 PM PST 24	Feb 18 04:24:51 PM PST 24	3637805292 ps
T296	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2212222249			Feb 18 03:58:32 PM PST 24	Feb 18 04:12:50 PM PST 24	4735095532 ps
T171	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1525820797			Feb 18 03:58:28 PM PST 24	Feb 18 04:06:25 PM PST 24	3900897216 ps
T64	/workspace/coverage/default/55.chip_sw_all_escalation_resets.308858421			Feb 18 04:21:33 PM PST 24	Feb 18 04:31:17 PM PST 24	5101898220 ps
T314	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2142676406			Feb 18 03:52:11 PM PST 24	Feb 18 04:08:01 PM PST 24	5180608304 ps
T65	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2780080726			Feb 18 03:59:49 PM PST 24	Feb 18 04:33:30 PM PST 24	14019458680 ps
T62	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4263065481			Feb 18 03:53:29 PM PST 24	Feb 18 03:55:13 PM PST 24	2635472855 ps
T66	/workspace/coverage/default/2.chip_sw_flash_crash_alert.1596558035			Feb 18 04:14:43 PM PST 24	Feb 18 04:25:32 PM PST 24	4850880864 ps
T175	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2572883329			Feb 18 04:19:14 PM PST 24	Feb 18 04:26:48 PM PST 24	3904692296 ps
T45	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3111576211			Feb 18 03:52:20 PM PST 24	Feb 18 03:56:27 PM PST 24	3241348406 ps
T101	/workspace/coverage/default/39.chip_sw_all_escalation_resets.1532529421			Feb 18 04:20:24 PM PST 24	Feb 18 04:31:51 PM PST 24	6165697180 ps
T44	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.610107500			Feb 18 04:00:00 PM PST 24	Feb 18 04:34:40 PM PST 24	8351881144 ps
T102	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3922576164			Feb 18 03:58:08 PM PST 24	Feb 18 04:22:03 PM PST 24	5852941296 ps
T13	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.996876398			Feb 18 04:16:56 PM PST 24	Feb 18 04:31:17 PM PST 24	5255819400 ps
T103	/workspace/coverage/default/0.chip_sw_aes_entropy.1352938503			Feb 18 03:56:05 PM PST 24	Feb 18 04:01:37 PM PST 24	3447214864 ps
T104	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.550363024			Feb 18 04:25:17 PM PST 24	Feb 18 04:31:57 PM PST 24	3882782000 ps
T105	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.29735236			Feb 18 04:01:37 PM PST 24	Feb 18 04:07:34 PM PST 24	3510178120 ps
T106	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2447673792			Feb 18 03:54:45 PM PST 24	Feb 18 04:15:17 PM PST 24	5818555432 ps
T107	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1708984229			Feb 18 04:17:39 PM PST 24	Feb 18 04:24:06 PM PST 24	3158708336 ps
T128	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.827621802			Feb 18 04:14:26 PM PST 24	Feb 18 04:22:41 PM PST 24	4093832919 ps
T63	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2330460859			Feb 18 04:01:13 PM PST 24	Feb 18 04:03:21 PM PST 24	2534951286 ps
T6	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.911767724			Feb 18 04:01:01 PM PST 24	Feb 18 04:40:43 PM PST 24	10143124355 ps
T172	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.922994275			Feb 18 04:09:00 PM PST 24	Feb 18 04:28:14 PM PST 24	5887879620 ps
T148	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2412032555			Feb 18 04:02:13 PM PST 24	Feb 18 04:11:49 PM PST 24	5048356337 ps
T178	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1949772209			Feb 18 03:53:36 PM PST 24	Feb 18 03:58:13 PM PST 24	3270996095 ps
T120	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.260714130			Feb 18 04:13:27 PM PST 24	Feb 18 05:06:53 PM PST 24	26732093558 ps
T687	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3168389685			Feb 18 04:22:01 PM PST 24	Feb 18 04:30:27 PM PST 24	3626711132 ps
T668	/workspace/coverage/default/0.chip_sw_csrng_kat_test.2384761111			Feb 18 03:55:05 PM PST 24	Feb 18 03:59:04 PM PST 24	2621792070 ps
T60	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3738037318			Feb 18 04:16:55 PM PST 24	Feb 18 04:23:45 PM PST 24	6056566307 ps
T240	/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3059333898			Feb 18 04:10:32 PM PST 24	Feb 18 04:17:04 PM PST 24	3631714004 ps
T903	/workspace/coverage/default/2.chip_sw_example_concurrency.1790683148			Feb 18 04:08:36 PM PST 24	Feb 18 04:14:48 PM PST 24	3457887256 ps
T376	/workspace/coverage/default/0.chip_sw_uart_smoketest_signed.3854929023			Feb 18 04:02:31 PM PST 24	Feb 18 04:38:29 PM PST 24	9259328400 ps
T182	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1063149610			Feb 18 04:17:50 PM PST 24	Feb 18 04:35:24 PM PST 24	5198157470 ps
T704	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.810160310			Feb 18 04:03:33 PM PST 24	Feb 18 04:08:53 PM PST 24	2666971854 ps
T680	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.768287525			Feb 18 04:21:41 PM PST 24	Feb 18 04:29:44 PM PST 24	4071824460 ps
T377	/workspace/coverage/default/1.rom_e2e_asm_init_prod.1758429776			Feb 18 04:11:21 PM PST 24	Feb 18 04:39:47 PM PST 24	8629115118 ps
T241	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.175556684			Feb 18 04:14:18 PM PST 24	Feb 18 04:16:20 PM PST 24	1978871640 ps
T211	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3103592598			Feb 18 04:09:27 PM PST 24	Feb 18 04:36:26 PM PST 24	8883418826 ps
T41	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1534151362			Feb 18 04:01:55 PM PST 24	Feb 18 04:39:46 PM PST 24	8577640536 ps
T149	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3594600803			Feb 18 03:56:37 PM PST 24	Feb 18 04:08:58 PM PST 24	4692049800 ps
T200	/workspace/coverage/default/93.chip_sw_all_escalation_resets.2336984968			Feb 18 04:23:58 PM PST 24	Feb 18 04:35:00 PM PST 24	4564506352 ps
T184	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3130929113			Feb 18 03:53:13 PM PST 24	Feb 18 04:08:17 PM PST 24	5166098306 ps
T201	/workspace/coverage/default/35.chip_sw_all_escalation_resets.1227516417			Feb 18 04:20:10 PM PST 24	Feb 18 04:28:33 PM PST 24	4570877048 ps
T282	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.3645757711			Feb 18 03:53:59 PM PST 24	Feb 18 03:59:53 PM PST 24	3283331030 ps
T61	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3400976911			Feb 18 04:09:22 PM PST 24	Feb 18 05:42:21 PM PST 24	51858277753 ps
T118	/workspace/coverage/default/49.chip_sw_all_escalation_resets.1840503151			Feb 18 04:21:44 PM PST 24	Feb 18 04:30:54 PM PST 24	5584218612 ps
T108	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2883575595			Feb 18 03:54:04 PM PST 24	Feb 18 04:57:25 PM PST 24	18610222560 ps
T123	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1799833692			Feb 18 04:09:51 PM PST 24	Feb 18 04:11:56 PM PST 24	2233590297 ps
T283	/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2164719911			Feb 18 03:57:01 PM PST 24	Feb 18 04:00:38 PM PST 24	2334335800 ps
T121	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3639829789			Feb 18 04:00:49 PM PST 24	Feb 18 04:10:26 PM PST 24	7190936016 ps
T70	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2888159840			Feb 18 04:05:08 PM PST 24	Feb 18 04:14:27 PM PST 24	5607243966 ps
T904	/workspace/coverage/default/1.chip_sw_uart_smoketest.1909036896			Feb 18 04:08:52 PM PST 24	Feb 18 04:13:54 PM PST 24	3013570748 ps
T150	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2200078083			Feb 18 04:16:53 PM PST 24	Feb 18 05:17:20 PM PST 24	22866047133 ps
T42	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2619064400			Feb 18 04:00:31 PM PST 24	Feb 18 04:47:10 PM PST 24	11228786477 ps
T315	/workspace/coverage/default/77.chip_sw_all_escalation_resets.2962719970			Feb 18 04:23:19 PM PST 24	Feb 18 04:33:26 PM PST 24	4820504744 ps
T905	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2496793730			Feb 18 03:53:54 PM PST 24	Feb 18 03:58:59 PM PST 24	2962962776 ps
T180	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2600683582			Feb 18 03:53:35 PM PST 24	Feb 18 04:03:05 PM PST 24	4001703144 ps
T17	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1523701578			Feb 18 04:06:54 PM PST 24	Feb 18 04:37:21 PM PST 24	20933981744 ps
T300	/workspace/coverage/default/1.chip_plic_all_irqs_0.1615420723			Feb 18 04:07:08 PM PST 24	Feb 18 04:27:50 PM PST 24	5785256670 ps
T382	/workspace/coverage/default/20.chip_sw_all_escalation_resets.38493097			Feb 18 04:18:38 PM PST 24	Feb 18 04:27:17 PM PST 24	4976933896 ps
T71	/workspace/coverage/default/4.chip_tap_straps_rma.2254221907			Feb 18 04:17:02 PM PST 24	Feb 18 04:22:03 PM PST 24	3513378825 ps
T383	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1328422573			Feb 18 04:17:44 PM PST 24	Feb 18 04:25:07 PM PST 24	3756992884 ps
T384	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2850288679			Feb 18 04:17:20 PM PST 24	Feb 18 04:22:39 PM PST 24	3372313224 ps
T195	/workspace/coverage/default/33.chip_sw_all_escalation_resets.2893533337			Feb 18 04:19:30 PM PST 24	Feb 18 04:31:34 PM PST 24	6556490912 ps
T230	/workspace/coverage/default/32.chip_sw_all_escalation_resets.322672310			Feb 18 04:19:57 PM PST 24	Feb 18 04:29:29 PM PST 24	4271140460 ps
T248	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2802335671			Feb 18 04:09:48 PM PST 24	Feb 18 04:19:29 PM PST 24	4479212984 ps
T129	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3500954534			Feb 18 04:11:42 PM PST 24	Feb 18 04:54:22 PM PST 24	28365855899 ps
T249	/workspace/coverage/default/70.chip_sw_all_escalation_resets.3479549444			Feb 18 04:23:57 PM PST 24	Feb 18 04:31:32 PM PST 24	4993058728 ps
T14	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3241798972			Feb 18 04:09:34 PM PST 24	Feb 18 04:24:37 PM PST 24	5379396740 ps
T72	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.442327996			Feb 18 04:07:58 PM PST 24	Feb 18 07:00:20 PM PST 24	57538342032 ps
T250	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.754798724			Feb 18 03:53:22 PM PST 24	Feb 18 04:06:21 PM PST 24	5055734880 ps
T173	/workspace/coverage/default/0.chip_sw_power_idle_load.190117201			Feb 18 03:56:55 PM PST 24	Feb 18 04:10:41 PM PST 24	4502796928 ps
T251	/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3208452007			Feb 18 04:10:45 PM PST 24	Feb 18 04:43:35 PM PST 24	8357120658 ps
T204	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2788999954			Feb 18 04:19:14 PM PST 24	Feb 18 04:26:01 PM PST 24	3107499316 ps
T170	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3810109047			Feb 18 04:00:52 PM PST 24	Feb 18 04:20:17 PM PST 24	9428637204 ps
T368	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.296123242			Feb 18 03:53:44 PM PST 24	Feb 18 04:03:31 PM PST 24	4323915352 ps
T192	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3912168096			Feb 18 04:01:14 PM PST 24	Feb 18 04:27:16 PM PST 24	8147544840 ps
T15	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3877833395			Feb 18 03:59:45 PM PST 24	Feb 18 04:05:29 PM PST 24	3998262162 ps
T385	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3398591300			Feb 18 04:21:00 PM PST 24	Feb 18 04:27:42 PM PST 24	3704791992 ps
T386	/workspace/coverage/default/1.chip_sw_aes_entropy.3865393198			Feb 18 04:03:24 PM PST 24	Feb 18 04:07:06 PM PST 24	3353044442 ps
T181	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1588119041			Feb 18 03:59:42 PM PST 24	Feb 18 04:11:20 PM PST 24	4480500552 ps
T387	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2114357282			Feb 18 04:10:28 PM PST 24	Feb 18 04:31:09 PM PST 24	14797724072 ps
T388	/workspace/coverage/default/1.chip_sw_kmac_entropy.1920329835			Feb 18 03:58:17 PM PST 24	Feb 18 04:02:13 PM PST 24	2818522612 ps
T151	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1911035046			Feb 18 04:03:23 PM PST 24	Feb 18 04:13:06 PM PST 24	3879413998 ps
T389	/workspace/coverage/default/36.chip_sw_all_escalation_resets.1581897667			Feb 18 04:20:55 PM PST 24	Feb 18 04:32:12 PM PST 24	5108571264 ps
T202	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1036284890			Feb 18 03:54:12 PM PST 24	Feb 18 04:01:30 PM PST 24	4095595118 ps
T109	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2471304631			Feb 18 04:10:40 PM PST 24	Feb 18 05:18:33 PM PST 24	16767696056 ps
T906	/workspace/coverage/default/1.chip_sw_aes_idle.1368890402			Feb 18 04:02:05 PM PST 24	Feb 18 04:05:35 PM PST 24	2049093524 ps
T153	/workspace/coverage/default/1.chip_sw_edn_boot_mode.1755212851			Feb 18 04:00:49 PM PST 24	Feb 18 04:11:15 PM PST 24	2867494656 ps
T685	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3284535425			Feb 18 04:14:40 PM PST 24	Feb 18 04:22:22 PM PST 24	2958693752 ps
T205	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1112903824			Feb 18 04:12:53 PM PST 24	Feb 18 04:23:02 PM PST 24	4460806352 ps
T231	/workspace/coverage/default/53.chip_sw_all_escalation_resets.1096537536			Feb 18 04:21:40 PM PST 24	Feb 18 04:28:58 PM PST 24	5436433128 ps
T907	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2448202003			Feb 18 04:09:01 PM PST 24	Feb 18 04:13:27 PM PST 24	3198127398 ps
T80	/workspace/coverage/default/0.rom_raw_unlock.4000224892			Feb 18 03:58:40 PM PST 24	Feb 18 04:35:36 PM PST 24	14056146417 ps
T10	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.1520968385			Feb 18 03:52:27 PM PST 24	Feb 18 04:07:08 PM PST 24	7852298672 ps
T136	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.4093047460			Feb 18 04:13:23 PM PST 24	Feb 18 04:22:32 PM PST 24	3777988757 ps
T110	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1619495705			Feb 18 03:53:39 PM PST 24	Feb 18 04:55:35 PM PST 24	17392101038 ps
T130	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.562662301			Feb 18 03:54:47 PM PST 24	Feb 18 04:17:51 PM PST 24	12057518988 ps
T157	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3086018284			Feb 18 04:05:09 PM PST 24	Feb 18 04:15:20 PM PST 24	5933212168 ps
T46	/workspace/coverage/default/2.chip_jtag_csr_rw.3783749749			Feb 18 04:06:49 PM PST 24	Feb 18 04:28:55 PM PST 24	11769374240 ps
T274	/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3491782092			Feb 18 04:16:49 PM PST 24	Feb 18 04:22:48 PM PST 24	4785014366 ps
T233	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1476386798			Feb 18 04:19:44 PM PST 24	Feb 18 04:26:27 PM PST 24	3820493532 ps
T119	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2120442368			Feb 18 04:22:24 PM PST 24	Feb 18 04:30:08 PM PST 24	3608192704 ps
T275	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.146727922			Feb 18 04:10:42 PM PST 24	Feb 18 04:19:36 PM PST 24	4827698377 ps
T276	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2924492428			Feb 18 03:56:12 PM PST 24	Feb 18 04:11:30 PM PST 24	6417605061 ps
T301	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2835236940			Feb 18 04:18:10 PM PST 24	Feb 18 04:56:33 PM PST 24	14201278104 ps
T362	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2240925043			Feb 18 04:11:52 PM PST 24	Feb 18 04:41:00 PM PST 24	6994376840 ps
T335	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2927679179			Feb 18 04:06:27 PM PST 24	Feb 18 04:11:45 PM PST 24	3136198778 ps
T390	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.2914609572			Feb 18 04:03:40 PM PST 24	Feb 18 04:14:05 PM PST 24	6535194104 ps
T164	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3929973175			Feb 18 04:00:51 PM PST 24	Feb 18 04:08:42 PM PST 24	7809278672 ps
T7	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3186764552			Feb 18 03:59:31 PM PST 24	Feb 18 04:05:01 PM PST 24	2978587588 ps
T185	/workspace/coverage/default/1.chip_sw_pattgen_ios.599188874			Feb 18 03:58:45 PM PST 24	Feb 18 04:04:00 PM PST 24	3138177250 ps
T131	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.819060626			Feb 18 04:18:32 PM PST 24	Feb 18 04:30:21 PM PST 24	12621631521 ps
T325	/workspace/coverage/default/40.chip_sw_all_escalation_resets.3759538171			Feb 18 04:22:06 PM PST 24	Feb 18 04:31:48 PM PST 24	5005946250 ps
T158	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2319189893			Feb 18 04:02:42 PM PST 24	Feb 18 04:15:12 PM PST 24	8592584912 ps
T135	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1939340014			Feb 18 03:53:39 PM PST 24	Feb 18 04:33:46 PM PST 24	27614184926 ps
T341	/workspace/coverage/default/38.chip_sw_all_escalation_resets.1337726454			Feb 18 04:20:58 PM PST 24	Feb 18 04:30:04 PM PST 24	6124470456 ps
T26	/workspace/coverage/default/2.chip_sw_gpio_smoketest.3721047547			Feb 18 04:16:41 PM PST 24	Feb 18 04:21:44 PM PST 24	2771241785 ps
T252	/workspace/coverage/default/1.rom_volatile_raw_unlock.4082930257			Feb 18 04:08:42 PM PST 24	Feb 18 04:10:38 PM PST 24	2495005816 ps
T345	/workspace/coverage/default/0.chip_sw_uart_smoketest.2463850475			Feb 18 03:58:27 PM PST 24	Feb 18 04:02:52 PM PST 24	2873580678 ps
T186	/workspace/coverage/default/1.rom_e2e_shutdown_output.2526351040			Feb 18 04:12:02 PM PST 24	Feb 18 04:57:48 PM PST 24	25919360912 ps
T346	/workspace/coverage/default/0.chip_sw_example_manufacturer.2267774115			Feb 18 03:53:41 PM PST 24	Feb 18 03:58:02 PM PST 24	2734798960 ps
T313	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.385389919			Feb 18 04:08:37 PM PST 24	Feb 18 04:24:59 PM PST 24	4372569068 ps
T306	/workspace/coverage/default/1.chip_sw_uart_tx_rx.1335979601			Feb 18 04:00:12 PM PST 24	Feb 18 04:15:05 PM PST 24	5225726200 ps
T347	/workspace/coverage/default/0.rom_e2e_asm_init_dev.2711900293			Feb 18 04:03:01 PM PST 24	Feb 18 04:33:52 PM PST 24	8780142441 ps
T348	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3241160882			Feb 18 03:52:32 PM PST 24	Feb 18 04:09:02 PM PST 24	5663529815 ps
T203	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2820277971			Feb 18 04:03:21 PM PST 24	Feb 18 05:10:16 PM PST 24	18256383016 ps
T234	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.940726707			Feb 18 04:17:56 PM PST 24	Feb 18 04:24:27 PM PST 24	3467268472 ps
T908	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.2162658084			Feb 18 04:03:42 PM PST 24	Feb 18 04:07:13 PM PST 24	2985267656 ps
T909	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1642769507			Feb 18 04:09:54 PM PST 24	Feb 18 04:21:51 PM PST 24	3672423696 ps
T68	/workspace/coverage/default/3.chip_tap_straps_rma.4030040489			Feb 18 04:16:20 PM PST 24	Feb 18 04:21:57 PM PST 24	4074183970 ps
T910	/workspace/coverage/default/1.chip_sw_csrng_smoketest.936521130			Feb 18 04:07:25 PM PST 24	Feb 18 04:10:14 PM PST 24	2121056610 ps
T165	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1770194435			Feb 18 04:10:06 PM PST 24	Feb 18 04:16:18 PM PST 24	6128198692 ps
T911	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2381579406			Feb 18 03:53:10 PM PST 24	Feb 18 04:04:52 PM PST 24	4106301060 ps
T253	/workspace/coverage/default/2.rom_volatile_raw_unlock.3848236111			Feb 18 04:22:02 PM PST 24	Feb 18 04:23:53 PM PST 24	2426512275 ps
T912	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2388652897			Feb 18 04:00:22 PM PST 24	Feb 18 04:09:01 PM PST 24	5683712888 ps
T196	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3299954045			Feb 18 04:24:02 PM PST 24	Feb 18 04:30:15 PM PST 24	4154322224 ps
T727	/workspace/coverage/default/17.chip_sw_all_escalation_resets.1321471397			Feb 18 04:19:31 PM PST 24	Feb 18 04:29:25 PM PST 24	4606047728 ps
T913	/workspace/coverage/default/3.chip_tap_straps_prod.614198706			Feb 18 04:15:31 PM PST 24	Feb 18 04:18:07 PM PST 24	2634696381 ps
T914	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1448437784			Feb 18 04:10:26 PM PST 24	Feb 18 04:19:51 PM PST 24	3574136664 ps
T915	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3973354865			Feb 18 04:02:56 PM PST 24	Feb 18 04:22:44 PM PST 24	10813373763 ps
T363	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4122427850			Feb 18 04:02:39 PM PST 24	Feb 18 04:54:09 PM PST 24	12098230568 ps
T684	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.922723457			Feb 18 04:09:57 PM PST 24	Feb 18 04:22:55 PM PST 24	5096553400 ps
T206	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1888192945			Feb 18 04:12:38 PM PST 24	Feb 18 04:19:43 PM PST 24	5153027694 ps
T916	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1825620614			Feb 18 04:03:09 PM PST 24	Feb 18 04:11:44 PM PST 24	4822639560 ps
T408	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.4259780413			Feb 18 03:55:55 PM PST 24	Feb 18 04:00:38 PM PST 24	2657982890 ps
T758	/workspace/coverage/default/88.chip_sw_all_escalation_resets.903987681			Feb 18 04:23:44 PM PST 24	Feb 18 04:32:01 PM PST 24	5058727660 ps
T682	/workspace/coverage/default/14.chip_sw_all_escalation_resets.2394192328			Feb 18 04:18:39 PM PST 24	Feb 18 04:30:40 PM PST 24	5694748576 ps
T227	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2556172160			Feb 18 04:22:40 PM PST 24	Feb 18 04:27:29 PM PST 24	3559822976 ps
T190	/workspace/coverage/default/4.chip_sw_all_escalation_resets.2111852735			Feb 18 04:18:20 PM PST 24	Feb 18 04:28:52 PM PST 24	4481845792 ps
T917	/workspace/coverage/default/4.chip_tap_straps_prod.452193813			Feb 18 04:17:35 PM PST 24	Feb 18 04:28:35 PM PST 24	7910913593 ps
T83	/workspace/coverage/default/67.chip_sw_all_escalation_resets.3012728406			Feb 18 04:22:58 PM PST 24	Feb 18 04:30:55 PM PST 24	4372129320 ps
T90	/workspace/coverage/default/1.chip_sw_hmac_smoketest.491986815			Feb 18 04:08:13 PM PST 24	Feb 18 04:13:35 PM PST 24	2797027784 ps
T91	/workspace/coverage/default/60.chip_sw_all_escalation_resets.1422254567			Feb 18 04:21:19 PM PST 24	Feb 18 04:30:23 PM PST 24	5855572562 ps
T92	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2702123797			Feb 18 03:56:21 PM PST 24	Feb 18 04:01:37 PM PST 24	5551710512 ps
T93	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1132476350			Feb 18 04:17:31 PM PST 24	Feb 18 04:26:36 PM PST 24	6056221466 ps
T94	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2008725994			Feb 18 03:54:55 PM PST 24	Feb 18 03:59:49 PM PST 24	2625666398 ps
T95	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2242569571			Feb 18 04:18:09 PM PST 24	Feb 18 04:53:48 PM PST 24	12970298398 ps
T96	/workspace/coverage/default/0.chip_sw_aes_masking_off.2081832843			Feb 18 03:53:23 PM PST 24	Feb 18 03:59:55 PM PST 24	3150483013 ps
T97	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2677900296			Feb 18 04:13:16 PM PST 24	Feb 18 04:23:37 PM PST 24	4805408418 ps
T98	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.924110423			Feb 18 03:57:58 PM PST 24	Feb 18 04:08:16 PM PST 24	5333885026 ps
T117	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1747066917			Feb 18 04:01:05 PM PST 24	Feb 18 07:20:29 PM PST 24	255381316174 ps
T677	/workspace/coverage/default/72.chip_sw_all_escalation_resets.2158226142			Feb 18 04:23:00 PM PST 24	Feb 18 04:30:52 PM PST 24	5066703946 ps
T193	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1301368626			Feb 18 04:12:42 PM PST 24	Feb 18 04:33:48 PM PST 24	7569118696 ps
T369	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1758092355			Feb 18 04:09:29 PM PST 24	Feb 18 04:19:12 PM PST 24	3942468552 ps
T207	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2714319938			Feb 18 04:17:56 PM PST 24	Feb 18 04:24:54 PM PST 24	4055502416 ps
T53	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2375321324			Feb 18 04:05:05 PM PST 24	Feb 18 04:12:51 PM PST 24	6899439960 ps
T212	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.614998996			Feb 18 04:11:41 PM PST 24	Feb 18 04:18:33 PM PST 24	5276502770 ps
T918	/workspace/coverage/default/0.chip_sw_coremark.2161789417			Feb 18 03:57:25 PM PST 24	Feb 18 06:43:04 PM PST 24	50104068792 ps
T919	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1032228116			Feb 18 04:04:29 PM PST 24	Feb 18 04:31:46 PM PST 24	7331104786 ps
T238	/workspace/coverage/default/0.chip_sw_rv_timer_irq.3221356386			Feb 18 03:53:20 PM PST 24	Feb 18 03:56:52 PM PST 24	2188757694 ps
T757	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2087953230			Feb 18 04:20:09 PM PST 24	Feb 18 04:33:57 PM PST 24	7574269197 ps
T920	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1843808215			Feb 18 03:57:52 PM PST 24	Feb 18 04:03:27 PM PST 24	3569931592 ps
T921	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3263027289			Feb 18 04:18:28 PM PST 24	Feb 18 04:34:00 PM PST 24	5417893870 ps
T750	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1716283556			Feb 18 04:19:58 PM PST 24	Feb 18 04:26:26 PM PST 24	3742484816 ps
T683	/workspace/coverage/default/75.chip_sw_all_escalation_resets.1952061838			Feb 18 04:23:04 PM PST 24	Feb 18 04:32:45 PM PST 24	4729872818 ps
T20	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3415745918			Feb 18 04:00:39 PM PST 24	Feb 18 04:31:16 PM PST 24	20637862176 ps
T922	/workspace/coverage/default/2.chip_tap_straps_prod.532337734			Feb 18 04:13:58 PM PST 24	Feb 18 04:29:13 PM PST 24	10013090931 ps
T923	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2849792139			Feb 18 04:19:44 PM PST 24	Feb 18 04:30:22 PM PST 24	4653620018 ps
T336	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3003197512			Feb 18 03:54:52 PM PST 24	Feb 18 03:59:12 PM PST 24	2837935372 ps
T924	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.162195861			Feb 18 04:09:53 PM PST 24	Feb 18 04:23:48 PM PST 24	8977697110 ps
T254	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2036718401			Feb 18 04:06:50 PM PST 24	Feb 18 04:46:25 PM PST 24	11416634484 ps
T152	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1496879194			Feb 18 03:57:50 PM PST 24	Feb 18 04:09:21 PM PST 24	3924385500 ps
T925	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.4055929643			Feb 18 03:53:30 PM PST 24	Feb 18 04:12:16 PM PST 24	11272154136 ps
T154	/workspace/coverage/default/2.chip_sw_edn_kat.4184648726			Feb 18 04:12:26 PM PST 24	Feb 18 04:22:39 PM PST 24	3351200048 ps
T740	/workspace/coverage/default/91.chip_sw_all_escalation_resets.3982083514			Feb 18 04:24:50 PM PST 24	Feb 18 04:33:48 PM PST 24	4544262110 ps
T179	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1930941369			Feb 18 03:53:31 PM PST 24	Feb 18 04:04:20 PM PST 24	4291050935 ps
T926	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1531509184			Feb 18 04:12:34 PM PST 24	Feb 18 04:43:19 PM PST 24	8568344260 ps
T686	/workspace/coverage/default/45.chip_sw_all_escalation_resets.115525052			Feb 18 04:20:48 PM PST 24	Feb 18 04:30:54 PM PST 24	5673489872 ps
T307	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2208516450			Feb 18 04:18:48 PM PST 24	Feb 18 04:53:59 PM PST 24	13106367928 ps
T84	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1997957084			Feb 18 04:11:19 PM PST 24	Feb 18 04:35:28 PM PST 24	11956664292 ps
T681	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.488842254			Feb 18 04:21:57 PM PST 24	Feb 18 04:29:29 PM PST 24	3203685760 ps
T927	/workspace/coverage/default/0.chip_sw_example_concurrency.2456506533			Feb 18 03:51:45 PM PST 24	Feb 18 03:54:22 PM PST 24	2578495088 ps
T928	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3725919564			Feb 18 03:57:12 PM PST 24	Feb 18 04:02:00 PM PST 24	2923366145 ps
T39	/workspace/coverage/default/0.chip_sw_spi_device_tpm.1088226788			Feb 18 03:52:04 PM PST 24	Feb 18 03:56:50 PM PST 24	3089235166 ps
T802	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.482199554			Feb 18 04:21:10 PM PST 24	Feb 18 04:28:14 PM PST 24	3724197940 ps
T929	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2259932029			Feb 18 03:55:01 PM PST 24	Feb 18 03:59:17 PM PST 24	2670414384 ps
T930	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3029740792			Feb 18 04:13:03 PM PST 24	Feb 18 04:16:14 PM PST 24	2908727834 ps
T931	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.323642289			Feb 18 04:19:57 PM PST 24	Feb 18 04:23:14 PM PST 24	2655152073 ps
T137	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3869679662			Feb 18 04:19:24 PM PST 24	Feb 18 04:28:22 PM PST 24	7405820640 ps
T754	/workspace/coverage/default/78.chip_sw_all_escalation_resets.982950014			Feb 18 04:24:27 PM PST 24	Feb 18 04:33:53 PM PST 24	4789506518 ps
T932	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.626817207			Feb 18 03:57:50 PM PST 24	Feb 18 04:09:01 PM PST 24	4487324724 ps
T933	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2464711907			Feb 18 04:00:05 PM PST 24	Feb 18 04:15:52 PM PST 24	11254198941 ps
T934	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2671950140			Feb 18 04:03:38 PM PST 24	Feb 18 04:11:09 PM PST 24	4007899098 ps
T50	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2406642804			Feb 18 03:58:52 PM PST 24	Feb 18 04:06:31 PM PST 24	4670967540 ps
T935	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2017377194			Feb 18 04:19:29 PM PST 24	Feb 18 04:32:45 PM PST 24	4644943192 ps
T667	/workspace/coverage/default/1.chip_sw_aes_masking_off.1442034085			Feb 18 04:02:56 PM PST 24	Feb 18 04:07:29 PM PST 24	2756278352 ps
T936	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2721276298			Feb 18 03:53:15 PM PST 24	Feb 18 04:51:04 PM PST 24	38922182234 ps
T255	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3950407524			Feb 18 04:01:27 PM PST 24	Feb 18 04:29:11 PM PST 24	7175054121 ps
T937	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2047005783			Feb 18 04:16:04 PM PST 24	Feb 18 04:34:31 PM PST 24	5592391936 ps
T751	/workspace/coverage/default/80.chip_sw_all_escalation_resets.965376441			Feb 18 04:23:20 PM PST 24	Feb 18 04:33:27 PM PST 24	5832152338 ps
T323	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.382304522			Feb 18 04:11:15 PM PST 24	Feb 18 04:24:27 PM PST 24	4996072700 ps
T938	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2915733			Feb 18 03:54:21 PM PST 24	Feb 18 03:58:14 PM PST 24	3556657011 ps
T745	/workspace/coverage/default/68.chip_sw_all_escalation_resets.4053519324			Feb 18 04:22:15 PM PST 24	Feb 18 04:31:11 PM PST 24	4834275194 ps
T674	/workspace/coverage/default/0.rom_volatile_raw_unlock.906916102			Feb 18 03:58:04 PM PST 24	Feb 18 03:59:59 PM PST 24	2338281613 ps
T73	/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.4030789757			Feb 18 03:56:21 PM PST 24	Feb 18 04:01:34 PM PST 24	2386882225 ps
T939	/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2156247816			Feb 18 04:07:14 PM PST 24	Feb 18 04:15:40 PM PST 24	5317891128 ps
T679	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.71290280			Feb 18 04:20:49 PM PST 24	Feb 18 04:27:42 PM PST 24	3956876552 ps
T940	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2549204627			Feb 18 04:19:32 PM PST 24	Feb 18 04:41:47 PM PST 24	7022415401 ps
T678	/workspace/coverage/default/47.chip_sw_all_escalation_resets.812445495			Feb 18 04:21:24 PM PST 24	Feb 18 04:30:44 PM PST 24	4213282978 ps
T941	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3844109266			Feb 18 04:07:08 PM PST 24	Feb 18 04:21:39 PM PST 24	4937304292 ps
T277	/workspace/coverage/default/99.chip_sw_all_escalation_resets.3765285712			Feb 18 04:24:31 PM PST 24	Feb 18 04:34:51 PM PST 24	5063022534 ps
T942	/workspace/coverage/default/2.chip_sw_uart_smoketest.3132780924			Feb 18 04:15:39 PM PST 24	Feb 18 04:19:56 PM PST 24	2919670142 ps
T943	/workspace/coverage/default/1.rom_e2e_static_critical.2978071786			Feb 18 04:10:51 PM PST 24	Feb 18 04:48:52 PM PST 24	10982493488 ps
T308	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1357553778			Feb 18 03:52:56 PM PST 24	Feb 18 04:11:12 PM PST 24	5575468205 ps
T944	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.4259578250			Feb 18 04:00:12 PM PST 24	Feb 18 04:04:20 PM PST 24	2581820908 ps
T197	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1924662911			Feb 18 04:15:43 PM PST 24	Feb 18 04:38:13 PM PST 24	7044609976 ps
T21	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.276616791			Feb 18 03:54:57 PM PST 24	Feb 18 04:55:19 PM PST 24	20211532406 ps
T85	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.3733581667			Feb 18 03:55:02 PM PST 24	Feb 18 04:02:39 PM PST 24	3746363247 ps
T226	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2510222261			Feb 18 04:16:11 PM PST 24	Feb 18 04:36:47 PM PST 24	6025002736 ps
T945	/workspace/coverage/default/0.rom_e2e_smoke.1309810318			Feb 18 03:58:17 PM PST 24	Feb 18 04:31:30 PM PST 24	9058044600 ps
T27	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.4012999807			Feb 18 03:54:01 PM PST 24	Feb 18 04:00:29 PM PST 24	3120781940 ps
T946	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3757741428			Feb 18 04:16:11 PM PST 24	Feb 18 04:25:26 PM PST 24	4320895080 ps
T748	/workspace/coverage/default/11.chip_sw_all_escalation_resets.496139392			Feb 18 04:18:31 PM PST 24	Feb 18 04:30:45 PM PST 24	5892238522 ps
T366	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3864712943			Feb 18 03:58:18 PM PST 24	Feb 18 04:34:23 PM PST 24	8176353626 ps