| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| big_delay | 200 | 1 | T502 | 1 | T548 | 1 | T902 | 1 | ||||
| small_delay | 948 | 1 | T78 | 1 | T79 | 1 | T113 | 1 | ||||
| zero | 652 | 1 | T77 | 1 | T82 | 1 | T156 | 1 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |