Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	439	1			T474	1		T443	2		T499	1
all_values[1]	438	1			T443	1		T398	1		T505	1
all_values[2]	462	1			T443	4		T505	5		T880	3
all_values[3]	444	1			T391	1		T525	2		T505	2
all_values[4]	447	1			T391	1		T443	1		T499	1
all_values[5]	486	1			T474	1		T505	4		T417	1
all_values[6]	434	1			T474	1		T443	1		T505	2
all_values[7]	463	1			T474	1		T443	1		T505	3
all_values[8]	411	1			T499	1		T525	2		T878	1
all_values[9]	450	1			T474	3		T391	1		T443	4
all_values[10]	456	1			T499	1		T505	1		T422	1
all_values[11]	455	1			T391	1		T443	1		T398	2
all_values[12]	444	1			T443	1		T499	1		T505	2
all_values[13]	449	1			T391	1		T443	1		T505	4
all_values[14]	449	1			T443	2		T398	1		T525	2
all_values[15]	466	1			T443	1		T392	1		T880	1
all_values[16]	457	1			T474	1		T443	2		T499	1
all_values[17]	422	1			T474	1		T499	2		T525	1
all_values[18]	430	1			T443	2		T398	1		T525	1
all_values[19]	423	1			T474	1		T443	5		T499	1
all_values[20]	446	1			T525	1		T505	5		T689	1
all_values[21]	490	1			T474	1		T391	1		T443	1
all_values[22]	448	1			T391	1		T443	2		T525	1
all_values[23]	528	1			T443	1		T525	1		T505	2
all_values[24]	442	1			T474	1		T443	2		T398	1
all_values[25]	488	1			T443	2		T525	4		T878	1
all_values[26]	451	1			T525	1		T505	3		T880	2
all_values[27]	447	1			T113	2		T474	1		T391	2
all_values[28]	465	1			T474	1		T499	1		T505	4
all_values[29]	475	1			T443	3		T499	2		T398	1
all_values[30]	422	1			T525	3		T422	1		T395	1
all_values[31]	444	1			T474	1		T443	4		T499	1
all_values[32]	434	1			T443	1		T525	3		T392	1
all_values[33]	455	1			T391	1		T443	1		T525	2
all_values[34]	479	1			T443	1		T505	3		T422	1
all_values[35]	433	1			T474	1		T391	1		T525	1
all_values[36]	456	1			T443	1		T525	1		T392	1
all_values[37]	424	1			T474	1		T391	1		T443	1
all_values[38]	435	1			T474	1		T391	1		T443	2
all_values[39]	428	1			T391	2		T443	2		T499	1
all_values[40]	429	1			T113	1		T525	1		T505	3
all_values[41]	412	1			T474	1		T443	3		T525	1
all_values[42]	408	1			T391	1		T443	4		T505	2
all_values[43]	453	1			T391	1		T505	4		T395	1
all_values[44]	433	1			T474	1		T505	2		T399	1
all_values[45]	469	1			T391	1		T443	1		T499	1
all_values[46]	427	1			T391	1		T443	3		T505	2
all_values[47]	455	1			T443	2		T499	2		T398	1
all_values[48]	453	1			T443	1		T398	1		T525	1
all_values[49]	440	1			T443	2		T398	1		T525	2