Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3411	1			T443	8		T398	6		T525	9
all_values[1]	3278	1			T443	2		T398	8		T525	5
all_values[2]	3368	1			T443	4		T398	6		T525	11
all_values[3]	3400	1			T501	2		T443	4		T398	8
all_values[4]	3308	1			T443	5		T398	4		T525	12
all_values[5]	3405	1			T443	5		T398	5		T525	13
all_values[6]	3318	1			T443	4		T398	8		T525	10
all_values[7]	3273	1			T443	2		T398	7		T525	3
all_values[8]	3442	1			T501	1		T443	4		T398	7
all_values[9]	3413	1			T501	1		T443	4		T398	3
all_values[10]	3366	1			T501	1		T443	9		T398	4
all_values[11]	3325	1			T443	5		T398	5		T525	10
all_values[12]	3277	1			T501	1		T443	7		T398	4
all_values[13]	3343	1			T443	5		T398	11		T525	6
all_values[14]	3247	1			T443	4		T398	5		T525	12
all_values[15]	3367	1			T443	5		T398	7		T525	8
all_values[16]	3452	1			T443	4		T398	8		T525	9
all_values[17]	3451	1			T443	3		T398	7		T525	14
all_values[18]	3466	1			T443	3		T398	6		T525	9
all_values[19]	3350	1			T443	5		T398	4		T525	7
all_values[20]	3323	1			T443	5		T398	7		T525	6
all_values[21]	3299	1			T443	2		T398	5		T525	9
all_values[22]	3334	1			T443	8		T398	5		T525	9
all_values[23]	3316	1			T443	5		T398	6		T525	13
all_values[24]	3431	1			T443	6		T398	5		T525	11
all_values[25]	3351	1			T443	8		T398	4		T525	10
all_values[26]	3368	1			T443	4		T398	4		T525	5
all_values[27]	3272	1			T501	1		T443	5		T398	6
all_values[28]	3336	1			T443	8		T398	3		T525	6
all_values[29]	3323	1			T443	5		T398	8		T525	12
all_values[30]	3374	1			T443	4		T398	5		T525	6
all_values[31]	3435	1			T443	4		T398	9		T525	11
all_values[32]	3331	1			T443	3		T398	4		T525	14
all_values[33]	3378	1			T443	5		T398	4		T525	9
all_values[34]	3407	1			T501	1		T443	3		T398	9
all_values[35]	3398	1			T443	4		T525	10		T392	3
all_values[36]	3453	1			T501	2		T443	5		T398	10
all_values[37]	3412	1			T501	1		T443	6		T398	5
all_values[38]	3451	1			T443	3		T398	7		T525	10
all_values[39]	3246	1			T443	6		T398	3		T525	8
all_values[40]	3309	1			T501	1		T443	5		T398	3
all_values[41]	3419	1			T443	3		T398	14		T525	12
all_values[42]	3443	1			T443	6		T398	6		T525	6
all_values[43]	3329	1			T443	6		T398	7		T525	8
all_values[44]	3301	1			T443	7		T398	3		T525	7
all_values[45]	3417	1			T398	6		T525	7		T392	5
all_values[46]	3373	1			T443	4		T398	3		T525	4
all_values[47]	3367	1			T443	4		T398	6		T525	7
all_values[48]	3431	1			T443	4		T398	3		T525	5
all_values[49]	3393	1			T443	3		T398	2		T525	13
all_values[50]	3488	1			T443	7		T398	10		T525	9
all_values[51]	3550	1			T501	1		T443	2		T398	6
all_values[52]	3332	1			T443	2		T398	4		T525	4
all_values[53]	3400	1			T501	1		T443	3		T398	8
all_values[54]	3331	1			T443	2		T398	6		T525	6
all_values[55]	3392	1			T443	3		T398	6		T525	9
all_values[56]	3351	1			T501	1		T443	6		T398	3
all_values[57]	3363	1			T443	5		T398	11		T525	11
all_values[58]	3428	1			T443	4		T398	6		T525	13
all_values[59]	3410	1			T501	2		T443	6		T398	4
all_values[60]	3437	1			T443	4		T398	8		T525	16
all_values[61]	3406	1			T443	2		T398	7		T525	6
all_values[62]	3351	1			T443	4		T398	6		T525	10
all_values[63]	3401	1			T443	3		T398	1		T525	10