Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 909268 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 1535542 1 T1 39 T2 39 T3 39


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 1849111 1 T38 36 T14 2328 T39 10
values[0x0] 282072 1 T1 18 T2 14 T3 20
values[0x1] 313627 1 T1 21 T2 25 T3 19


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 685206 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1759604 1 T1 39 T2 39 T3 39


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 38497 1 T38 14 T14 75 T39 9
valid_sources[0x01] 39206 1 T4 2 T6 1 T38 12
valid_sources[0x02] 38172 1 T1 1 T2 2 T3 2
valid_sources[0x03] 38054 1 T3 6 T5 2 T38 15
valid_sources[0x04] 37863 1 T1 1 T2 2 T5 1
valid_sources[0x05] 38216 1 T1 1 T5 1 T6 1
valid_sources[0x06] 38141 1 T2 1 T3 7 T4 2
valid_sources[0x07] 37813 1 T2 1 T4 1 T6 1
valid_sources[0x08] 37939 1 T1 1 T4 5 T5 1
valid_sources[0x09] 38058 1 T5 1 T6 1 T38 16
valid_sources[0x0a] 37962 1 T1 2 T2 1 T4 1
valid_sources[0x0b] 38200 1 T6 1 T38 13 T14 82
valid_sources[0x0c] 37886 1 T38 16 T14 77 T39 16
valid_sources[0x0d] 37583 1 T2 2 T3 4 T4 1
valid_sources[0x0e] 38237 1 T1 3 T2 1 T5 2
valid_sources[0x0f] 37642 1 T5 1 T6 2 T38 25
valid_sources[0x10] 37950 1 T2 1 T4 1 T6 1
valid_sources[0x11] 38399 1 T1 2 T4 1 T6 1
valid_sources[0x12] 38403 1 T1 2 T2 2 T5 1
valid_sources[0x13] 36933 1 T1 3 T2 2 T3 1
valid_sources[0x14] 38707 1 T5 1 T38 17 T14 83
valid_sources[0x15] 41237 1 T5 1 T38 21 T14 70
valid_sources[0x16] 38341 1 T2 1 T38 18 T14 78
valid_sources[0x17] 37830 1 T2 1 T3 6 T4 2
valid_sources[0x18] 37488 1 T1 2 T5 2 T6 3
valid_sources[0x19] 38076 1 T4 2 T6 1 T38 9
valid_sources[0x1a] 37714 1 T2 1 T4 1 T38 11
valid_sources[0x1b] 37663 1 T5 1 T38 15 T14 64
valid_sources[0x1c] 38200 1 T4 1 T38 18 T14 76
valid_sources[0x1d] 38307 1 T2 1 T3 3 T4 1
valid_sources[0x1e] 37670 1 T4 2 T6 2 T38 22
valid_sources[0x1f] 38014 1 T6 1 T38 12 T14 66
valid_sources[0x20] 38062 1 T1 2 T2 2 T4 1


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 1074664 1 T38 32 T14 1168 T39 10
values[0x0] all_enables biggest_size 238178 1 T1 18 T2 14 T3 20
values[0x1] all_enables biggest_size 222700 1 T1 21 T2 25 T3 19


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2985656 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 472729 1 T11 163 T12 102 T13 415


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 1170728 1 T11 341 T12 417 T13 1012
values[0x0] 1118328 1 T11 349 T12 72 T13 976
values[0x1] 1169329 1 T11 350 T12 446 T13 1025


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2312277 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1146108 1 T11 352 T12 362 T13 1007


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 53649 1 T11 15 T12 12 T13 53
valid_sources[0x01] 54098 1 T11 20 T12 14 T13 40
valid_sources[0x02] 53792 1 T11 18 T12 21 T13 30
valid_sources[0x03] 54026 1 T11 17 T12 17 T13 48
valid_sources[0x04] 54272 1 T11 16 T12 20 T13 35
valid_sources[0x05] 54106 1 T11 16 T12 17 T13 70
valid_sources[0x06] 54327 1 T11 16 T12 18 T13 42
valid_sources[0x07] 54321 1 T11 15 T12 13 T13 48
valid_sources[0x08] 54122 1 T11 15 T12 21 T13 49
valid_sources[0x09] 54640 1 T11 12 T12 23 T13 35
valid_sources[0x0a] 53715 1 T11 18 T12 11 T13 59
valid_sources[0x0b] 54972 1 T11 22 T12 17 T13 41
valid_sources[0x0c] 53842 1 T11 7 T12 18 T13 56
valid_sources[0x0d] 55346 1 T11 28 T12 10 T13 59
valid_sources[0x0e] 53314 1 T11 11 T12 19 T13 36
valid_sources[0x0f] 53727 1 T11 15 T12 19 T13 47
valid_sources[0x10] 54597 1 T11 19 T12 26 T13 59
valid_sources[0x11] 53346 1 T11 11 T12 18 T13 45
valid_sources[0x12] 54246 1 T11 26 T12 7 T13 56
valid_sources[0x13] 54631 1 T11 14 T12 13 T13 52
valid_sources[0x14] 55056 1 T11 17 T12 12 T13 31
valid_sources[0x15] 53579 1 T11 4 T12 15 T13 38
valid_sources[0x16] 53554 1 T11 14 T12 13 T13 52
valid_sources[0x17] 54551 1 T11 24 T12 7 T13 35
valid_sources[0x18] 53056 1 T11 15 T12 14 T13 33
valid_sources[0x19] 54452 1 T11 16 T12 13 T13 61
valid_sources[0x1a] 54423 1 T11 30 T12 19 T13 55
valid_sources[0x1b] 54261 1 T11 19 T12 6 T13 64
valid_sources[0x1c] 54039 1 T11 15 T12 18 T13 52
valid_sources[0x1d] 54304 1 T11 13 T12 9 T13 48
valid_sources[0x1e] 53839 1 T11 17 T12 19 T13 79
valid_sources[0x1f] 53940 1 T11 14 T12 16 T13 38
valid_sources[0x20] 54781 1 T11 21 T12 15 T13 63


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 49461 1 T11 18 T12 40 T13 37
values[0x0] all_enables biggest_size 373685 1 T11 134 T12 29 T13 345
values[0x1] all_enables biggest_size 49583 1 T11 11 T12 33 T13 33


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3186874 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 518790 1 T11 143 T12 115 T13 418


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 1268148 1 T11 336 T12 499 T13 1035
values[0x0] 1170321 1 T11 345 T12 85 T13 976
values[0x1] 1267195 1 T11 321 T12 466 T13 1092


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2447525 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1258139 1 T11 350 T12 410 T13 1010


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 58701 1 T11 5 T12 26 T13 51
valid_sources[0x01] 57847 1 T11 8 T12 18 T13 43
valid_sources[0x02] 58576 1 T11 16 T12 21 T13 71
valid_sources[0x03] 56849 1 T11 11 T12 16 T13 34
valid_sources[0x04] 57615 1 T11 5 T12 17 T13 35
valid_sources[0x05] 57728 1 T11 25 T12 14 T13 13
valid_sources[0x06] 58203 1 T11 17 T12 14 T13 35
valid_sources[0x07] 58040 1 T11 6 T12 13 T13 95
valid_sources[0x08] 58617 1 T11 18 T12 20 T13 72
valid_sources[0x09] 57838 1 T11 7 T12 13 T13 42
valid_sources[0x0a] 56912 1 T11 25 T12 12 T13 40
valid_sources[0x0b] 58814 1 T11 7 T12 6 T13 68
valid_sources[0x0c] 56949 1 T11 11 T12 19 T13 34
valid_sources[0x0d] 57982 1 T11 5 T12 16 T13 22
valid_sources[0x0e] 58176 1 T11 23 T12 15 T13 20
valid_sources[0x0f] 57829 1 T11 14 T12 24 T13 121
valid_sources[0x10] 59137 1 T11 15 T12 18 T13 44
valid_sources[0x11] 56088 1 T11 28 T12 16 T13 31
valid_sources[0x12] 57728 1 T11 12 T12 17 T13 57
valid_sources[0x13] 58364 1 T11 8 T12 14 T13 51
valid_sources[0x14] 57804 1 T11 15 T12 23 T13 25
valid_sources[0x15] 57506 1 T11 19 T12 27 T13 77
valid_sources[0x16] 57824 1 T11 13 T12 16 T13 98
valid_sources[0x17] 58201 1 T11 15 T12 12 T13 66
valid_sources[0x18] 58669 1 T11 11 T12 17 T13 36
valid_sources[0x19] 58492 1 T11 19 T12 9 T13 27
valid_sources[0x1a] 58019 1 T11 11 T12 15 T13 43
valid_sources[0x1b] 57509 1 T11 12 T12 20 T13 26
valid_sources[0x1c] 57626 1 T11 13 T12 17 T13 35
valid_sources[0x1d] 57928 1 T11 9 T12 11 T13 22
valid_sources[0x1e] 58041 1 T11 13 T12 16 T13 45
valid_sources[0x1f] 58285 1 T11 14 T12 17 T13 74
valid_sources[0x20] 57857 1 T11 18 T12 14 T13 44


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 54251 1 T11 10 T12 45 T13 39
values[0x0] all_enables biggest_size 410126 1 T11 123 T12 34 T13 321
values[0x1] all_enables biggest_size 54413 1 T11 10 T12 36 T13 58


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3013074 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 476597 1 T11 126 T12 110 T13 361


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 1182227 1 T11 315 T12 439 T13 943
values[0x0] 1126435 1 T11 280 T12 107 T13 923
values[0x1] 1181009 1 T11 334 T12 468 T13 950


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2332028 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1157643 1 T11 302 T12 374 T13 913


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 54701 1 T11 14 T12 15 T13 38
valid_sources[0x01] 53720 1 T11 15 T12 14 T13 65
valid_sources[0x02] 54223 1 T11 9 T12 25 T13 41
valid_sources[0x03] 55360 1 T11 13 T12 13 T13 39
valid_sources[0x04] 54027 1 T11 13 T12 15 T13 55
valid_sources[0x05] 54081 1 T11 13 T12 19 T13 47
valid_sources[0x06] 54885 1 T11 17 T12 12 T13 47
valid_sources[0x07] 54104 1 T11 16 T12 8 T13 35
valid_sources[0x08] 54837 1 T11 13 T12 14 T13 47
valid_sources[0x09] 55439 1 T11 22 T12 17 T13 31
valid_sources[0x0a] 53519 1 T11 20 T12 11 T13 36
valid_sources[0x0b] 56042 1 T11 9 T12 22 T13 42
valid_sources[0x0c] 53980 1 T11 22 T12 25 T13 39
valid_sources[0x0d] 55072 1 T11 12 T12 18 T13 53
valid_sources[0x0e] 54549 1 T11 17 T12 27 T13 54
valid_sources[0x0f] 54335 1 T11 17 T12 23 T13 32
valid_sources[0x10] 56075 1 T11 12 T12 7 T13 48
valid_sources[0x11] 54307 1 T11 17 T12 19 T13 44
valid_sources[0x12] 55149 1 T11 12 T12 21 T13 38
valid_sources[0x13] 55340 1 T11 13 T12 6 T13 49
valid_sources[0x14] 55110 1 T11 21 T12 23 T13 23
valid_sources[0x15] 54227 1 T11 14 T12 18 T13 36
valid_sources[0x16] 55063 1 T11 13 T12 13 T13 40
valid_sources[0x17] 54739 1 T11 16 T12 17 T13 47
valid_sources[0x18] 53563 1 T11 11 T12 20 T13 45
valid_sources[0x19] 54001 1 T11 11 T12 16 T13 41
valid_sources[0x1a] 54149 1 T11 7 T12 15 T13 46
valid_sources[0x1b] 54023 1 T11 14 T12 13 T13 48
valid_sources[0x1c] 54768 1 T11 13 T12 11 T13 60
valid_sources[0x1d] 54750 1 T11 20 T12 13 T13 53
valid_sources[0x1e] 54838 1 T11 19 T12 17 T13 43
valid_sources[0x1f] 54414 1 T11 12 T12 19 T13 52
valid_sources[0x20] 54898 1 T11 14 T12 14 T13 45


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 49650 1 T11 13 T12 34 T13 28
values[0x0] all_enables biggest_size 377415 1 T11 97 T12 48 T13 300
values[0x1] all_enables biggest_size 49532 1 T11 16 T12 28 T13 33

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%