Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : spi_device
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.38 82.38

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_spi_device 92.02 92.02


Module Instance : tb.dut.top_earlgrey.u_spi_device

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.02 92.02


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.02 92.02


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
86.44 74.46 84.85 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : spi_device
TotalCoveredPercent
Totals 59 43 72.88
Total Bits 420 346 82.38
Total Bits 0->1 210 173 82.38
Total Bits 1->0 210 173 82.38

Ports 59 43 72.88
Port Bits 420 346 82.38
Port Bits 0->1 210 173 82.38
Port Bits 1->0 210 173 82.38

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T3,T11,T12 Yes T3,T11,T12 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T3,T11,T12 Yes T3,T11,T12 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[12:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
tl_i.a_address[15:13] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T3,*T4,*T5 Yes T3,T4,T5 INPUT
tl_i.a_address[17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18] Yes Yes *T3,*T4,*T5 Yes T3,T4,T5 INPUT
tl_i.a_address[29:19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T3,T11,T12 Yes T3,T11,T12 INPUT
tl_o.a_ready Yes Yes T3,T11,T12 Yes T3,T11,T12 OUTPUT
tl_o.d_error Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T3,T11,T12 Yes T3,T11,T12 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T3,T11,T12 Yes T3,T11,T12 OUTPUT
tl_o.d_data[31:0] Yes Yes T3,T11,T12 Yes T3,T11,T12 OUTPUT
tl_o.d_sink Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
tl_o.d_source[5:0] Yes Yes *T3,T11,T12 Yes T3,T11,T12 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T3,*T11,*T12 Yes T3,T11,T12 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T3,T11,T12 Yes T3,T11,T12 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T15,T16,T17 Yes T15,T16,T17 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T15,T16,T17 Yes T15,T16,T17 OUTPUT
cio_sck_i Yes Yes T7,T8,T9 Yes T7,T8,T9 INPUT
cio_csb_i Yes Yes T7,T8,T9 Yes T7,T8,T9 INPUT
cio_sd_o[3:0] No No No OUTPUT
cio_sd_en_o[3:0] No No No OUTPUT
cio_sd_i[3:0] Yes Yes T7,T8,T9 Yes T7,T8,T9 INPUT
cio_tpm_csb_i Yes Yes T50,T7,T8 Yes T50,T7,T8 INPUT
passthrough_o.s_en[3:0] No No No OUTPUT
passthrough_o.s[3:0] Yes Yes T7,T8,T9 Yes T7,T8,T9 OUTPUT
passthrough_o.csb_en No No No OUTPUT
passthrough_o.csb Yes Yes T7,T8,T9 Yes T7,T8,T9 OUTPUT
passthrough_o.sck_en No No No OUTPUT
passthrough_o.sck Yes Yes T7,T8,T9 Yes T7,T8,T9 OUTPUT
passthrough_o.passthrough_en Yes Yes T21 Yes T21 OUTPUT
passthrough_i.s[3:0] Yes Yes T7,T8,T9 Yes T7,T8,T9 INPUT
intr_upload_cmdfifo_not_empty_o Yes Yes T19,T21,T20 Yes T19,T21,T20 OUTPUT
intr_upload_payload_not_empty_o Yes Yes T21,T22 Yes T21,T22 OUTPUT
intr_upload_payload_overflow_o Yes Yes T14 Yes T14 OUTPUT
intr_readbuf_watermark_o No No No OUTPUT
intr_readbuf_flip_o Yes Yes T14,T19,T22 Yes T14,T19,T22 OUTPUT
intr_tpm_header_not_empty_o Yes Yes T19 Yes T19 OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0] No No No INPUT
ram_cfg_i.b_ram_lcfg.cfg_en No No No INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0] No No No INPUT
ram_cfg_i.a_ram_lcfg.cfg_en No No No INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0] No No No INPUT
ram_cfg_i.b_ram_fcfg.cfg_en No No No INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0] No No No INPUT
ram_cfg_i.a_ram_fcfg.cfg_en No No No INPUT
sck_monitor_o Yes Yes T7,T8,T9 Yes T7,T8,T9 OUTPUT
mbist_en_i Unreachable Unreachable Unreachable INPUT
scan_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_device
TotalCoveredPercent
Totals 49 43 87.76
Total Bits 376 346 92.02
Total Bits 0->1 188 173 92.02
Total Bits 1->0 188 173 92.02

Ports 49 43 87.76
Port Bits 376 346 92.02
Port Bits 0->1 188 173 92.02
Port Bits 1->0 188 173 92.02

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T3,T11,T12 Yes T3,T11,T12 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T3,T11,T12 Yes T3,T11,T12 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[12:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
tl_i.a_address[15:13] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T3,*T4,*T5 Yes T3,T4,T5 INPUT
tl_i.a_address[17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18] Yes Yes *T3,*T4,*T5 Yes T3,T4,T5 INPUT
tl_i.a_address[29:19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T3,T11,T12 Yes T3,T11,T12 INPUT
tl_o.a_ready Yes Yes T3,T11,T12 Yes T3,T11,T12 OUTPUT
tl_o.d_error Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T3,T11,T12 Yes T3,T11,T12 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T3,T11,T12 Yes T3,T11,T12 OUTPUT
tl_o.d_data[31:0] Yes Yes T3,T11,T12 Yes T3,T11,T12 OUTPUT
tl_o.d_sink Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
tl_o.d_source[5:0] Yes Yes *T3,T11,T12 Yes T3,T11,T12 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T3,*T11,*T12 Yes T3,T11,T12 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T3,T11,T12 Yes T3,T11,T12 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T15,T16,T17 Yes T15,T16,T17 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T15,T16,T17 Yes T15,T16,T17 OUTPUT
cio_sck_i Yes Yes T7,T8,T9 Yes T7,T8,T9 INPUT
cio_csb_i Yes Yes T7,T8,T9 Yes T7,T8,T9 INPUT
cio_sd_o[3:0] No No No OUTPUT
cio_sd_en_o[3:0] No No No OUTPUT
cio_sd_i[3:0] Yes Yes T7,T8,T9 Yes T7,T8,T9 INPUT
cio_tpm_csb_i Yes Yes T50,T7,T8 Yes T50,T7,T8 INPUT
passthrough_o.s_en[3:0] No No No OUTPUT
passthrough_o.s[3:0] Yes Yes T7,T8,T9 Yes T7,T8,T9 OUTPUT
passthrough_o.csb_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off.
passthrough_o.csb Yes Yes T7,T8,T9 Yes T7,T8,T9 OUTPUT
passthrough_o.sck_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off.
passthrough_o.sck Yes Yes T7,T8,T9 Yes T7,T8,T9 OUTPUT
passthrough_o.passthrough_en Yes Yes T21 Yes T21 OUTPUT
passthrough_i.s[3:0] Yes Yes T7,T8,T9 Yes T7,T8,T9 INPUT
intr_upload_cmdfifo_not_empty_o Yes Yes T19,T21,T20 Yes T19,T21,T20 OUTPUT
intr_upload_payload_not_empty_o Yes Yes T21,T22 Yes T21,T22 OUTPUT
intr_upload_payload_overflow_o Yes Yes T14 Yes T14 OUTPUT
intr_readbuf_watermark_o No No No OUTPUT
intr_readbuf_flip_o Yes Yes T14,T19,T22 Yes T14,T19,T22 OUTPUT
intr_tpm_header_not_empty_o Yes Yes T19 Yes T19 OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_lcfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_lcfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_lcfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_fcfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_fcfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_fcfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_fcfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
sck_monitor_o Yes Yes T7,T8,T9 Yes T7,T8,T9 OUTPUT
mbist_en_i Unreachable Unreachable Unreachable INPUT
scan_clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%