Unified Coverage Report :: Module :: gpio

Module : gpio

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26			99.26

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_gpio_0.1/rtl/gpio.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_gpio	99.26			99.26

---

Module Instance : tb.dut.top_earlgrey.u_gpio

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26			99.26

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26			99.26

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.44	74.46		84.85			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : gpio

	Total	Covered	Percent
Totals	33	31	93.94
Total Bits	540	536	99.26
Total Bits 0->1	270	268	99.26
Total Bits 1->0	270	268	99.26

Ports	33	31	93.94
Port Bits	540	536	99.26
Port Bits 0->1	270	268	99.26
Port Bits 1->0	270	268	99.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
tl_i.a_address[17:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	INPUT
tl_i.a_address[29:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
tl_o.d_error	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
tl_o.d_sink	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T4,*T5,T11	Yes	T4,T5,T11	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T11	Yes	T4,T5,T11	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
intr_gpio_o[31:0]	Yes	Yes	T14,T29,T18	Yes	T14,T29,T18	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T5,T14,T15	Yes	T5,T14,T15	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T5,T14,T15	Yes	T5,T14,T15	OUTPUT
cio_gpio_i[31:0]	Yes	Yes	T16,T32,T44	Yes	T16,T32,T44	INPUT
cio_gpio_o[31:0]	Yes	Yes	T4,T5,T14	Yes	T4,T5,T14	OUTPUT
cio_gpio_en_o[31:0]	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	OUTPUT

*Tests covering at least one bit in the range