Unified Coverage Report :: Module :: rv_core_ibex

Module : rv_core_ibex

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
41.06	28.24	14.29	61.58		58.33	42.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex	41.21	28.24	14.29	62.34		58.33	42.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
41.21	28.24	14.29	62.34		58.33	42.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.81	67.96	81.68	48.01		86.67	59.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.44	74.46		84.85			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
fifo_d	100.00	100.00	100.00			100.00	100.00
fifo_i	73.12	12.50	100.00			100.00	80.00
gen_alert_senders[0].u_alert_sender	33.33			33.33
gen_alert_senders[1].u_alert_sender	33.33			33.33
gen_alert_senders[2].u_alert_sender	33.33			33.33
gen_alert_senders[3].u_alert_sender	33.33			33.33
tl_adapter_host_d_ibex	62.24	81.40	40.91			60.00	66.67
tl_adapter_host_i_ibex	47.42	28.57	38.89			55.56	66.67
u_alert_nmi_sync	100.00	100.00				100.00
u_core	21.45			21.45
u_core_sleeping_buf	100.00	100.00
u_dbus_trans	11.80	1.15	22.22			16.67	7.14
u_edn_if	48.85	75.32	50.85			69.23	0.00
u_ibus_trans	9.94	1.15	14.81			16.67	7.14
u_intr_timer_sync	100.00	100.00				100.00
u_lc_sync	100.00	100.00				100.00	100.00
u_prim_buf_irq	100.00	100.00
u_prim_esc_receiver	28.57			28.57
u_prim_lc_sender	80.00	60.00				100.00
u_prim_sync_reqack_data	26.22	44.90	0.00			60.00	0.00
u_pwrmgr_sync	100.00	100.00				100.00	100.00
u_reg_cfg	96.62	95.90	96.37			98.74	95.45
u_sim_win_rsp	55.63	30.61	36.36			55.56	100.00
u_tlul_req_buf	100.00	100.00
u_tlul_rsp_buf	0.00	0.00
u_wdog_nmi_sync	100.00	100.00				100.00

Line Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	24	28.24
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	0	0.00
CONT_ASSIGN	218	1	0	0.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	268	1	0	0.00
CONT_ASSIGN	342	1	0	0.00
CONT_ASSIGN	348	1	0	0.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	488	3	3	100.00
CONT_ASSIGN	508	1	0	0.00
CONT_ASSIGN	509	1	0	0.00
CONT_ASSIGN	510	1	0	0.00
CONT_ASSIGN	511	1	0	0.00
ALWAYS	514	8	5	62.50
CONT_ASSIGN	698	1	0	0.00
CONT_ASSIGN	698	1	0	0.00
CONT_ASSIGN	699	1	0	0.00
CONT_ASSIGN	699	1	0	0.00
CONT_ASSIGN	700	1	0	0.00
CONT_ASSIGN	700	1	0	0.00
CONT_ASSIGN	704	1	0	0.00
CONT_ASSIGN	704	1	0	0.00
CONT_ASSIGN	705	1	0	0.00
CONT_ASSIGN	705	1	0	0.00
CONT_ASSIGN	706	1	0	0.00
CONT_ASSIGN	706	1	0	0.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	714	1	0	0.00
CONT_ASSIGN	715	1	0	0.00
CONT_ASSIGN	718	1	0	0.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	722	1	0	0.00
CONT_ASSIGN	724	1	0	0.00
CONT_ASSIGN	731	1	0	0.00
CONT_ASSIGN	733	1	0	0.00
CONT_ASSIGN	735	1	0	0.00
CONT_ASSIGN	737	1	0	0.00
CONT_ASSIGN	747	1	0	0.00
CONT_ASSIGN	748	1	0	0.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	0	0.00
CONT_ASSIGN	753	1	0	0.00
CONT_ASSIGN	756	1	0	0.00
ALWAYS	788	11	0	0.00
ALWAYS	804	7	7	100.00
CONT_ASSIGN	815	1	0	0.00
CONT_ASSIGN	834	1	0	0.00
CONT_ASSIGN	835	1	0	0.00
CONT_ASSIGN	836	1	0	0.00
CONT_ASSIGN	839	1	0	0.00
CONT_ASSIGN	843	0	0
CONT_ASSIGN	882	1	0	0.00
ALWAYS	941	0	0
CONT_ASSIGN	982	1	0	0.00
CONT_ASSIGN	984	1	0	0.00
CONT_ASSIGN	986	1	1	100.00
CONT_ASSIGN	988	1	0	0.00
CONT_ASSIGN	990	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	0	1
218	0	1
225	1	1
263	0	1
265	0	1
268	0	1
342	0	1
348	0	1
363	1	1
488	1	1
489	1	1
491	1	1
508	0	1
509	0	1
510	0	1
511	0	1
514	1	1
515	1	1
516	1	1
517	1	1
518	1	1
519	0	1
520	0	1
521	0	1
			MISSING_ELSE
698	0	2
699	0	2
700	0	2
704	0	2
705	0	2
706	0	2
713	1	1
714	0	1
715	0	1
718	0	1
720	1	1
722	0	1
724	0	1
731	0	1
733	0	1
735	0	1
737	0	1
747	0	1
748	0	1
749	1	1
750	0	1
753	0	1
756	0	1
788	0	1
789	0	1
790	0	1
792	0	1
793	0	1
794	0	1
795	0	1
796	0	1
797	0	1
798	0	1
799	0	1
			==> MISSING_ELSE
804	1	1
805	1	1
806	1	1
807	1	1
809	1	1
810	1	1
811	1	1
815	0	1
834	0	1
835	0	1
836	0	1
839	0	1
843		unreachable
882	0	1
941		unreachable
942		unreachable
943		unreachable
944		unreachable
			==> MISSING_ELSE
982	0	1
984	0	1
986	1	1
988	0	1
990	0	1

---

Cond Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Conditions	28	4	14.29
Logical	28	4	14.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       731
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       733
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       749
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       796
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Toggle Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Totals	121	100	82.64
Total Bits	1624	1000	61.58
Total Bits 0->1	812	500	61.58
Total Bits 1->0	812	500	61.58

Ports	121	100	82.64
Port Bits	1624	1000	61.58
Port Bits 0->1	812	500	61.58
Port Bits 1->0	812	500	61.58

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_cpu_n_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T11,T12,T30	Yes	T11,T12,T13	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T12,T13,T31	Yes	T12,T13,T31	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
corei_tl_h_i.d_error	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T6	Yes	T1,T2,T6	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_error	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
irq_software_i	Yes	Yes	T3,T16,T29	Yes	T3,T16,T29	INPUT
irq_timer_i	Yes	Yes	T21,T22	Yes	T21,T22	INPUT
irq_external_i	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
esc_tx_i.esc_n	Yes	Yes	T15,T18,T32	Yes	T15,T18,T32	INPUT
esc_tx_i.esc_p	Yes	Yes	T15,T18,T32	Yes	T15,T18,T32	INPUT
esc_rx_o.resp_n	Yes	Yes	T15,T18,T32	Yes	T15,T18,T32	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T15,T18,T32	Yes	T15,T18,T32	OUTPUT
nmi_wdog_i	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	INPUT
debug_req_i	No	No		No		INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T11,*T12,*T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T11,*T12,*T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T11,T12,T30	Yes	T11,T12,T13	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T11,*T12,*T13	Yes	T11,T12,T13	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	No	No		No		INPUT
edn_i.edn_fips	No	No		No		INPUT
edn_i.edn_ack	No	No		No		INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
icache_otp_key_o.req	No	No		No		OUTPUT
icache_otp_key_i.seed_valid	No	No		No		INPUT
icache_otp_key_i.nonce[127:0]	No	No		No		INPUT
icache_otp_key_i.key[127:0]	No	No		No		INPUT
icache_otp_key_i.ack	No	No		No		INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
alert_rx_i[1].ping_n	No	No		No		INPUT
alert_rx_i[1].ping_p	No	No		No		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T15,T16,T29	Yes	T15,T16,T29	INPUT
alert_rx_i[2].ping_n	No	No		No		INPUT
alert_rx_i[2].ping_p	No	No		No		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T16,T17,T29	Yes	T16,T17,T29	INPUT
alert_rx_i[3].ping_n	No	No		No		INPUT
alert_rx_i[3].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T15,T16,T29	Yes	T15,T16,T29	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T16,T17,T29	Yes	T16,T17,T29	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	7	58.33
TERNARY	348	2	1	50.00
IF	488	2	2	100.00
IF	514	3	2	66.67
IF	792	3	0	0.00
IF	804	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	488	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	514	if ((!rst_ni))
-2-:	518	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	792	if (reg2hw.rnd_data.re)
-2-:	796	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	804	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	9	42.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	9	42.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	8117675	0	0	0
FpvSecCmIbexFetchEnable1_A	8117675	261034	0	32
FpvSecCmIbexFetchEnable2_A	8117675	907182	0	32
FpvSecCmIbexFetchEnable3Rev_A	8117675	7208054	0	32
FpvSecCmIbexFetchEnable3_A	8117675	7208080	0	0
FpvSecCmIbexInstrIntgErrCheck_A	8117675	0	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	8117675	0	0	0
FpvSecCmIbexPcMismatchCheck_A	8117675	0	0	0
FpvSecCmIbexRfEccErrCheck_A	8117675	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	8117675	0	0	0
FpvSecCmRegWeOnehotCheck_A	8117675	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	8117675	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	8117675	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	8117675	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	16	16	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	16	16	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	16	16	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	16	16	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	16	16	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	8117675	0	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	8117675	0	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	261034	0	32
T1	107581	10074	0	2
T2	111097	10077	0	2
T3	966422	10124	0	2
T4	149102	10065	0	2
T5	809331	10178	0	2
T6	110408	10112	0	2
T7	174353	20106	0	2
T8	169724	20036	0	2
T9	141291	19998	0	2
T10	147699	20062	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	907182	0	32
T1	107581	34926	0	2
T2	111097	34933	0	2
T3	966422	34976	0	2
T4	149102	34913	0	2
T5	809331	35026	0	2
T6	110408	34964	0	2
T7	174353	69802	0	2
T8	169724	69748	0	2
T9	141291	69698	0	2
T10	147699	69762	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	7208054	0	32
T1	107581	104077	0	2
T2	111097	107593	0	2
T3	966422	931324	0	2
T4	149102	145598	0	2
T5	809331	774183	0	2
T6	110408	106901	0	2
T7	174353	104365	0	2
T8	169724	99804	0	2
T9	141291	71410	0	2
T10	147699	77765	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	7208080	0	0
T1	107581	104077	0	0
T2	111097	107594	0	0
T3	966422	931325	0	0
T4	149102	145598	0	0
T5	809331	774184	0	0
T6	110408	106901	0	0
T7	174353	104367	0	0
T8	169724	99806	0	0
T9	141291	71412	0	0
T10	147699	77767	0	0

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	24	28.24
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	0	0.00
CONT_ASSIGN	218	1	0	0.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	265	1	0	0.00
CONT_ASSIGN	268	1	0	0.00
CONT_ASSIGN	342	1	0	0.00
CONT_ASSIGN	348	1	0	0.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	488	3	3	100.00
CONT_ASSIGN	508	1	0	0.00
CONT_ASSIGN	509	1	0	0.00
CONT_ASSIGN	510	1	0	0.00
CONT_ASSIGN	511	1	0	0.00
ALWAYS	514	8	5	62.50
CONT_ASSIGN	698	1	0	0.00
CONT_ASSIGN	698	1	0	0.00
CONT_ASSIGN	699	1	0	0.00
CONT_ASSIGN	699	1	0	0.00
CONT_ASSIGN	700	1	0	0.00
CONT_ASSIGN	700	1	0	0.00
CONT_ASSIGN	704	1	0	0.00
CONT_ASSIGN	704	1	0	0.00
CONT_ASSIGN	705	1	0	0.00
CONT_ASSIGN	705	1	0	0.00
CONT_ASSIGN	706	1	0	0.00
CONT_ASSIGN	706	1	0	0.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	714	1	0	0.00
CONT_ASSIGN	715	1	0	0.00
CONT_ASSIGN	718	1	0	0.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	722	1	0	0.00
CONT_ASSIGN	724	1	0	0.00
CONT_ASSIGN	731	1	0	0.00
CONT_ASSIGN	733	1	0	0.00
CONT_ASSIGN	735	1	0	0.00
CONT_ASSIGN	737	1	0	0.00
CONT_ASSIGN	747	1	0	0.00
CONT_ASSIGN	748	1	0	0.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	0	0.00
CONT_ASSIGN	753	1	0	0.00
CONT_ASSIGN	756	1	0	0.00
ALWAYS	788	11	0	0.00
ALWAYS	804	7	7	100.00
CONT_ASSIGN	815	1	0	0.00
CONT_ASSIGN	834	1	0	0.00
CONT_ASSIGN	835	1	0	0.00
CONT_ASSIGN	836	1	0	0.00
CONT_ASSIGN	839	1	0	0.00
CONT_ASSIGN	843	0	0
CONT_ASSIGN	882	1	0	0.00
ALWAYS	941	0	0
CONT_ASSIGN	982	1	0	0.00
CONT_ASSIGN	984	1	0	0.00
CONT_ASSIGN	986	1	1	100.00
CONT_ASSIGN	988	1	0	0.00
CONT_ASSIGN	990	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	0	1
218	0	1
225	1	1
263	0	1
265	0	1
268	0	1
342	0	1
348	0	1
363	1	1
488	1	1
489	1	1
491	1	1
508	0	1
509	0	1
510	0	1
511	0	1
514	1	1
515	1	1
516	1	1
517	1	1
518	1	1
519	0	1
520	0	1
521	0	1
			MISSING_ELSE
698	0	2
699	0	2
700	0	2
704	0	2
705	0	2
706	0	2
713	1	1
714	0	1
715	0	1
718	0	1
720	1	1
722	0	1
724	0	1
731	0	1
733	0	1
735	0	1
737	0	1
747	0	1
748	0	1
749	1	1
750	0	1
753	0	1
756	0	1
788	0	1
789	0	1
790	0	1
792	0	1
793	0	1
794	0	1
795	0	1
796	0	1
797	0	1
798	0	1
799	0	1
			==> MISSING_ELSE
804	1	1
805	1	1
806	1	1
807	1	1
809	1	1
810	1	1
811	1	1
815	0	1
834	0	1
835	0	1
836	0	1
839	0	1
843		unreachable
882	0	1
941		unreachable
942		unreachable
943		unreachable
944		unreachable
			==> MISSING_ELSE
982	0	1
984	0	1
986	1	1
988	0	1
990	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Conditions	28	4	14.29
Logical	28	4	14.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       731
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       733
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       749
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       796
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Totals	117	100	85.47
Total Bits	1604	1000	62.34
Total Bits 0->1	802	500	62.34
Total Bits 1->0	802	500	62.34

Ports	117	100	85.47
Port Bits	1604	1000	62.34
Port Bits 0->1	802	500	62.34
Port Bits 1->0	802	500	62.34

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_cpu_n_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T11,T12,T30	Yes	T11,T12,T13	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T12,T13,T31	Yes	T12,T13,T31	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
corei_tl_h_i.d_error	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T6	Yes	T1,T2,T6	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_error	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
irq_software_i	Yes	Yes	T3,T16,T29	Yes	T3,T16,T29	INPUT
irq_timer_i	Yes	Yes	T21,T22	Yes	T21,T22	INPUT
irq_external_i	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
esc_tx_i.esc_n	Yes	Yes	T15,T18,T32	Yes	T15,T18,T32	INPUT
esc_tx_i.esc_p	Yes	Yes	T15,T18,T32	Yes	T15,T18,T32	INPUT
esc_rx_o.resp_n	Yes	Yes	T15,T18,T32	Yes	T15,T18,T32	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T15,T18,T32	Yes	T15,T18,T32	OUTPUT
nmi_wdog_i	Yes	Yes	T14,T16,T17	Yes	T14,T16,T17	INPUT
debug_req_i	No	No		No		INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T11,*T12,*T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T11,*T12,*T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T11,T12,T30	Yes	T11,T12,T13	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T11,*T12,*T13	Yes	T11,T12,T13	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	No	No		No		INPUT
edn_i.edn_fips	No	No		No		INPUT
edn_i.edn_ack	No	No		No		INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
icache_otp_key_o.req	No	No		No		OUTPUT
icache_otp_key_i.seed_valid	No	No		No		INPUT
icache_otp_key_i.nonce[127:0]	No	No		No		INPUT
icache_otp_key_i.key[127:0]	No	No		No		INPUT
icache_otp_key_i.ack	No	No		No		INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
alert_rx_i[1].ping_n	No	No		No		INPUT
alert_rx_i[1].ping_p	No	No		No		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T15,T16,T29	Yes	T15,T16,T29	INPUT
alert_rx_i[2].ping_n	No	No		No		INPUT
alert_rx_i[2].ping_p	No	No		No		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T16,T17,T29	Yes	T16,T17,T29	INPUT
alert_rx_i[3].ping_n	No	No		No		INPUT
alert_rx_i[3].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T15,T16,T29	Yes	T15,T16,T29	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T16,T17,T29	Yes	T16,T17,T29	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	7	58.33
TERNARY	348	2	1	50.00
IF	488	2	2	100.00
IF	514	3	2	66.67
IF	792	3	0	0.00
IF	804	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	488	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	514	if ((!rst_ni))
-2-:	518	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	792	if (reg2hw.rnd_data.re)
-2-:	796	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	804	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	9	42.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	9	42.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	8117675	0	0	0
FpvSecCmIbexFetchEnable1_A	8117675	261034	0	32
FpvSecCmIbexFetchEnable2_A	8117675	907182	0	32
FpvSecCmIbexFetchEnable3Rev_A	8117675	7208054	0	32
FpvSecCmIbexFetchEnable3_A	8117675	7208080	0	0
FpvSecCmIbexInstrIntgErrCheck_A	8117675	0	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	8117675	0	0	0
FpvSecCmIbexPcMismatchCheck_A	8117675	0	0	0
FpvSecCmIbexRfEccErrCheck_A	8117675	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	8117675	0	0	0
FpvSecCmRegWeOnehotCheck_A	8117675	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	8117675	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	8117675	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	8117675	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	16	16	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	16	16	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	16	16	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	16	16	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	16	16	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	8117675	0	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	8117675	0	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	261034	0	32
T1	107581	10074	0	2
T2	111097	10077	0	2
T3	966422	10124	0	2
T4	149102	10065	0	2
T5	809331	10178	0	2
T6	110408	10112	0	2
T7	174353	20106	0	2
T8	169724	20036	0	2
T9	141291	19998	0	2
T10	147699	20062	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	907182	0	32
T1	107581	34926	0	2
T2	111097	34933	0	2
T3	966422	34976	0	2
T4	149102	34913	0	2
T5	809331	35026	0	2
T6	110408	34964	0	2
T7	174353	69802	0	2
T8	169724	69748	0	2
T9	141291	69698	0	2
T10	147699	69762	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	7208054	0	32
T1	107581	104077	0	2
T2	111097	107593	0	2
T3	966422	931324	0	2
T4	149102	145598	0	2
T5	809331	774183	0	2
T6	110408	106901	0	2
T7	174353	104365	0	2
T8	169724	99804	0	2
T9	141291	71410	0	2
T10	147699	77765	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	7208080	0	0
T1	107581	104077	0	0
T2	111097	107594	0	0
T3	966422	931325	0	0
T4	149102	145598	0	0
T5	809331	774184	0	0
T6	110408	106901	0	0
T7	174353	104367	0	0
T8	169724	99806	0	0
T9	141291	71412	0	0
T10	147699	77767	0	0

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0