Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3748294	1			T11	5745		T12	577		T13	764
values[2]	741843	1			T11	1334		T12	35		T13	48
values[3]	105011	1			T11	174		T13	1		T14	24
values[4]	54536	1			T11	62		T14	3		T28	146
values[5]	36645	1			T11	13		T28	81		T53	284
values[6]	27199	1			T11	14		T28	43		T53	232
values[7]	22072	1			T11	2		T28	54		T53	134
values[8]	18473	1			T28	68		T53	54		T200	54
values[9]	16378	1			T28	61		T53	34		T200	36
values[10]	15180	1			T28	50		T53	11		T200	29
values[11]	14236	1			T28	79		T53	8		T200	24
values[12]	13318	1			T28	66		T53	3		T200	22
values[13]	12699	1			T28	54		T53	3		T200	19
values[14]	12196	1			T28	39		T53	2		T200	35
values[15]	11648	1			T28	32		T53	3		T200	33
values[16]	11243	1			T28	26		T53	4		T200	32
values[17]	10980	1			T28	34		T53	8		T200	36
values[18]	10533	1			T28	33		T53	8		T200	26
values[19]	10185	1			T28	33		T53	3		T200	27
values[20]	9852	1			T28	33		T53	3		T200	21
values[21]	9756	1			T28	31		T53	4		T200	17
values[22]	9542	1			T28	31		T53	2		T200	18
values[23]	9206	1			T28	21		T53	2		T200	13
values[24]	8506	1			T28	26		T53	1		T200	15
values[25]	8626	1			T28	29		T53	1		T200	11
values[26]	8237	1			T28	36		T53	1		T200	13
values[27]	7711	1			T28	39		T53	1		T200	16
values[28]	7282	1			T28	33		T53	1		T200	11
values[29]	7000	1			T28	8		T53	1		T200	11
values[30]	6478	1			T28	15		T53	3		T200	14
values[31]	5976	1			T28	9		T53	2		T200	18
values[32]	5476	1			T28	11		T53	1		T200	9
values[33]	5201	1			T28	8		T53	1		T200	27
values[34]	4758	1			T28	5		T53	1		T200	14
values[35]	4466	1			T28	10		T53	3		T200	21
values[36]	4052	1			T28	7		T53	2		T200	12
values[37]	3960	1			T28	12		T53	1		T200	10
values[38]	3768	1			T28	6		T53	1		T200	6
values[39]	3667	1			T28	6		T53	1		T200	5
values[40]	3431	1			T28	4		T53	2		T200	4
values[41]	3401	1			T28	4		T53	2		T200	2
values[42]	3415	1			T28	5		T53	2		T200	2
values[43]	3296	1			T28	4		T53	2		T200	2
values[44]	3259	1			T28	4		T53	1		T200	4
values[45]	3246	1			T28	7		T53	1		T200	5
values[46]	3064	1			T28	8		T53	2		T200	2
values[47]	3051	1			T28	13		T53	2		T200	4
values[48]	3057	1			T28	8		T53	1		T200	5
values[49]	2952	1			T28	6		T53	1		T200	5
values[50]	2881	1			T28	5		T53	1		T200	4
values[51]	2784	1			T28	3		T53	1		T200	2
values[52]	2679	1			T28	3		T53	6		T200	5
values[53]	2639	1			T28	5		T53	2		T200	2
values[54]	2593	1			T28	6		T53	4		T200	3
values[55]	2609	1			T28	7		T53	1		T200	6
values[56]	2566	1			T28	9		T53	1		T200	5
values[57]	2616	1			T28	5		T53	2		T200	6
values[58]	2558	1			T28	3		T53	2		T200	9
values[59]	2490	1			T28	14		T53	2		T200	9
values[60]	2413	1			T28	4		T53	2		T200	3
values[61]	2724	1			T28	6		T53	6		T200	5
values[62]	4492	1			T28	21		T53	3		T200	7
values[63]	16636	1			T28	105		T53	22		T200	30
values[64]	223651	1			T28	205		T53	81		T200	223

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4796874	1			T11	6915		T12	557		T13	819
values[2]	791079	1			T11	712		T12	40		T13	57
values[3]	72466	1			T11	24		T12	4		T13	4
values[4]	13592	1			T11	3		T14	41		T28	28
values[5]	5474	1			T14	24		T28	14		T53	62
values[6]	3217	1			T14	17		T28	10		T53	57
values[7]	2325	1			T14	29		T28	8		T53	39
values[8]	2110	1			T14	19		T28	10		T53	25
values[9]	1705	1			T14	10		T28	24		T53	1
values[10]	1507	1			T14	7		T28	23		T53	1
values[11]	1271	1			T14	5		T28	17		T53	1
values[12]	1217	1			T14	20		T28	13		T53	1
values[13]	1159	1			T14	33		T28	14		T53	4
values[14]	1110	1			T14	28		T28	13		T53	5
values[15]	1081	1			T14	13		T28	9		T53	3
values[16]	962	1			T14	13		T28	13		T53	9
values[17]	890	1			T14	6		T28	7		T53	6
values[18]	839	1			T14	1		T28	7		T53	7
values[19]	821	1			T14	1		T28	4		T53	2
values[20]	916	1			T14	3		T28	10		T53	1
values[21]	825	1			T28	5		T53	1		T200	4
values[22]	768	1			T28	10		T53	1		T200	5
values[23]	756	1			T28	13		T53	1		T200	3
values[24]	688	1			T28	11		T53	1		T200	3
values[25]	681	1			T28	4		T53	1		T200	13
values[26]	673	1			T28	3		T53	1		T200	14
values[27]	629	1			T28	2		T53	4		T200	11
values[28]	601	1			T28	5		T53	5		T200	1
values[29]	648	1			T28	8		T53	13		T200	1
values[30]	550	1			T28	3		T53	4		T200	2
values[31]	481	1			T28	4		T200	1		T82	1
values[32]	516	1			T28	4		T200	1		T82	1
values[33]	500	1			T28	3		T200	2		T82	1
values[34]	546	1			T28	9		T200	1		T82	1
values[35]	486	1			T28	4		T200	4		T82	2
values[36]	450	1			T28	1		T200	1		T82	1
values[37]	441	1			T28	1		T200	2		T82	1
values[38]	461	1			T28	2		T200	2		T82	1
values[39]	455	1			T28	3		T200	2		T82	1
values[40]	433	1			T28	3		T200	1		T82	1
values[41]	440	1			T28	3		T200	4		T82	1
values[42]	417	1			T28	1		T200	7		T82	1
values[43]	440	1			T28	7		T200	1		T82	1
values[44]	430	1			T28	1		T200	2		T82	1
values[45]	435	1			T28	1		T200	1		T82	1
values[46]	413	1			T28	1		T200	2		T82	1
values[47]	400	1			T28	2		T200	1		T82	1
values[48]	423	1			T28	1		T200	1		T82	1
values[49]	403	1			T28	1		T200	1		T82	1
values[50]	421	1			T28	4		T200	2		T82	1
values[51]	396	1			T28	3		T200	1		T82	1
values[52]	402	1			T28	5		T200	1		T82	1
values[53]	392	1			T28	2		T200	1		T82	1
values[54]	374	1			T28	2		T200	1		T82	1
values[55]	371	1			T28	1		T200	1		T82	1
values[56]	348	1			T28	1		T200	1		T82	1
values[57]	344	1			T28	1		T200	1		T82	1
values[58]	365	1			T28	1		T200	1		T82	1
values[59]	356	1			T28	2		T200	3		T82	1
values[60]	357	1			T28	1		T200	2		T82	1
values[61]	377	1			T28	1		T200	1		T82	1
values[62]	702	1			T28	7		T200	10		T82	1
values[63]	3517	1			T28	24		T200	39		T82	25
values[64]	25503	1			T28	59		T200	94		T82	181

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	618798	1			T11	2412		T12	57		T13	246
values[2]	2702125	1			T11	3699		T12	214		T13	506
values[3]	1111178	1			T11	1249		T12	323		T13	59
values[4]	142837	1			T11	145		T12	1		T14	107
values[5]	70118	1			T11	58		T14	47		T28	175
values[6]	45741	1			T11	53		T14	24		T28	120
values[7]	33560	1			T11	18		T14	32		T28	81
values[8]	26879	1			T11	11		T14	27		T28	73
values[9]	22730	1			T11	18		T14	13		T28	53
values[10]	19486	1			T11	24		T14	9		T28	42
values[11]	18243	1			T11	5		T14	19		T28	61
values[12]	16936	1			T11	6		T14	17		T28	83
values[13]	15974	1			T11	7		T14	15		T28	85
values[14]	14897	1			T11	5		T14	7		T28	72
values[15]	14172	1			T11	1		T14	8		T28	73
values[16]	13661	1			T14	4		T28	72		T53	27
values[17]	13070	1			T14	13		T28	68		T53	15
values[18]	12408	1			T14	10		T28	43		T53	8
values[19]	11701	1			T14	16		T28	39		T53	4
values[20]	11448	1			T14	20		T28	38		T53	1
values[21]	11011	1			T14	21		T28	43		T53	1
values[22]	10878	1			T14	9		T28	56		T53	8
values[23]	10706	1			T14	4		T28	50		T53	11
values[24]	9961	1			T14	3		T28	23		T53	2
values[25]	9606	1			T14	2		T28	26		T53	1
values[26]	9077	1			T14	2		T28	40		T53	3
values[27]	8609	1			T14	5		T28	48		T53	5
values[28]	8272	1			T14	9		T28	48		T53	10
values[29]	7681	1			T14	9		T28	33		T53	5
values[30]	7073	1			T14	4		T28	17		T53	1
values[31]	6768	1			T14	8		T28	12		T53	3
values[32]	6322	1			T14	10		T28	14		T53	2
values[33]	5825	1			T14	8		T28	14		T53	6
values[34]	5333	1			T14	17		T28	17		T53	6
values[35]	5003	1			T14	15		T28	11		T53	9
values[36]	4726	1			T14	11		T28	10		T53	4
values[37]	4320	1			T14	12		T28	6		T53	5
values[38]	4058	1			T14	8		T28	8		T53	3
values[39]	3863	1			T14	5		T28	11		T53	2
values[40]	3789	1			T14	16		T28	5		T53	2
values[41]	3525	1			T14	9		T28	9		T53	2
values[42]	3568	1			T14	15		T28	6		T53	4
values[43]	3438	1			T14	16		T28	16		T53	10
values[44]	3479	1			T14	10		T28	11		T53	6
values[45]	3382	1			T14	18		T28	12		T53	2
values[46]	3292	1			T14	11		T28	8		T53	1
values[47]	3239	1			T14	15		T28	8		T53	2
values[48]	3288	1			T14	10		T28	11		T53	6
values[49]	3219	1			T14	1		T28	11		T53	12
values[50]	3041	1			T28	11		T53	11		T200	5
values[51]	2964	1			T28	10		T53	6		T200	4
values[52]	2906	1			T28	9		T53	4		T200	4
values[53]	2896	1			T28	8		T53	2		T200	2
values[54]	2846	1			T28	10		T53	1		T200	3
values[55]	2865	1			T28	8		T53	5		T200	5
values[56]	2785	1			T28	8		T53	3		T200	10
values[57]	2720	1			T28	12		T53	2		T200	6
values[58]	2673	1			T28	12		T200	10		T337	1
values[59]	2543	1			T28	6		T200	3		T337	1
values[60]	2591	1			T28	17		T200	3		T337	1
values[61]	2674	1			T28	12		T200	2		T337	1
values[62]	3969	1			T28	20		T200	11		T337	1
values[63]	18734	1			T28	139		T200	49		T337	1
values[64]	212105	1			T28	308		T200	180		T337	193