Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	837906	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1583775

1

T1

39

T2

39

T3

39

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1761814	1			T15	12409		T16	12217		T40	79
values[0x0]	316057	1			T1	18		T2	20		T3	18
values[0x1]	343810	1			T1	21		T2	19		T3	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	626804	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1794877

1

T1

39

T2

39

T3

39

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	41652	1			T15	435		T16	361		T40	8
valid_sources[0x01]	37843	1			T1	3		T15	480		T16	381
valid_sources[0x02]	37916	1			T15	414		T16	332		T40	21
valid_sources[0x03]	38707	1			T1	2		T15	473		T16	436
valid_sources[0x04]	38130	1			T2	3		T6	2		T15	393
valid_sources[0x05]	37944	1			T6	3		T15	373		T16	425
valid_sources[0x06]	37229	1			T2	1		T15	333		T16	350
valid_sources[0x07]	38453	1			T3	7		T6	4		T15	388
valid_sources[0x08]	37295	1			T6	1		T15	433		T16	343
valid_sources[0x09]	37717	1			T2	1		T3	1		T15	345
valid_sources[0x0a]	37661	1			T15	401		T16	385		T40	1
valid_sources[0x0b]	37736	1			T1	1		T3	1		T15	335
valid_sources[0x0c]	37457	1			T3	7		T15	380		T16	461
valid_sources[0x0d]	37565	1			T1	2		T2	3		T6	2
valid_sources[0x0e]	37584	1			T15	507		T16	380		T40	6
valid_sources[0x0f]	37872	1			T6	1		T15	377		T16	444
valid_sources[0x10]	37661	1			T15	405		T16	350		T40	6
valid_sources[0x11]	37586	1			T6	1		T15	390		T16	436
valid_sources[0x12]	37358	1			T15	469		T16	383		T40	8
valid_sources[0x13]	39451	1			T3	7		T15	383		T16	346
valid_sources[0x14]	38519	1			T1	2		T15	480		T16	313
valid_sources[0x15]	37391	1			T1	2		T3	3		T4	6
valid_sources[0x16]	38385	1			T6	3		T15	423		T16	447
valid_sources[0x17]	37842	1			T1	4		T15	346		T16	415
valid_sources[0x18]	38342	1			T1	2		T6	2		T15	433
valid_sources[0x19]	37747	1			T6	2		T15	306		T16	382
valid_sources[0x1a]	38048	1			T15	455		T16	348		T40	2
valid_sources[0x1b]	37790	1			T15	379		T16	416		T40	36
valid_sources[0x1c]	37793	1			T5	39		T15	325		T16	390
valid_sources[0x1d]	37402	1			T15	389		T16	396		T40	33
valid_sources[0x1e]	38169	1			T3	2		T15	450		T16	343
valid_sources[0x1f]	37722	1			T6	2		T15	314		T16	451
valid_sources[0x20]	37922	1			T15	363		T16	382		T40	53

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1058899

1

T15

12409

T16

12217

T40

68

values[0x0]

all_enables

biggest_size

270286

1

T1

18

T2

20

T3

18

values[0x1]

all_enables

biggest_size

254590

1

T1

21

T2

19

T3

21

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2992219	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

473975

1

T11

996

T12

70

T13

118

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1172656	1			T11	2488		T12	210		T13	243
values[0x0]	1121434	1			T11	2378		T12	180		T13	272
values[0x1]	1172104	1			T11	2478		T12	222		T13	298

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2318456	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1147738

1

T11

2450

T12

186

T13

270

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53631	1			T11	87		T12	13		T13	62
valid_sources[0x01]	54022	1			T11	124		T12	14		T14	171
valid_sources[0x02]	53951	1			T11	125		T12	12		T14	157
valid_sources[0x03]	55251	1			T11	169		T12	2		T13	67
valid_sources[0x04]	53790	1			T11	148		T12	11		T13	33
valid_sources[0x05]	54088	1			T11	82		T12	15		T13	14
valid_sources[0x06]	54500	1			T11	253		T12	12		T13	2
valid_sources[0x07]	54733	1			T11	78		T12	6		T13	27
valid_sources[0x08]	54344	1			T11	102		T12	11		T13	30
valid_sources[0x09]	53273	1			T11	136		T12	9		T13	17
valid_sources[0x0a]	52881	1			T11	67		T12	8		T14	50
valid_sources[0x0b]	55171	1			T11	99		T12	5		T14	131
valid_sources[0x0c]	54178	1			T11	122		T12	10		T14	59
valid_sources[0x0d]	54493	1			T11	86		T12	8		T14	61
valid_sources[0x0e]	53114	1			T11	153		T12	10		T14	90
valid_sources[0x0f]	54751	1			T11	189		T12	8		T14	61
valid_sources[0x10]	54243	1			T11	99		T12	11		T13	21
valid_sources[0x11]	53935	1			T11	81		T12	8		T14	122
valid_sources[0x12]	54119	1			T11	73		T12	7		T13	28
valid_sources[0x13]	53526	1			T11	89		T12	8		T13	13
valid_sources[0x14]	54080	1			T11	87		T12	9		T14	54
valid_sources[0x15]	55100	1			T11	139		T12	11		T13	33
valid_sources[0x16]	54052	1			T11	110		T12	9		T13	30
valid_sources[0x17]	55150	1			T11	62		T12	8		T13	37
valid_sources[0x18]	55178	1			T11	44		T12	14		T13	18
valid_sources[0x19]	54103	1			T11	71		T12	10		T14	124
valid_sources[0x1a]	55138	1			T11	152		T12	3		T13	15
valid_sources[0x1b]	54197	1			T11	68		T12	14		T13	11
valid_sources[0x1c]	54220	1			T11	141		T12	11		T13	4
valid_sources[0x1d]	53511	1			T11	90		T12	11		T14	57
valid_sources[0x1e]	54155	1			T11	165		T12	5		T13	22
valid_sources[0x1f]	54874	1			T11	146		T12	9		T13	17
valid_sources[0x20]	53817	1			T11	137		T12	11		T14	55

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49697

1

T11

119

T12

11

T13

8

values[0x0]

all_enables

biggest_size

374364

1

T11

769

T12

54

T13

95

values[0x1]

all_enables

biggest_size

49914

1

T11

108

T12

5

T13

15

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3185874	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

518376

1

T11

1070

T12

95

T13

123

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1268201	1			T11	2608		T12	201		T13	284
values[0x0]	1170652	1			T11	2462		T12	207		T13	285
values[0x1]	1265397	1			T11	2584		T12	193		T13	311

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2446541	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1257709

1

T11

2560

T12

220

T13

304

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57389	1			T11	109		T12	6		T13	10
valid_sources[0x01]	57545	1			T11	122		T12	12		T13	8
valid_sources[0x02]	59428	1			T11	182		T12	7		T13	5
valid_sources[0x03]	57433	1			T11	211		T12	6		T13	1
valid_sources[0x04]	58340	1			T11	159		T12	6		T13	9
valid_sources[0x05]	56648	1			T11	166		T12	14		T13	7
valid_sources[0x06]	57710	1			T11	143		T12	14		T13	15
valid_sources[0x07]	57957	1			T11	104		T12	10		T13	6
valid_sources[0x08]	58853	1			T11	112		T12	9		T13	17
valid_sources[0x09]	57833	1			T11	140		T12	10		T13	7
valid_sources[0x0a]	57658	1			T11	57		T12	11		T13	20
valid_sources[0x0b]	57261	1			T11	90		T12	7		T14	137
valid_sources[0x0c]	58064	1			T11	106		T12	7		T13	24
valid_sources[0x0d]	58766	1			T11	113		T12	14		T13	30
valid_sources[0x0e]	57293	1			T11	85		T12	5		T13	26
valid_sources[0x0f]	59181	1			T11	185		T12	11		T14	122
valid_sources[0x10]	57557	1			T11	105		T12	17		T13	12
valid_sources[0x11]	57101	1			T11	122		T12	5		T13	2
valid_sources[0x12]	57317	1			T11	84		T12	10		T13	53
valid_sources[0x13]	57976	1			T11	62		T12	10		T13	14
valid_sources[0x14]	58213	1			T11	135		T12	4		T13	10
valid_sources[0x15]	57344	1			T11	109		T12	12		T13	29
valid_sources[0x16]	57825	1			T11	87		T12	13		T13	9
valid_sources[0x17]	58076	1			T11	51		T12	13		T13	14
valid_sources[0x18]	58064	1			T11	57		T12	12		T13	2
valid_sources[0x19]	56775	1			T11	82		T12	9		T13	20
valid_sources[0x1a]	57994	1			T11	149		T12	9		T13	18
valid_sources[0x1b]	57054	1			T11	107		T12	9		T13	3
valid_sources[0x1c]	57809	1			T11	189		T12	5		T13	11
valid_sources[0x1d]	57369	1			T11	93		T12	11		T13	13
valid_sources[0x1e]	58112	1			T11	149		T12	13		T13	21
valid_sources[0x1f]	57580	1			T11	146		T12	4		T13	15
valid_sources[0x20]	58319	1			T11	124		T12	14		T13	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

54129

1

T11

96

T12

8

T13

15

values[0x0]

all_enables

biggest_size

410119

1

T11

868

T12

79

T13

92

values[0x1]

all_enables

biggest_size

54128

1

T11

106

T12

8

T13

16

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3010749	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

477615

1

T11

1074

T12

100

T13

113

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1179939	1			T11	2562		T12	198		T13	271
values[0x0]	1128214	1			T11	2561		T12	220		T13	266
values[0x1]	1180211	1			T11	2588		T12	177		T13	274

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2330609	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1157755

1

T11

2536

T12

214

T13

279

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54041	1			T11	74		T12	10		T13	7
valid_sources[0x01]	53825	1			T11	128		T12	11		T13	16
valid_sources[0x02]	55201	1			T11	121		T12	14		T13	18
valid_sources[0x03]	54806	1			T11	210		T12	9		T13	8
valid_sources[0x04]	55330	1			T11	196		T12	9		T13	12
valid_sources[0x05]	54917	1			T11	129		T12	17		T13	8
valid_sources[0x06]	54611	1			T11	220		T12	6		T13	11
valid_sources[0x07]	54842	1			T11	107		T12	11		T13	17
valid_sources[0x08]	55150	1			T11	117		T12	14		T13	15
valid_sources[0x09]	53205	1			T11	111		T12	4		T13	15
valid_sources[0x0a]	53977	1			T11	91		T12	2		T13	14
valid_sources[0x0b]	54308	1			T11	77		T12	2		T13	10
valid_sources[0x0c]	54967	1			T11	144		T12	8		T13	23
valid_sources[0x0d]	55053	1			T11	96		T12	12		T13	25
valid_sources[0x0e]	54750	1			T11	89		T12	6		T13	15
valid_sources[0x0f]	54728	1			T11	163		T12	6		T13	13
valid_sources[0x10]	54468	1			T11	91		T12	10		T13	17
valid_sources[0x11]	54347	1			T11	103		T12	12		T13	12
valid_sources[0x12]	54449	1			T11	73		T12	16		T13	9
valid_sources[0x13]	54044	1			T11	104		T12	9		T13	7
valid_sources[0x14]	55473	1			T11	110		T12	9		T13	19
valid_sources[0x15]	54705	1			T11	117		T12	6		T13	11
valid_sources[0x16]	54494	1			T11	95		T12	8		T13	17
valid_sources[0x17]	54891	1			T11	86		T12	9		T13	5
valid_sources[0x18]	54623	1			T11	85		T12	8		T13	10
valid_sources[0x19]	54144	1			T11	84		T12	12		T13	9
valid_sources[0x1a]	54156	1			T11	158		T12	10		T13	12
valid_sources[0x1b]	54132	1			T11	124		T12	11		T13	8
valid_sources[0x1c]	53898	1			T11	196		T12	12		T13	14
valid_sources[0x1d]	53973	1			T11	88		T12	8		T13	15
valid_sources[0x1e]	53850	1			T11	164		T12	11		T13	14
valid_sources[0x1f]	55043	1			T11	136		T12	15		T13	12
valid_sources[0x20]	54687	1			T11	144		T12	6		T13	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50135

1

T11

88

T12

7

T13

10

values[0x0]

all_enables

biggest_size

377649

1

T11

870

T12

87

T13

90

values[0x1]

all_enables

biggest_size

49831

1

T11

116

T12

6

T13

13