Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sram_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.99 51.99

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_sram_ctrl_ret_aon 51.82 51.82
tb.dut.top_earlgrey.u_sram_ctrl_main 52.57 52.57


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.82 51.82


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
51.82 51.82


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
79.60 53.96 84.85 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
52.57 52.57


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
52.57 52.57


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
79.60 53.96 84.85 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : sram_ctrl
TotalCoveredPercent
Totals 64 52 81.25
Total Bits 1158 602 51.99
Total Bits 0->1 579 301 51.99
Total Bits 1->0 579 301 51.99

Ports 64 52 81.25
Port Bits 1158 602 51.99
Port Bits 0->1 579 301 51.99
Port Bits 1->0 579 301 51.99

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[16:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
ram_tl_i.a_address[20:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[27:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_sink Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
ram_tl_o.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[1:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
regs_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T1,T11,T12 Yes T1,T11,T12 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T1,T11,T12 Yes T1,T11,T12 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[4:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
regs_tl_i.a_address[17:5] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] Yes Yes T1,T2,T11 Yes T1,T2,T11 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T1,*T11,*T12 Yes T1,T11,T12 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_valid Yes Yes T1,T11,T12 Yes T1,T11,T12 INPUT
regs_tl_o.a_ready Yes Yes T1,T12,T13 Yes T1,T11,T12 OUTPUT
regs_tl_o.d_error Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T1,T11,T12 Yes T1,T11,T12 OUTPUT
regs_tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T11,T12 Yes T1,T11,T12 OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T1,T11,T12 Yes T1,T11,T12 OUTPUT
regs_tl_o.d_sink Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
regs_tl_o.d_source[5:0] Yes Yes *T1,T11,T12 Yes T1,T11,T12 OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[1:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T1,*T11,*T12 Yes T1,T11,T12 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T1,T11,T12 Yes T1,T11,T12 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T15,T16,T18 Yes T15,T16,T18 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T15,T16,T18 Yes T15,T16,T18 OUTPUT
lc_escalate_en_i[3:0] No No No INPUT
lc_hw_debug_en_i[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[2:1] No No No INPUT
otp_en_sram_ifetch_i[3] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[4] No No No INPUT
otp_en_sram_ifetch_i[6:5] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[7] No No No INPUT
sram_otp_key_o.req Yes Yes T23,T19,T20 Yes T23,T19,T20 OUTPUT
sram_otp_key_i.seed_valid No No No INPUT
sram_otp_key_i.nonce[127:0] No No No INPUT
sram_otp_key_i.key[127:0] No No No INPUT
sram_otp_key_i.ack No No No INPUT
cfg_i.rf_cfg.cfg[3:0] No No No INPUT
cfg_i.rf_cfg.cfg_en No No No INPUT
cfg_i.ram_cfg.cfg[3:0] No No No INPUT
cfg_i.ram_cfg.cfg_en No No No INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon
TotalCoveredPercent
Totals 58 51 87.93
Total Bits 1096 568 51.82
Total Bits 0->1 548 284 51.82
Total Bits 1->0 548 284 51.82

Ports 58 51 87.93
Port Bits 1096 568 51.82
Port Bits 0->1 548 284 51.82
Port Bits 1->0 548 284 51.82

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[11:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
ram_tl_i.a_address[20:12] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_sink Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
ram_tl_o.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[1:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
regs_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T1,T11,T12 Yes T1,T11,T12 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T1,T11,T12 Yes T1,T11,T12 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[4:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
regs_tl_i.a_address[19:5] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20] Yes Yes *T1,*T2,*T11 Yes T1,T2,T11 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_valid Yes Yes T1,T11,T12 Yes T1,T11,T12 INPUT
regs_tl_o.a_ready Yes Yes T1,T12,T13 Yes T1,T11,T12 OUTPUT
regs_tl_o.d_error Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T1,T11,T12 Yes T1,T11,T13 OUTPUT
regs_tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T11,T12 Yes T1,T11,T12 OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T1,T11,T12 Yes T1,T11,T12 OUTPUT
regs_tl_o.d_sink Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
regs_tl_o.d_source[5:0] Yes Yes *T1,T11,T12 Yes T1,T11,T12 OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[1:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T1,*T11,*T12 Yes T1,T11,T12 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T1,T11,T12 Yes T1,T11,T12 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T15,T16,T18 Yes T15,T16,T18 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T15,T16,T18 Yes T15,T16,T18 OUTPUT
lc_escalate_en_i[3:0] No No No INPUT
lc_hw_debug_en_i[3:0] Unreachable Unreachable Unreachable INPUT
otp_en_sram_ifetch_i[7:0] Unreachable Unreachable Unreachable INPUT
sram_otp_key_o.req Yes Yes T19,T20 Yes T19,T20 OUTPUT
sram_otp_key_i.seed_valid No No No INPUT
sram_otp_key_i.nonce[127:0] No No No INPUT
sram_otp_key_i.key[127:0] No No No INPUT
sram_otp_key_i.ack No No No INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_main
TotalCoveredPercent
Totals 60 52 86.67
Total Bits 1130 594 52.57
Total Bits 0->1 565 297 52.57
Total Bits 1->0 565 297 52.57

Ports 60 52 86.67
Port Bits 1130 594 52.57
Port Bits 0->1 565 297 52.57
Port Bits 1->0 565 297 52.57

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[16:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
ram_tl_i.a_address[27:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[31:29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[2:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
ram_tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_sink Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
ram_tl_o.d_source[5:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[1:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
regs_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T1,T11,T12 Yes T1,T11,T12 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T11,T12 Yes T1,T11,T12 INPUT
regs_tl_i.a_user.instr_type[3:0] Yes Yes T1,T11,T12 Yes T1,T11,T12 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T1,T11,T12 Yes T1,T11,T12 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T1,T11,T12 Yes T1,T11,T12 INPUT
regs_tl_i.a_address[4:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
regs_tl_i.a_address[17:5] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] Yes Yes T1,T11,T12 Yes T1,T11,T12 INPUT
regs_tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T1,*T11,*T12 Yes T1,T11,T12 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T1,*T11,*T12 Yes T1,T11,T12 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T1,T11,T12 Yes T1,T11,T12 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[2:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
regs_tl_i.a_valid Yes Yes T1,T11,T12 Yes T1,T11,T12 INPUT
regs_tl_o.a_ready Yes Yes T1,T12,T13 Yes T1,T11,T12 OUTPUT
regs_tl_o.d_error Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T1,T11,T12 Yes T1,T11,T12 OUTPUT
regs_tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T11,T12 Yes T1,T11,T12 OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T1,T11,T12 Yes T1,T11,T12 OUTPUT
regs_tl_o.d_sink Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
regs_tl_o.d_source[5:0] Yes Yes *T1,T11,T12 Yes T1,T11,T12 OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[1:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T1,*T11,*T12 Yes T1,T11,T12 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T1,T11,T12 Yes T1,T11,T12 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T15,T16,T17 Yes T15,T16,T17 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T15,T16,T17 Yes T15,T16,T17 OUTPUT
lc_escalate_en_i[3:0] No No No INPUT
lc_hw_debug_en_i[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[2:1] No No No INPUT
otp_en_sram_ifetch_i[3] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[4] No No No INPUT
otp_en_sram_ifetch_i[6:5] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[7] No No No INPUT
sram_otp_key_o.req Yes Yes T23,T20,T21 Yes T23,T20,T21 OUTPUT
sram_otp_key_i.seed_valid No No No INPUT
sram_otp_key_i.nonce[127:0] No No No INPUT
sram_otp_key_i.key[127:0] No No No INPUT
sram_otp_key_i.ack No No No INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%