Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	168011	1			T69	68		T70	69		T71	3
values[2]	4303	1			T485	1		T397	20		T366	2
values[3]	1914	1			T397	11		T488	1		T487	1
values[4]	1471	1			T397	16		T487	1		T495	1
values[5]	1204	1			T397	46		T487	1		T495	1
values[6]	1028	1			T397	25		T487	1		T495	1
values[7]	855	1			T397	12		T487	1		T495	1
values[8]	640	1			T397	4		T487	1		T495	1
values[9]	631	1			T397	2		T487	1		T495	1
values[10]	568	1			T397	2		T487	1		T495	1
values[11]	562	1			T397	6		T487	1		T495	1
values[12]	541	1			T397	7		T487	1		T495	1
values[13]	539	1			T397	9		T487	1		T495	1
values[14]	559	1			T397	3		T487	1		T495	1
values[15]	514	1			T397	2		T487	1		T495	1
values[16]	449	1			T397	6		T487	1		T495	1
values[17]	346	1			T397	7		T487	1		T495	1
values[18]	368	1			T397	25		T487	1		T495	1
values[19]	409	1			T397	22		T487	1		T495	1
values[20]	403	1			T397	12		T487	1		T495	1
values[21]	367	1			T397	5		T487	1		T495	1
values[22]	327	1			T397	2		T487	1		T495	1
values[23]	242	1			T397	3		T487	1		T495	1
values[24]	169	1			T487	2		T495	1		T486	4
values[25]	151	1			T487	1		T495	1		T486	2
values[26]	140	1			T487	1		T495	1		T486	3
values[27]	107	1			T487	1		T495	1		T486	1
values[28]	91	1			T487	1		T495	1		T486	2
values[29]	86	1			T487	1		T495	1		T486	3
values[30]	103	1			T487	1		T495	1		T486	4
values[31]	85	1			T487	1		T495	1		T486	5
values[32]	76	1			T487	1		T495	1		T486	2
values[33]	74	1			T487	1		T495	1		T486	2
values[34]	70	1			T487	1		T495	1		T486	3
values[35]	75	1			T487	1		T495	1		T486	9
values[36]	68	1			T487	1		T495	1		T486	7
values[37]	60	1			T487	1		T495	1		T486	4
values[38]	53	1			T487	1		T495	1		T486	5
values[39]	61	1			T487	1		T495	1		T486	1
values[40]	55	1			T487	1		T495	1		T486	1
values[41]	69	1			T487	1		T495	1		T486	4
values[42]	66	1			T487	1		T495	1		T486	3
values[43]	84	1			T487	1		T495	1		T486	2
values[44]	89	1			T487	1		T495	1		T486	5
values[45]	62	1			T487	1		T495	1		T486	5
values[46]	71	1			T487	1		T495	1		T486	5
values[47]	63	1			T487	1		T495	1		T486	4
values[48]	44	1			T487	1		T495	1		T486	2
values[49]	46	1			T487	1		T495	1		T486	2
values[50]	51	1			T487	1		T495	1		T486	1
values[51]	50	1			T487	1		T495	1		T486	3
values[52]	47	1			T487	1		T495	1		T486	2
values[53]	48	1			T487	1		T495	1		T486	3
values[54]	49	1			T487	1		T495	1		T486	3
values[55]	44	1			T487	1		T495	1		T486	2
values[56]	47	1			T487	1		T495	1		T486	4
values[57]	41	1			T487	1		T495	1		T486	1
values[58]	50	1			T487	1		T495	1		T486	2
values[59]	53	1			T487	1		T495	1		T486	2
values[60]	52	1			T487	1		T495	1		T486	6
values[61]	51	1			T487	1		T495	1		T486	2
values[62]	50	1			T487	1		T495	1		T486	2
values[63]	48	1			T487	1		T495	1		T486	2
values[64]	41	1			T487	1		T495	1		T486	3
values[65]	55	1			T487	1		T495	1		T486	6
values[66]	50	1			T487	1		T495	1		T486	8
values[67]	40	1			T487	1		T495	1		T486	6
values[68]	53	1			T487	1		T495	1		T486	4
values[69]	56	1			T487	1		T495	1		T486	2
values[70]	53	1			T487	1		T495	1		T486	1
values[71]	51	1			T487	1		T495	1		T486	2
values[72]	58	1			T487	1		T495	1		T486	2
values[73]	48	1			T487	1		T495	1		T486	1
values[74]	51	1			T487	1		T495	1		T486	2
values[75]	58	1			T487	1		T495	1		T486	1
values[76]	61	1			T487	1		T495	1		T486	4
values[77]	64	1			T487	1		T495	1		T486	2
values[78]	66	1			T487	1		T495	1		T486	1
values[79]	66	1			T487	1		T495	1		T486	6
values[80]	65	1			T487	1		T495	1		T486	3
values[81]	61	1			T487	1		T495	1		T486	3
values[82]	57	1			T487	1		T495	1		T486	3
values[83]	65	1			T487	1		T495	1		T486	5
values[84]	63	1			T487	1		T495	1		T486	3
values[85]	64	1			T487	1		T495	1		T486	2
values[86]	67	1			T487	1		T495	1		T486	3
values[87]	72	1			T487	1		T495	1		T486	5
values[88]	59	1			T487	1		T495	1		T486	1
values[89]	61	1			T487	1		T495	1		T486	2
values[90]	65	1			T487	1		T495	1		T486	4
values[91]	61	1			T487	1		T495	1		T486	7
values[92]	55	1			T487	1		T495	1		T486	2
values[93]	63	1			T487	1		T495	1		T486	2
values[94]	59	1			T487	1		T495	1		T486	2
values[95]	67	1			T487	1		T495	1		T486	1
values[96]	60	1			T487	1		T495	1		T486	1
values[97]	83	1			T487	1		T495	1		T486	6
values[98]	75	1			T487	1		T495	1		T486	7
values[99]	72	1			T487	1		T495	1		T486	3
values[100]	69	1			T487	1		T495	1		T486	12
values[101]	63	1			T487	1		T495	1		T486	5
values[102]	67	1			T487	1		T495	1		T486	4
values[103]	63	1			T487	1		T495	1		T486	8
values[104]	58	1			T487	1		T495	1		T486	2
values[105]	82	1			T487	1		T495	1		T486	6
values[106]	86	1			T487	1		T495	1		T486	3
values[107]	67	1			T487	1		T495	2		T486	2
values[108]	78	1			T487	1		T495	1		T486	1
values[109]	75	1			T487	1		T495	1		T486	1
values[110]	62	1			T487	1		T495	1		T486	5
values[111]	76	1			T487	1		T495	2		T486	6
values[112]	78	1			T487	1		T495	1		T486	3
values[113]	81	1			T487	1		T495	1		T486	4
values[114]	87	1			T487	1		T495	4		T486	5
values[115]	118	1			T487	1		T495	3		T486	12
values[116]	106	1			T487	1		T495	9		T486	1
values[117]	89	1			T487	1		T495	1		T486	2
values[118]	86	1			T487	1		T495	5		T486	5
values[119]	81	1			T487	1		T495	4		T486	5
values[120]	83	1			T487	1		T495	1		T486	3
values[121]	64	1			T487	2		T495	1		T486	4
values[122]	75	1			T487	4		T495	2		T486	6
values[123]	95	1			T487	3		T495	2		T486	7
values[124]	173	1			T487	3		T495	1		T486	32
values[125]	241	1			T487	2		T495	2		T486	34
values[126]	537	1			T487	19		T495	11		T486	29
values[127]	2997	1			T487	163		T495	102		T486	20
values[128]	5327	1			T487	247		T495	180		T486	2