Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.91	95.21	93.87	95.03		94.38	97.38	99.58

Total tests in report: 2847

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.51	40.51	45.95	45.95	43.20	43.20	31.88	31.88			58.29	58.29	63.33	63.33	0.38	0.38	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1956884025
53.03	12.52	60.43	14.49	58.39	15.18	37.56	5.68			69.81	11.52	90.00	26.67	1.99	1.61	/workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.1716551297
58.22	5.19	71.59	11.16	66.03	7.65	39.91	2.35			79.78	9.98	90.00	0.00	1.99	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.3233364676
63.19	4.97	71.59	0.00	67.51	1.47	39.91	0.00			79.78	0.00	90.00	0.00	30.33	28.34	/workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.4062776750
66.45	3.26	76.62	5.03	68.76	1.25	43.95	4.04			79.96	0.17	90.00	0.00	39.41	9.08	/workspace/coverage/cover_reg_top/84.xbar_error_random.2762745622
69.66	3.22	76.63	0.01	68.78	0.02	63.15	19.20			79.97	0.02	90.00	0.00	39.46	0.05	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3361118504
72.73	3.07	76.63	0.00	68.78	0.00	63.15	0.00			79.97	0.00	90.00	0.00	57.85	18.39	/workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1297818211
75.18	2.45	76.63	0.00	69.30	0.52	63.15	0.00			79.97	0.00	90.00	0.00	72.04	14.20	/workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.1881088999
77.55	2.37	82.05	5.43	73.13	3.84	66.61	3.46			81.48	1.51	90.00	0.00	72.04	0.00	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.122410448
79.57	2.02	83.89	1.84	75.64	2.51	72.20	5.59			83.28	1.80	90.37	0.37	72.04	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1815716457
81.03	1.46	84.13	0.24	75.79	0.15	80.20	8.00			83.47	0.18	90.56	0.19	72.04	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1119239937
82.32	1.29	86.05	1.92	78.74	2.95	80.48	0.27			86.07	2.61	90.56	0.00	72.04	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2026330286
83.50	1.18	87.42	1.36	79.69	0.96	82.19	1.72			87.19	1.12	92.41	1.85	72.09	0.05	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1804024697
84.64	1.14	87.42	0.00	79.69	0.00	82.19	0.00			87.19	0.00	92.41	0.00	78.91	6.82	/workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3990039365
85.51	0.87	88.16	0.75	79.89	0.20	82.23	0.03			87.39	0.20	96.48	4.07	78.91	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.4186023928
86.35	0.84	89.41	1.24	80.95	1.06	83.77	1.55			88.59	1.20	96.48	0.00	78.91	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.2490148015
87.19	0.84	89.41	0.00	82.10	1.16	83.79	0.02			88.59	0.00	96.48	0.00	82.75	3.84	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.1675840737
87.87	0.69	89.41	0.00	82.10	0.00	83.79	0.00			88.59	0.00	96.48	0.00	86.86	4.11	/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.1517558371
88.49	0.62	90.36	0.96	83.42	1.31	84.14	0.34			89.68	1.10	96.48	0.00	86.86	0.00	/workspace/coverage/default/1.chip_sw_gpio.580860082
89.06	0.57	90.41	0.05	83.48	0.06	86.07	1.93			89.68	0.00	96.48	0.00	88.25	1.39	/workspace/coverage/default/0.chip_sw_alert_test.1059395372
89.62	0.56	91.59	1.18	84.29	0.81	86.08	0.01			91.04	1.36	96.48	0.00	88.25	0.00	/workspace/coverage/default/2.chip_sw_plic_sw_irq.3333839677
90.17	0.55	91.59	0.00	84.43	0.13	86.08	0.00			91.04	0.00	96.48	0.00	91.39	3.14	/workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.2944652213
90.65	0.48	91.61	0.01	86.98	2.55	86.08	0.00			91.04	0.00	96.48	0.00	91.73	0.34	/workspace/coverage/cover_reg_top/26.chip_tl_errors.2312693974
91.03	0.37	92.37	0.77	87.83	0.85	86.11	0.02			91.64	0.60	96.48	0.00	91.74	0.01	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.415464285
91.38	0.36	92.92	0.55	88.33	0.50	86.68	0.58			92.14	0.50	96.48	0.00	91.74	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.4185282296
91.66	0.27	92.92	0.00	88.42	0.09	86.68	0.00			92.16	0.02	96.48	0.00	93.27	1.53	/workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.1183403335
91.92	0.26	92.92	0.00	88.42	0.01	86.68	0.00			92.16	0.00	96.48	0.00	94.83	1.56	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.1848704114
92.18	0.26	92.92	0.00	88.52	0.09	86.68	0.00			92.16	0.00	96.48	0.00	96.29	1.46	/workspace/coverage/cover_reg_top/45.xbar_stress_all.1951973007
92.40	0.23	93.01	0.09	88.55	0.03	87.92	1.23			92.17	0.01	96.48	0.00	96.29	0.00	/workspace/coverage/default/2.chip_jtag_mem_access.2787845885
92.62	0.22	93.02	0.01	88.55	0.01	89.15	1.23			92.17	0.00	96.48	0.00	96.33	0.05	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.556972397
92.79	0.17	93.31	0.29	88.88	0.33	89.58	0.43			92.17	0.00	96.48	0.00	96.33	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2633068102
92.96	0.17	93.68	0.36	89.21	0.33	89.58	0.01			92.50	0.33	96.48	0.00	96.33	0.00	/workspace/coverage/cover_reg_top/7.chip_csr_rw.823312136
93.13	0.17	93.68	0.01	89.67	0.46	89.63	0.05			93.00	0.51	96.48	0.00	96.33	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3488515641
93.30	0.17	93.68	0.00	89.67	0.00	90.64	1.01			93.00	0.00	96.48	0.00	96.33	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3906134935
93.46	0.15	93.92	0.24	89.91	0.24	90.80	0.16			93.29	0.29	96.48	0.00	96.33	0.00	/workspace/coverage/default/1.chip_jtag_csr_rw.522958669
93.59	0.13	93.92	0.00	89.91	0.00	91.49	0.69			93.29	0.00	96.48	0.00	96.45	0.12	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3887171296
93.72	0.13	93.92	0.00	90.11	0.20	91.49	0.00			93.34	0.05	96.48	0.00	96.98	0.53	/workspace/coverage/cover_reg_top/97.xbar_stress_all.3948797782
93.84	0.12	94.04	0.12	90.29	0.18	91.81	0.31			93.43	0.08	96.48	0.00	96.98	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1792694445
93.95	0.11	94.04	0.00	90.32	0.03	91.81	0.00			93.44	0.01	96.48	0.00	97.60	0.62	/workspace/coverage/cover_reg_top/85.xbar_random_large_delays.2951471832
94.06	0.11	94.08	0.04	90.39	0.07	92.30	0.49			93.49	0.06	96.48	0.00	97.60	0.00	/workspace/coverage/default/49.chip_sw_all_escalation_resets.3217786509
94.16	0.10	94.12	0.04	90.44	0.05	92.75	0.46			93.53	0.04	96.48	0.00	97.61	0.01	/workspace/coverage/default/2.rom_e2e_shutdown_output.3506292296
94.26	0.10	94.12	0.00	90.61	0.17	92.75	0.00			93.53	0.00	96.48	0.00	98.05	0.43	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.1421421045
94.35	0.09	94.12	0.00	91.09	0.49	92.75	0.00			93.53	0.00	96.48	0.00	98.12	0.07	/workspace/coverage/cover_reg_top/16.chip_tl_errors.2906582911
94.42	0.07	94.26	0.14	91.20	0.11	92.82	0.06			93.66	0.12	96.48	0.00	98.12	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.979783527
94.50	0.07	94.27	0.01	91.40	0.19	92.83	0.01			93.88	0.22	96.48	0.00	98.12	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3443173593
94.56	0.06	94.27	0.00	91.40	0.00	93.19	0.37			93.88	0.00	96.48	0.00	98.12	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.717851839
94.61	0.05	94.27	0.00	91.72	0.32	93.19	0.00			93.88	0.00	96.48	0.00	98.12	0.00	/workspace/coverage/cover_reg_top/12.chip_tl_errors.2309582748
94.66	0.05	94.35	0.07	91.86	0.14	93.19	0.00			93.96	0.08	96.48	0.00	98.12	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.580531343
94.71	0.05	94.35	0.00	91.86	0.00	93.47	0.28			93.96	0.00	96.48	0.00	98.12	0.00	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2701545646
94.75	0.05	94.35	0.00	91.98	0.12	93.47	0.00			93.99	0.03	96.48	0.00	98.24	0.12	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.3385765090
94.79	0.04	94.35	0.00	91.98	0.00	93.73	0.25			93.99	0.00	96.48	0.00	98.24	0.00	/workspace/coverage/default/0.chip_sw_kmac_idle.823261929
94.84	0.04	94.38	0.03	91.98	0.01	93.73	0.01			94.01	0.02	96.67	0.19	98.25	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.1360667529
94.88	0.04	94.39	0.01	92.00	0.01	93.73	0.00			94.03	0.02	96.85	0.19	98.26	0.01	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3834692873
94.92	0.04	94.39	0.01	92.01	0.01	93.73	0.01			94.04	0.01	97.04	0.19	98.27	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.4103845557
94.95	0.04	94.40	0.01	92.03	0.01	93.73	0.00			94.05	0.01	97.22	0.19	98.28	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.2035986265
94.99	0.04	94.40	0.01	92.04	0.01	93.74	0.01			94.06	0.01	97.41	0.19	98.30	0.01	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3978945919
95.03	0.04	94.40	0.00	92.07	0.03	93.74	0.00			94.07	0.02	97.41	0.00	98.47	0.18	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.132401028
95.06	0.03	94.42	0.01	92.25	0.19	93.74	0.00			94.07	0.00	97.41	0.00	98.47	0.00	/workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.3075632902
95.09	0.03	94.47	0.05	92.30	0.05	93.80	0.06			94.10	0.02	97.41	0.00	98.47	0.00	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3253982862
95.12	0.03	94.47	0.00	92.46	0.16	93.80	0.00			94.10	0.00	97.41	0.00	98.47	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.1665176445
95.14	0.03	94.47	0.00	92.46	0.00	93.96	0.16			94.10	0.00	97.41	0.00	98.47	0.00	/workspace/coverage/default/1.chip_sw_aes_enc.3320509787
95.17	0.03	94.54	0.07	92.51	0.05	93.96	0.00			94.13	0.03	97.41	0.00	98.47	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1081380613
95.20	0.03	94.61	0.07	92.55	0.04	93.96	0.00			94.18	0.05	97.41	0.00	98.47	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3830261364
95.22	0.03	94.61	0.00	92.55	0.00	94.11	0.15			94.18	0.00	97.41	0.00	98.47	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.497209291
95.25	0.02	94.64	0.04	92.59	0.04	94.14	0.03			94.22	0.04	97.41	0.00	98.47	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.733574957
95.27	0.02	94.64	0.00	92.59	0.00	94.28	0.14			94.22	0.00	97.41	0.00	98.47	0.00	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.183924774
95.29	0.02	94.72	0.08	92.59	0.00	94.34	0.06			94.23	0.01	97.41	0.00	98.47	0.00	/workspace/coverage/default/2.chip_tap_straps_rma.732958603
95.31	0.02	94.72	0.00	92.69	0.10	94.34	0.00			94.25	0.02	97.41	0.00	98.48	0.01	/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.4165132312
95.33	0.02	94.72	0.00	92.81	0.12	94.34	0.00			94.25	0.00	97.41	0.00	98.48	0.00	/workspace/coverage/cover_reg_top/6.chip_tl_errors.3522220418
95.35	0.02	94.75	0.03	92.85	0.04	94.34	0.01			94.27	0.02	97.41	0.00	98.48	0.00	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2118154076
95.37	0.02	94.75	0.00	92.95	0.10	94.34	0.00			94.27	0.00	97.41	0.00	98.48	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.3512508438
95.38	0.02	94.77	0.02	92.95	0.00	94.41	0.06			94.29	0.02	97.41	0.00	98.48	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1126043069
95.40	0.02	94.77	0.00	92.95	0.00	94.50	0.09			94.29	0.00	97.41	0.00	98.48	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.372876038
95.42	0.01	94.77	0.00	93.03	0.07	94.50	0.00			94.31	0.02	97.41	0.00	98.48	0.00	/workspace/coverage/cover_reg_top/86.xbar_stress_all.1633616555
95.43	0.01	94.78	0.01	93.04	0.01	94.57	0.06			94.31	0.00	97.41	0.00	98.48	0.00	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1586668006
95.44	0.01	94.78	0.01	93.08	0.04	94.60	0.03			94.31	0.01	97.41	0.00	98.48	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1738446863
95.46	0.01	94.78	0.00	93.09	0.01	94.60	0.00			94.31	0.00	97.41	0.00	98.55	0.07	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.1724234868
95.47	0.01	94.78	0.01	93.10	0.01	94.63	0.03			94.32	0.01	97.41	0.00	98.57	0.01	/workspace/coverage/default/88.chip_sw_all_escalation_resets.3825993876
95.48	0.01	94.78	0.00	93.16	0.06	94.63	0.00			94.32	0.00	97.41	0.00	98.57	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.1998138764
95.49	0.01	94.78	0.00	93.23	0.06	94.63	0.00			94.32	0.00	97.41	0.00	98.57	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1835580972
95.50	0.01	94.78	0.00	93.23	0.00	94.69	0.06			94.32	0.00	97.41	0.00	98.57	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2142884674
95.51	0.01	94.81	0.03	93.24	0.01	94.69	0.00			94.34	0.02	97.41	0.00	98.57	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2332106215
95.52	0.01	94.82	0.01	93.26	0.02	94.71	0.02			94.34	0.00	97.41	0.00	98.57	0.00	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.555866194
95.53	0.01	94.84	0.02	93.27	0.01	94.72	0.01			94.36	0.02	97.41	0.00	98.57	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3070884553
95.53	0.01	94.84	0.00	93.32	0.05	94.72	0.00			94.36	0.00	97.41	0.00	98.57	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.3626589113
95.54	0.01	94.84	0.00	93.32	0.01	94.72	0.00			94.36	0.00	97.41	0.00	98.61	0.05	/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.2708012673
95.55	0.01	94.84	0.00	93.32	0.00	94.72	0.00			94.36	0.00	97.41	0.00	98.66	0.05	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.363017531
95.56	0.01	94.84	0.00	93.34	0.01	94.72	0.00			94.36	0.00	97.41	0.00	98.70	0.04	/workspace/coverage/cover_reg_top/74.xbar_access_same_device.1168322741
95.57	0.01	94.84	0.00	93.37	0.03	94.72	0.00			94.36	0.00	97.41	0.00	98.71	0.01	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.3799948534
95.57	0.01	94.84	0.00	93.41	0.04	94.72	0.00			94.36	0.00	97.41	0.00	98.71	0.00	/workspace/coverage/cover_reg_top/3.chip_tl_errors.1539868057
95.58	0.01	94.84	0.00	93.45	0.04	94.72	0.00			94.36	0.00	97.41	0.00	98.71	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.4179071253
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95.81	0.01	94.91	0.00	93.71	0.00	94.95	0.00			94.36	0.00	97.41	0.00	99.49	0.01	/workspace/coverage/default/78.chip_sw_all_escalation_resets.1911420491
95.81	0.01	94.91	0.00	93.71	0.00	94.95	0.00			94.36	0.00	97.41	0.00	99.51	0.01	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1268473281
95.81	0.01	94.91	0.00	93.71	0.00	94.95	0.00			94.36	0.00	97.41	0.00	99.52	0.01	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1251513679
95.81	0.01	94.91	0.00	93.71	0.00	94.95	0.00			94.36	0.00	97.41	0.00	99.53	0.01	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3920749482
95.81	0.01	94.91	0.00	93.71	0.00	94.95	0.00			94.36	0.00	97.41	0.00	99.54	0.01	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1547892992
95.82	0.01	94.91	0.00	93.71	0.00	94.95	0.00			94.36	0.00	97.41	0.00	99.55	0.01	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1121770771
95.82	0.01	94.91	0.00	93.71	0.00	94.95	0.00			94.36	0.00	97.41	0.00	99.57	0.01	/workspace/coverage/default/89.chip_sw_all_escalation_resets.4013036346
95.82	0.01	94.91	0.00	93.71	0.00	94.95	0.00			94.36	0.00	97.41	0.00	99.58	0.01	/workspace/coverage/default/94.chip_sw_all_escalation_resets.366581074
95.82	0.01	94.91	0.00	93.72	0.01	94.95	0.00			94.36	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/19.chip_tl_errors.1449232375
95.82	0.01	94.91	0.00	93.73	0.01	94.95	0.00			94.36	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.2406505356
95.83	0.01	94.91	0.00	93.75	0.01	94.95	0.00			94.36	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sival_flash_info_access.1629293190
95.83	0.01	94.91	0.00	93.76	0.01	94.95	0.00			94.36	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.341572239
95.83	0.01	94.91	0.00	93.77	0.01	94.95	0.00			94.36	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3425108961
95.83	0.01	94.91	0.01	93.77	0.00	94.96	0.01			94.36	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/67.chip_sw_all_escalation_resets.1377986601
95.83	0.01	94.91	0.00	93.77	0.00	94.97	0.01			94.36	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.4118445121
95.83	0.01	94.91	0.00	93.77	0.00	94.98	0.01			94.36	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3930655719
95.84	0.01	94.91	0.00	93.77	0.00	94.99	0.01			94.36	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2085206219
95.84	0.01	94.91	0.00	93.77	0.00	94.99	0.00			94.36	0.01	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3829532203
95.84	0.01	94.91	0.00	93.77	0.00	94.99	0.00			94.37	0.01	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4257497054
95.84	0.01	94.91	0.00	93.77	0.00	94.99	0.00			94.38	0.01	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_tap_straps_dev.4131393342
95.84	0.01	94.91	0.00	93.77	0.01	94.99	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/0.xbar_stress_all.1448249571
95.84	0.01	94.91	0.00	93.78	0.01	94.99	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/15.xbar_random.764085000
95.84	0.01	94.91	0.00	93.79	0.01	94.99	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/2.chip_tl_errors.156381008
95.84	0.01	94.91	0.00	93.80	0.01	94.99	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1147521719
95.85	0.01	94.91	0.00	93.80	0.01	94.99	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_gpio.776929862
95.85	0.01	94.91	0.00	93.81	0.01	94.99	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1849901665
95.85	0.01	94.92	0.01	93.81	0.00	94.99	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.563228030
95.85	0.01	94.92	0.00	93.81	0.00	95.00	0.01			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.2009044472
95.85	0.01	94.92	0.00	93.81	0.00	95.00	0.01			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4263908899
95.85	0.01	94.92	0.00	93.81	0.00	95.01	0.01			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.913997612
95.85	0.01	94.92	0.00	93.81	0.00	95.01	0.01			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1789337341
95.85	0.01	94.92	0.00	93.81	0.00	95.02	0.01			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3210284291
95.85	0.01	94.92	0.00	93.81	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1681797732
95.85	0.01	94.92	0.00	93.82	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.132489530
95.85	0.01	94.92	0.00	93.82	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.2713579531
95.85	0.01	94.92	0.00	93.83	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3706411784
95.86	0.01	94.92	0.00	93.83	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.2511547259
95.86	0.01	94.92	0.00	93.83	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.2865312718
95.86	0.01	94.92	0.00	93.84	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.994883129
95.86	0.01	94.92	0.00	93.84	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.2232367003
95.86	0.01	94.92	0.00	93.84	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.2034167862
95.86	0.01	94.92	0.00	93.85	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.904540546
95.86	0.01	94.92	0.00	93.85	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.4076725813
95.86	0.01	94.92	0.00	93.85	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.1920377264
95.86	0.01	94.92	0.00	93.86	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.1113386493
95.86	0.01	94.92	0.00	93.86	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.2017337172
95.86	0.01	94.92	0.00	93.87	0.01	95.02	0.00			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3881789030
95.86	0.01	94.92	0.00	93.87	0.00	95.02	0.01			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/1.chip_tap_straps_testunlock0.1319478743
95.86	0.01	94.92	0.00	93.87	0.00	95.02	0.01			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.3128830502
95.86	0.01	94.92	0.00	93.87	0.00	95.03	0.01			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_auto_mode.1602934331
95.86	0.01	94.92	0.00	93.87	0.00	95.03	0.01			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.944799383
95.86	0.01	94.92	0.00	93.87	0.00	95.03	0.01			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3621371876
95.86	0.01	94.92	0.00	93.87	0.00	95.03	0.01			94.38	0.00	97.41	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2738375794

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1127603722
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.458071592
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1458619045
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.4117066612
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2192357840
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2359967099
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1426008795
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.671990289
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3947019685
/workspace/coverage/cover_reg_top/0.xbar_error_random.3759441989
/workspace/coverage/cover_reg_top/0.xbar_random.1744836249
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.450091173
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3328824856
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2590842291
/workspace/coverage/cover_reg_top/0.xbar_same_source.1761530238
/workspace/coverage/cover_reg_top/0.xbar_smoke.3887480914
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2797966287
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.192435547
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1327303028
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.876526161
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2409575466
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3788013585
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3054028741
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.4026805024
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2028971718
/workspace/coverage/cover_reg_top/1.chip_csr_rw.1746626231
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.674498753
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1349513097
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1149888592
/workspace/coverage/cover_reg_top/1.chip_tl_errors.864409499
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.3870240034
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.641404090
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.4033908327
/workspace/coverage/cover_reg_top/1.xbar_error_random.352322715
/workspace/coverage/cover_reg_top/1.xbar_random.1216619060
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.3255649502
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3951636497
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.2371493221
/workspace/coverage/cover_reg_top/1.xbar_same_source.2492895570
/workspace/coverage/cover_reg_top/1.xbar_smoke.2339072296
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3246530531
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.764876918
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.568011827
/workspace/coverage/cover_reg_top/1.xbar_stress_all.3624525441
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1741939069
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.703638774
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.640270238
/workspace/coverage/cover_reg_top/10.chip_csr_rw.1950412177
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1084148243
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.604042813
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2105036959
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1049979272
/workspace/coverage/cover_reg_top/10.xbar_error_random.1813068119
/workspace/coverage/cover_reg_top/10.xbar_random.3226373810
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2603664352
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.67434034
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.232494335
/workspace/coverage/cover_reg_top/10.xbar_same_source.1566826076
/workspace/coverage/cover_reg_top/10.xbar_smoke.1937054711
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.981894637
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3565544977
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.735328567
/workspace/coverage/cover_reg_top/10.xbar_stress_all.4121898183
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1060789301
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.311751242
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2828779726
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3665249624
/workspace/coverage/cover_reg_top/11.chip_csr_rw.724356449
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2150316835
/workspace/coverage/cover_reg_top/11.chip_tl_errors.209779874
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.80340995
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1923272301
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3990148009
/workspace/coverage/cover_reg_top/11.xbar_error_random.511219994
/workspace/coverage/cover_reg_top/11.xbar_random.939374423
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.1268280836
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1934216543
/workspace/coverage/cover_reg_top/11.xbar_same_source.2313872363
/workspace/coverage/cover_reg_top/11.xbar_smoke.3562495359
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1209370781
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.1871059462
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3422011833
/workspace/coverage/cover_reg_top/11.xbar_stress_all.1251877639
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.258358716
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3003982511
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3493146480
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1091177849
/workspace/coverage/cover_reg_top/12.chip_csr_rw.988951150
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3147496120
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.1492937778
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3935656466
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.966199041
/workspace/coverage/cover_reg_top/12.xbar_error_random.3745518378
/workspace/coverage/cover_reg_top/12.xbar_random.2870046437
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2813394582
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2740383648
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2608766881
/workspace/coverage/cover_reg_top/12.xbar_same_source.3358631450
/workspace/coverage/cover_reg_top/12.xbar_smoke.2779957460
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1173158
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.695625361
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2824543580
/workspace/coverage/cover_reg_top/12.xbar_stress_all.868365791
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1026527491
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2631514315
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3170105013
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2507386888
/workspace/coverage/cover_reg_top/13.chip_csr_rw.2840179339
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3949108223
/workspace/coverage/cover_reg_top/13.chip_tl_errors.136810874
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/workspace/coverage/default/2.rom_e2e_asm_init_rma.1233927775
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2748913119
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3733234623
/workspace/coverage/default/2.rom_e2e_smoke.2297092789
/workspace/coverage/default/2.rom_e2e_static_critical.1835584447
/workspace/coverage/default/2.rom_keymgr_functest.1447836906
/workspace/coverage/default/2.rom_raw_unlock.2146388125
/workspace/coverage/default/2.rom_volatile_raw_unlock.3374326639
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1205161227
/workspace/coverage/default/24.chip_sw_all_escalation_resets.967753680
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.774994790
/workspace/coverage/default/29.chip_sw_all_escalation_resets.85236705
/workspace/coverage/default/3.chip_sw_all_escalation_resets.731682780
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4036913439
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.1412848485
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3968408987
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2409930588
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3338745782
/workspace/coverage/default/3.chip_sw_uart_tx_rx.1464423238
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.158592306
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2496082310
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3988009979
/workspace/coverage/default/3.chip_tap_straps_dev.219493101
/workspace/coverage/default/3.chip_tap_straps_prod.1062330450
/workspace/coverage/default/3.chip_tap_straps_rma.2356227418
/workspace/coverage/default/3.chip_tap_straps_testunlock0.3941840334
/workspace/coverage/default/30.chip_sw_all_escalation_resets.2345409555
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3000608092
/workspace/coverage/default/32.chip_sw_all_escalation_resets.3247475576
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.36859140
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2333353369
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.654416586
/workspace/coverage/default/36.chip_sw_all_escalation_resets.3481637932
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.834010082
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1309671802
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2931451751
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3485620500
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1732996418
/workspace/coverage/default/4.chip_sw_uart_tx_rx.2036108923
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1698037793
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3644236512
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.893184067
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.201579001
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2323419436
/workspace/coverage/default/4.chip_tap_straps_dev.1502289197
/workspace/coverage/default/4.chip_tap_straps_prod.163783362
/workspace/coverage/default/4.chip_tap_straps_rma.212911756
/workspace/coverage/default/4.chip_tap_straps_testunlock0.721136173
/workspace/coverage/default/40.chip_sw_all_escalation_resets.428330065
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1304431414
/workspace/coverage/default/41.chip_sw_all_escalation_resets.2200256688
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3826549317
/workspace/coverage/default/42.chip_sw_all_escalation_resets.488435841
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.110137014
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2129507221
/workspace/coverage/default/44.chip_sw_all_escalation_resets.1544590739
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2912264236
/workspace/coverage/default/45.chip_sw_all_escalation_resets.4260721820
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3830193232
/workspace/coverage/default/46.chip_sw_all_escalation_resets.3787275581
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.691474431
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1062212294
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4259429659
/workspace/coverage/default/5.chip_sw_all_escalation_resets.724018574
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.806450079
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1461986008
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.800856252
/workspace/coverage/default/51.chip_sw_all_escalation_resets.1486582246
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1418630376
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3749552940
/workspace/coverage/default/53.chip_sw_all_escalation_resets.2186627069
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2994899334
/workspace/coverage/default/54.chip_sw_all_escalation_resets.89488655
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1422389632
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1383501930
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.396205299
/workspace/coverage/default/57.chip_sw_all_escalation_resets.967332933
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2128882525
/workspace/coverage/default/58.chip_sw_all_escalation_resets.1829214467
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.703928122
/workspace/coverage/default/59.chip_sw_all_escalation_resets.2718695716
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2696626798
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.4250855091
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1527446204
/workspace/coverage/default/60.chip_sw_all_escalation_resets.3526919137
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2834280790
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2514587710
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1055519219
/workspace/coverage/default/62.chip_sw_all_escalation_resets.3601007815
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2382491429
/workspace/coverage/default/63.chip_sw_all_escalation_resets.2651566307
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.4134650088
/workspace/coverage/default/64.chip_sw_all_escalation_resets.415035547
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2500194475
/workspace/coverage/default/65.chip_sw_all_escalation_resets.822637961
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.60418085
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1574870731
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.966516522
/workspace/coverage/default/68.chip_sw_all_escalation_resets.2434770399
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3041477431
/workspace/coverage/default/69.chip_sw_all_escalation_resets.839222373
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1657669463
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.794772162
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3141774044
/workspace/coverage/default/70.chip_sw_all_escalation_resets.3507472281
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3196370158
/workspace/coverage/default/71.chip_sw_all_escalation_resets.975757845
/workspace/coverage/default/73.chip_sw_all_escalation_resets.2950199589
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2871398281
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1491377778
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3218488688
/workspace/coverage/default/75.chip_sw_all_escalation_resets.3779618090
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3159409246
/workspace/coverage/default/76.chip_sw_all_escalation_resets.3236840213
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.4262292482
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1729292232
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3416249255
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2885062125
/workspace/coverage/default/8.chip_sw_all_escalation_resets.1231999883
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.822995192
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1224393262
/workspace/coverage/default/80.chip_sw_all_escalation_resets.3064628687
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2646896895
/workspace/coverage/default/81.chip_sw_all_escalation_resets.911912731
/workspace/coverage/default/82.chip_sw_all_escalation_resets.2122939464
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.4077393849
/workspace/coverage/default/83.chip_sw_all_escalation_resets.944322454
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2145823085
/workspace/coverage/default/84.chip_sw_all_escalation_resets.214030943
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2446584709
/workspace/coverage/default/85.chip_sw_all_escalation_resets.658701423
/workspace/coverage/default/86.chip_sw_all_escalation_resets.3946944262
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1095177540
/workspace/coverage/default/87.chip_sw_all_escalation_resets.1685217572
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2423166561
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3092969630
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3212753797
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2973349213
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2405359565
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3153020041
/workspace/coverage/default/92.chip_sw_all_escalation_resets.259002526
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2428533428
/workspace/coverage/default/95.chip_sw_all_escalation_resets.1655930149
/workspace/coverage/default/96.chip_sw_all_escalation_resets.183921475
/workspace/coverage/default/97.chip_sw_all_escalation_resets.812867741
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3424506498
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1326318580
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2616439514
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3679707752
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.4191449569
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2807063221
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3052382136
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1122535553
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.310084877
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.707612958

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Total test records in report: 2847

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/10.chip_sw_all_escalation_resets.2209380237			Feb 29 04:02:23 PM PST 24	Feb 29 04:14:14 PM PST 24	5901002492 ps
T2	/workspace/coverage/default/14.chip_sw_all_escalation_resets.4180674624			Feb 29 04:01:46 PM PST 24	Feb 29 04:15:59 PM PST 24	6367766530 ps
T3	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1956884025			Feb 29 03:59:58 PM PST 24	Feb 29 04:12:17 PM PST 24	5234185320 ps
T39	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1815716457			Feb 29 03:39:11 PM PST 24	Feb 29 04:44:28 PM PST 24	11846118008 ps
T79	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2448514328			Feb 29 03:49:56 PM PST 24	Feb 29 03:55:55 PM PST 24	2829358762 ps
T80	/workspace/coverage/default/56.chip_sw_all_escalation_resets.3535028213			Feb 29 04:05:56 PM PST 24	Feb 29 04:19:28 PM PST 24	5814530380 ps
T55	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3621052819			Feb 29 03:55:15 PM PST 24	Feb 29 04:09:05 PM PST 24	8014532660 ps
T4	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.183924774			Feb 29 03:29:33 PM PST 24	Feb 29 03:36:52 PM PST 24	9766458820 ps
T81	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1851622386			Feb 29 03:49:41 PM PST 24	Feb 29 04:01:55 PM PST 24	4684607288 ps
T10	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1792694445			Feb 29 03:27:29 PM PST 24	Feb 29 03:34:54 PM PST 24	3850275467 ps
T135	/workspace/coverage/default/88.chip_sw_all_escalation_resets.3825993876			Feb 29 04:09:16 PM PST 24	Feb 29 04:22:34 PM PST 24	4546667298 ps
T130	/workspace/coverage/default/1.chip_sival_flash_info_access.3418297011			Feb 29 03:38:18 PM PST 24	Feb 29 03:46:08 PM PST 24	3785838558 ps
T5	/workspace/coverage/default/2.chip_jtag_mem_access.2787845885			Feb 29 03:48:59 PM PST 24	Feb 29 04:17:04 PM PST 24	13233816232 ps
T40	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2850854351			Feb 29 03:40:15 PM PST 24	Feb 29 04:25:15 PM PST 24	9754554188 ps
T6	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.98146909			Feb 29 04:00:41 PM PST 24	Feb 29 04:19:01 PM PST 24	13111443585 ps
T880	/workspace/coverage/default/1.chip_sw_example_manufacturer.2382489510			Feb 29 03:37:55 PM PST 24	Feb 29 03:40:44 PM PST 24	2739819156 ps
T41	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2748913119			Feb 29 04:02:49 PM PST 24	Feb 29 04:28:53 PM PST 24	6801510692 ps
T141	/workspace/coverage/default/0.rom_e2e_static_critical.2857917200			Feb 29 03:38:43 PM PST 24	Feb 29 04:31:58 PM PST 24	10835155536 ps
T115	/workspace/coverage/default/0.chip_sw_power_idle_load.2890838329			Feb 29 03:31:59 PM PST 24	Feb 29 03:42:12 PM PST 24	4492822986 ps
T116	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3361118504			Feb 29 03:54:07 PM PST 24	Feb 29 04:59:50 PM PST 24	11228189740 ps
T16	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1804024697			Feb 29 03:30:09 PM PST 24	Feb 29 03:51:02 PM PST 24	18272855500 ps
T99	/workspace/coverage/default/66.chip_sw_all_escalation_resets.3781749796			Feb 29 04:11:07 PM PST 24	Feb 29 04:22:37 PM PST 24	6127235080 ps
T100	/workspace/coverage/default/70.chip_sw_all_escalation_resets.3507472281			Feb 29 04:07:30 PM PST 24	Feb 29 04:19:55 PM PST 24	5265609898 ps
T101	/workspace/coverage/default/1.chip_sw_aes_enc.3320509787			Feb 29 03:41:36 PM PST 24	Feb 29 03:46:08 PM PST 24	3206523436 ps
T102	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2030046017			Feb 29 03:56:55 PM PST 24	Feb 29 04:28:43 PM PST 24	22422039867 ps
T103	/workspace/coverage/default/1.chip_sw_edn_boot_mode.3752287648			Feb 29 03:42:51 PM PST 24	Feb 29 03:51:58 PM PST 24	3166588312 ps
T104	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3362373411			Feb 29 03:31:43 PM PST 24	Feb 29 03:39:12 PM PST 24	4144690492 ps
T105	/workspace/coverage/default/2.chip_sw_example_flash.1012903433			Feb 29 03:49:26 PM PST 24	Feb 29 03:53:36 PM PST 24	2634870212 ps
T106	/workspace/coverage/default/0.chip_sw_rv_timer_irq.3773574951			Feb 29 03:28:17 PM PST 24	Feb 29 03:31:12 PM PST 24	2286635304 ps
T107	/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1104503717			Feb 29 03:50:24 PM PST 24	Feb 29 03:55:34 PM PST 24	3362267672 ps
T182	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.415464285			Feb 29 03:59:34 PM PST 24	Feb 29 04:07:50 PM PST 24	3736503750 ps
T161	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.767329731			Feb 29 03:37:47 PM PST 24	Feb 29 03:43:58 PM PST 24	3293106160 ps
T393	/workspace/coverage/default/0.chip_sw_kmac_entropy.3673217579			Feb 29 03:28:54 PM PST 24	Feb 29 03:32:11 PM PST 24	2546791264 ps
T134	/workspace/coverage/default/1.chip_sw_flash_init.2827430495			Feb 29 03:38:41 PM PST 24	Feb 29 04:17:16 PM PST 24	22514707574 ps
T394	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.3331511371			Feb 29 03:46:05 PM PST 24	Feb 29 03:51:43 PM PST 24	3278116950 ps
T209	/workspace/coverage/default/43.chip_sw_all_escalation_resets.2113455382			Feb 29 04:09:50 PM PST 24	Feb 29 04:21:27 PM PST 24	6028425752 ps
T56	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1119239937			Feb 29 03:52:18 PM PST 24	Feb 29 04:27:15 PM PST 24	22916128210 ps
T289	/workspace/coverage/default/2.chip_sw_hmac_enc.79904584			Feb 29 03:53:32 PM PST 24	Feb 29 03:58:12 PM PST 24	3353498762 ps
T136	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.717851839			Feb 29 03:31:50 PM PST 24	Feb 29 04:07:45 PM PST 24	26042770476 ps
T238	/workspace/coverage/default/0.chip_sw_aon_timer_irq.1437927180			Feb 29 03:29:54 PM PST 24	Feb 29 03:37:59 PM PST 24	4484880428 ps
T223	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.1412848485			Feb 29 04:00:33 PM PST 24	Feb 29 04:12:06 PM PST 24	5760440504 ps
T154	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1586668006			Feb 29 03:59:47 PM PST 24	Feb 29 04:43:13 PM PST 24	13659885614 ps
T58	/workspace/coverage/default/0.rom_volatile_raw_unlock.3156348580			Feb 29 03:38:08 PM PST 24	Feb 29 03:40:14 PM PST 24	2414159505 ps
T650	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2657814384			Feb 29 03:53:26 PM PST 24	Feb 29 03:56:34 PM PST 24	2837908448 ps
T479	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3159409246			Feb 29 04:08:04 PM PST 24	Feb 29 04:15:46 PM PST 24	3476410600 ps
T124	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2252256605			Feb 29 03:42:00 PM PST 24	Feb 29 03:53:42 PM PST 24	7571456100 ps
T36	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3055618688			Feb 29 03:38:54 PM PST 24	Feb 29 04:08:30 PM PST 24	8707365250 ps
T234	/workspace/coverage/default/2.chip_sw_plic_sw_irq.3333839677			Feb 29 03:56:11 PM PST 24	Feb 29 03:59:24 PM PST 24	2487583174 ps
T62	/workspace/coverage/default/4.chip_tap_straps_testunlock0.721136173			Feb 29 03:59:23 PM PST 24	Feb 29 04:03:25 PM PST 24	3260337333 ps
T346	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1321739007			Feb 29 03:37:47 PM PST 24	Feb 29 04:16:28 PM PST 24	8806622920 ps
T171	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1263169710			Feb 29 03:51:02 PM PST 24	Feb 29 07:24:50 PM PST 24	78409377400 ps
T159	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.1850472814			Feb 29 03:28:25 PM PST 24	Feb 29 03:53:48 PM PST 24	6894722184 ps
T13	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3253982862			Feb 29 03:34:32 PM PST 24	Feb 29 04:28:00 PM PST 24	14022786960 ps
T676	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.281720782			Feb 29 03:41:13 PM PST 24	Feb 29 03:48:35 PM PST 24	6036122260 ps
T179	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2118154076			Feb 29 03:37:45 PM PST 24	Feb 29 04:53:04 PM PST 24	23397501716 ps
T128	/workspace/coverage/default/49.chip_sw_all_escalation_resets.3217786509			Feb 29 04:04:32 PM PST 24	Feb 29 04:16:38 PM PST 24	5179878850 ps
T480	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2871398281			Feb 29 04:13:05 PM PST 24	Feb 29 04:20:03 PM PST 24	3818354360 ps
T671	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1574870731			Feb 29 04:07:13 PM PST 24	Feb 29 04:12:43 PM PST 24	3423748764 ps
T63	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.302304795			Feb 29 03:50:37 PM PST 24	Feb 29 03:58:37 PM PST 24	4314503804 ps
T37	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.401560986			Feb 29 03:41:40 PM PST 24	Feb 29 04:39:29 PM PST 24	12204265540 ps
T38	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2683545638			Feb 29 03:38:08 PM PST 24	Feb 29 04:11:43 PM PST 24	8652507838 ps
T721	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1812482985			Feb 29 03:42:00 PM PST 24	Feb 29 03:56:51 PM PST 24	8179964642 ps
T204	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3445175931			Feb 29 03:53:08 PM PST 24	Feb 29 04:27:52 PM PST 24	9547576616 ps
T881	/workspace/coverage/default/0.chip_sw_coremark.2627634806			Feb 29 03:28:34 PM PST 24	Feb 29 06:21:14 PM PST 24	50345486884 ps
T117	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.4197937645			Feb 29 03:44:01 PM PST 24	Feb 29 03:52:14 PM PST 24	4426000220 ps
T783	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2828550974			Feb 29 04:09:35 PM PST 24	Feb 29 04:14:40 PM PST 24	4045405226 ps
T882	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.59367407			Feb 29 03:26:52 PM PST 24	Feb 29 03:36:11 PM PST 24	6458774722 ps
T147	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4044649034			Feb 29 03:52:26 PM PST 24	Feb 29 04:00:03 PM PST 24	18842603980 ps
T883	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3573309823			Feb 29 03:45:56 PM PST 24	Feb 29 04:07:15 PM PST 24	5936053832 ps
T373	/workspace/coverage/default/2.chip_sw_all_escalation_resets.3867326050			Feb 29 03:49:43 PM PST 24	Feb 29 04:01:09 PM PST 24	5740190304 ps
T202	/workspace/coverage/default/84.chip_sw_all_escalation_resets.214030943			Feb 29 04:08:35 PM PST 24	Feb 29 04:18:22 PM PST 24	4945392912 ps
T677	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3000608092			Feb 29 04:04:26 PM PST 24	Feb 29 04:11:24 PM PST 24	3938719314 ps
T347	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1592561096			Feb 29 04:02:55 PM PST 24	Feb 29 04:37:59 PM PST 24	9023598368 ps
T672	/workspace/coverage/default/97.chip_sw_all_escalation_resets.812867741			Feb 29 04:09:49 PM PST 24	Feb 29 04:21:03 PM PST 24	4519797924 ps
T787	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1533202342			Feb 29 04:09:05 PM PST 24	Feb 29 04:16:52 PM PST 24	3716781720 ps
T210	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1789337341			Feb 29 03:33:21 PM PST 24	Feb 29 03:44:05 PM PST 24	5311669330 ps
T884	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3445665312			Feb 29 03:35:30 PM PST 24	Feb 29 03:39:13 PM PST 24	2027434116 ps
T180	/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2973349213			Feb 29 04:00:08 PM PST 24	Feb 29 04:12:25 PM PST 24	4122987860 ps
T305	/workspace/coverage/default/9.chip_sw_all_escalation_resets.3092969630			Feb 29 04:02:11 PM PST 24	Feb 29 04:13:47 PM PST 24	6033087924 ps
T675	/workspace/coverage/default/60.chip_sw_all_escalation_resets.3526919137			Feb 29 04:09:30 PM PST 24	Feb 29 04:17:35 PM PST 24	5454218200 ps
T14	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1006056616			Feb 29 03:28:42 PM PST 24	Feb 29 03:31:31 PM PST 24	3288370770 ps
T352	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2451742186			Feb 29 03:44:29 PM PST 24	Feb 29 03:55:08 PM PST 24	4382086732 ps
T189	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2852460184			Feb 29 03:34:54 PM PST 24	Feb 29 03:44:29 PM PST 24	4523006044 ps
T131	/workspace/coverage/default/2.rom_e2e_shutdown_output.3506292296			Feb 29 04:01:51 PM PST 24	Feb 29 04:54:52 PM PST 24	27311903696 ps
T212	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.944799383			Feb 29 03:31:04 PM PST 24	Feb 29 03:39:58 PM PST 24	3998633808 ps
T168	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.4044805321			Feb 29 03:28:34 PM PST 24	Feb 29 03:32:02 PM PST 24	2734034811 ps
T353	/workspace/coverage/default/0.chip_sw_example_flash.227909253			Feb 29 03:26:46 PM PST 24	Feb 29 03:30:48 PM PST 24	2697406568 ps
T309	/workspace/coverage/default/96.chip_sw_all_escalation_resets.183921475			Feb 29 04:09:51 PM PST 24	Feb 29 04:20:20 PM PST 24	4407637948 ps
T57	/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2243638869			Feb 29 03:49:43 PM PST 24	Feb 29 04:03:00 PM PST 24	8767697233 ps
T151	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.4027097702			Feb 29 03:53:37 PM PST 24	Feb 29 03:58:53 PM PST 24	3304311085 ps
T129	/workspace/coverage/default/2.rom_volatile_raw_unlock.3374326639			Feb 29 03:59:48 PM PST 24	Feb 29 04:01:49 PM PST 24	2346935282 ps
T224	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.2961166976			Feb 29 03:52:08 PM PST 24	Feb 29 04:00:02 PM PST 24	3416212856 ps
T32	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.555866194			Feb 29 03:51:37 PM PST 24	Feb 29 03:56:54 PM PST 24	2961988276 ps
T144	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1565010365			Feb 29 03:57:17 PM PST 24	Feb 29 04:02:34 PM PST 24	2969687429 ps
T152	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2227030372			Feb 29 03:43:29 PM PST 24	Feb 29 03:49:49 PM PST 24	4772540473 ps
T276	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.966516522			Feb 29 04:07:37 PM PST 24	Feb 29 04:14:33 PM PST 24	3679233024 ps
T254	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1863970311			Feb 29 03:38:51 PM PST 24	Feb 29 04:11:40 PM PST 24	8275687136 ps
T277	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.396205299			Feb 29 04:09:40 PM PST 24	Feb 29 04:17:25 PM PST 24	4158028982 ps
T278	/workspace/coverage/default/38.chip_sw_all_escalation_resets.3055345311			Feb 29 04:04:14 PM PST 24	Feb 29 04:14:14 PM PST 24	3972266728 ps
T123	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1128906841			Feb 29 03:51:27 PM PST 24	Feb 29 04:18:50 PM PST 24	13277798632 ps
T155	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3644236512			Feb 29 04:02:04 PM PST 24	Feb 29 04:13:34 PM PST 24	5225432480 ps
T279	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2475566636			Feb 29 04:02:16 PM PST 24	Feb 29 05:07:53 PM PST 24	23274739660 ps
T280	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1937332506			Feb 29 03:39:10 PM PST 24	Feb 29 04:36:57 PM PST 24	12074016744 ps
T658	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1121770771			Feb 29 04:10:37 PM PST 24	Feb 29 04:17:32 PM PST 24	3462506266 ps
T299	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3621371876			Feb 29 03:28:26 PM PST 24	Feb 29 03:57:14 PM PST 24	13259232032 ps
T108	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.709538169			Feb 29 03:51:44 PM PST 24	Feb 29 05:00:09 PM PST 24	19081577477 ps
T885	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1900387639			Feb 29 03:51:43 PM PST 24	Feb 29 03:59:23 PM PST 24	6500165784 ps
T710	/workspace/coverage/default/0.chip_sw_hmac_smoketest.3016997872			Feb 29 03:36:40 PM PST 24	Feb 29 03:42:54 PM PST 24	3135380550 ps
T306	/workspace/coverage/default/1.chip_sw_all_escalation_resets.608495647			Feb 29 03:37:28 PM PST 24	Feb 29 03:46:57 PM PST 24	4699447590 ps
T403	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.695310232			Feb 29 03:30:06 PM PST 24	Feb 29 03:50:04 PM PST 24	12453186196 ps
T386	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.557531829			Feb 29 03:40:21 PM PST 24	Feb 29 03:43:54 PM PST 24	2609889410 ps
T886	/workspace/coverage/default/4.chip_sw_uart_tx_rx.2036108923			Feb 29 04:00:23 PM PST 24	Feb 29 04:18:42 PM PST 24	4954578310 ps
T145	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.4186023928			Feb 29 03:30:36 PM PST 24	Feb 29 03:34:10 PM PST 24	2309500198 ps
T222	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.556972397			Feb 29 03:31:59 PM PST 24	Feb 29 03:53:52 PM PST 24	5609273360 ps
T328	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2500194475			Feb 29 04:11:42 PM PST 24	Feb 29 04:17:32 PM PST 24	3695408664 ps
T340	/workspace/coverage/default/2.rom_e2e_asm_init_prod.3147053618			Feb 29 04:01:24 PM PST 24	Feb 29 04:35:30 PM PST 24	8385041047 ps
T341	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.192239734			Feb 29 03:41:57 PM PST 24	Feb 29 04:25:02 PM PST 24	8367450990 ps
T11	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1999980876			Feb 29 03:27:37 PM PST 24	Feb 29 03:31:28 PM PST 24	2402664940 ps
T160	/workspace/coverage/default/0.chip_sw_edn_kat.3488585433			Feb 29 03:28:53 PM PST 24	Feb 29 03:39:54 PM PST 24	3523925812 ps
T33	/workspace/coverage/default/2.chip_sw_spi_device_tpm.159393542			Feb 29 03:49:52 PM PST 24	Feb 29 03:55:12 PM PST 24	3875838248 ps
T310	/workspace/coverage/default/48.chip_sw_all_escalation_resets.3786525970			Feb 29 04:04:29 PM PST 24	Feb 29 04:15:28 PM PST 24	5504602080 ps
T215	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.3778615096			Feb 29 03:43:46 PM PST 24	Feb 29 04:36:34 PM PST 24	10781252220 ps
T178	/workspace/coverage/default/1.rom_volatile_raw_unlock.945900765			Feb 29 03:48:04 PM PST 24	Feb 29 03:49:51 PM PST 24	2513680164 ps
T308	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.4171361398			Feb 29 03:47:10 PM PST 24	Feb 29 03:53:23 PM PST 24	3442252049 ps
T774	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2696626798			Feb 29 04:02:18 PM PST 24	Feb 29 04:10:04 PM PST 24	3337323476 ps
T75	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3887171296			Feb 29 03:54:18 PM PST 24	Feb 29 04:16:09 PM PST 24	11822358624 ps
T300	/workspace/coverage/default/36.chip_sw_all_escalation_resets.3481637932			Feb 29 04:03:23 PM PST 24	Feb 29 04:13:50 PM PST 24	6089235312 ps
T887	/workspace/coverage/default/3.chip_sw_uart_tx_rx.1464423238			Feb 29 03:59:35 PM PST 24	Feb 29 04:17:44 PM PST 24	4680017792 ps
T298	/workspace/coverage/default/2.chip_sw_otbn_randomness.1991809674			Feb 29 03:52:56 PM PST 24	Feb 29 04:08:07 PM PST 24	6041554558 ps
T203	/workspace/coverage/default/11.chip_sw_all_escalation_resets.2839527390			Feb 29 04:02:19 PM PST 24	Feb 29 04:11:22 PM PST 24	4335254764 ps
T156	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.554501349			Feb 29 03:30:22 PM PST 24	Feb 29 03:38:50 PM PST 24	4560910892 ps
T678	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2040517463			Feb 29 03:50:07 PM PST 24	Feb 29 04:00:13 PM PST 24	5319531896 ps
T888	/workspace/coverage/default/2.chip_sw_aes_smoketest.329672517			Feb 29 03:58:12 PM PST 24	Feb 29 04:02:51 PM PST 24	3371127112 ps
T342	/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3643605116			Feb 29 03:39:52 PM PST 24	Feb 29 03:42:44 PM PST 24	2901462818 ps
T122	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3050119605			Feb 29 03:28:04 PM PST 24	Feb 29 03:38:26 PM PST 24	5415999696 ps
T374	/workspace/coverage/default/21.chip_sw_all_escalation_resets.322437556			Feb 29 04:05:41 PM PST 24	Feb 29 04:17:08 PM PST 24	4531233126 ps
T290	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1337942706			Feb 29 03:28:00 PM PST 24	Feb 29 03:41:12 PM PST 24	4329108362 ps
T889	/workspace/coverage/default/2.chip_sw_example_rom.3846491196			Feb 29 03:48:26 PM PST 24	Feb 29 03:50:23 PM PST 24	2049778940 ps
T890	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1163904962			Feb 29 03:50:01 PM PST 24	Feb 29 03:59:46 PM PST 24	4160957112 ps
T194	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3417877128			Feb 29 03:30:56 PM PST 24	Feb 29 03:56:16 PM PST 24	8545949688 ps
T891	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3660452817			Feb 29 03:38:41 PM PST 24	Feb 29 03:55:33 PM PST 24	5642442770 ps
T333	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3834692873			Feb 29 04:01:30 PM PST 24	Feb 29 04:07:54 PM PST 24	4140522050 ps
T185	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.1377326857			Feb 29 03:49:24 PM PST 24	Feb 29 07:09:49 PM PST 24	64906632900 ps
T190	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2668042731			Feb 29 03:49:37 PM PST 24	Feb 29 04:02:45 PM PST 24	5836791788 ps
T335	/workspace/coverage/default/0.chip_sw_kmac_smoketest.2427568668			Feb 29 03:37:46 PM PST 24	Feb 29 03:44:29 PM PST 24	3395404216 ps
T146	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1292067256			Feb 29 03:57:35 PM PST 24	Feb 29 04:02:02 PM PST 24	2604057990 ps
T196	/workspace/coverage/default/4.chip_tap_straps_dev.1502289197			Feb 29 03:59:41 PM PST 24	Feb 29 04:03:25 PM PST 24	2866256022 ps
T336	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.844296843			Feb 29 03:40:17 PM PST 24	Feb 29 03:58:18 PM PST 24	14094035495 ps
T200	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1903299253			Feb 29 03:54:37 PM PST 24	Feb 29 04:31:02 PM PST 24	24498375310 ps
T337	/workspace/coverage/default/0.chip_sw_aes_enc.3155016988			Feb 29 03:29:18 PM PST 24	Feb 29 03:33:22 PM PST 24	2444836112 ps
T338	/workspace/coverage/default/0.chip_sw_kmac_idle.823261929			Feb 29 03:28:02 PM PST 24	Feb 29 03:32:04 PM PST 24	2688113220 ps
T255	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2276906797			Feb 29 03:52:19 PM PST 24	Feb 29 03:54:13 PM PST 24	2641103703 ps
T307	/workspace/coverage/default/39.chip_sw_all_escalation_resets.734878277			Feb 29 04:09:03 PM PST 24	Feb 29 04:18:20 PM PST 24	4262345514 ps
T892	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3398856003			Feb 29 03:27:30 PM PST 24	Feb 29 03:45:08 PM PST 24	13348319831 ps
T893	/workspace/coverage/default/1.chip_sw_flash_crash_alert.1492660495			Feb 29 03:46:21 PM PST 24	Feb 29 03:58:01 PM PST 24	4608818362 ps
T175	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3968408987			Feb 29 03:59:08 PM PST 24	Feb 29 04:15:12 PM PST 24	11025874084 ps
T12	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2011100969			Feb 29 03:42:09 PM PST 24	Feb 29 03:46:08 PM PST 24	3204836964 ps
T894	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2460470127			Feb 29 03:40:00 PM PST 24	Feb 29 03:53:06 PM PST 24	4161647020 ps
T256	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2910134720			Feb 29 03:46:48 PM PST 24	Feb 29 03:56:01 PM PST 24	9268512405 ps
T804	/workspace/coverage/default/64.chip_sw_all_escalation_resets.415035547			Feb 29 04:09:27 PM PST 24	Feb 29 04:18:13 PM PST 24	5115485906 ps
T225	/workspace/coverage/default/0.chip_sw_all_escalation_resets.1360667529			Feb 29 03:26:52 PM PST 24	Feb 29 03:36:58 PM PST 24	5138427014 ps
T186	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3568141822			Feb 29 03:54:02 PM PST 24	Feb 29 04:04:21 PM PST 24	4254311630 ps
T247	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2045821233			Feb 29 04:02:13 PM PST 24	Feb 29 04:08:04 PM PST 24	3911097324 ps
T248	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.4263821135			Feb 29 03:51:45 PM PST 24	Feb 29 04:01:06 PM PST 24	5243392980 ps
T249	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.890112746			Feb 29 03:29:22 PM PST 24	Feb 29 03:36:17 PM PST 24	4189276440 ps
T250	/workspace/coverage/default/1.chip_sw_csrng_kat_test.3584222003			Feb 29 03:43:06 PM PST 24	Feb 29 03:47:02 PM PST 24	2327526652 ps
T251	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.14822575			Feb 29 03:44:50 PM PST 24	Feb 29 04:01:01 PM PST 24	7128712496 ps
T132	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3906134935			Feb 29 03:27:09 PM PST 24	Feb 29 05:00:37 PM PST 24	50409605799 ps
T252	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2244678609			Feb 29 03:44:34 PM PST 24	Feb 29 03:54:52 PM PST 24	4168306184 ps
T253	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3602290500			Feb 29 03:42:13 PM PST 24	Feb 29 03:54:13 PM PST 24	5109007528 ps
T895	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2245313509			Feb 29 03:50:12 PM PST 24	Feb 29 04:35:32 PM PST 24	13949039248 ps
T334	/workspace/coverage/default/50.chip_sw_all_escalation_resets.2973150872			Feb 29 04:05:20 PM PST 24	Feb 29 04:17:38 PM PST 24	4910564752 ps
T896	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.881109308			Feb 29 03:28:05 PM PST 24	Feb 29 03:41:41 PM PST 24	9285687896 ps
T690	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3894768261			Feb 29 03:52:20 PM PST 24	Feb 29 03:56:37 PM PST 24	2999301344 ps
T237	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.3760378799			Feb 29 03:38:19 PM PST 24	Feb 29 03:41:55 PM PST 24	2715271800 ps
T897	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1201282579			Feb 29 03:30:53 PM PST 24	Feb 29 03:36:03 PM PST 24	4183119218 ps
T674	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2912264236			Feb 29 04:04:42 PM PST 24	Feb 29 04:10:22 PM PST 24	3238797100 ps
T898	/workspace/coverage/default/2.rom_keymgr_functest.1447836906			Feb 29 03:59:52 PM PST 24	Feb 29 04:12:15 PM PST 24	5397384376 ps
T257	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1848659279			Feb 29 03:46:49 PM PST 24	Feb 29 03:47:39 PM PST 24	1391768780 ps
T748	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.110137014			Feb 29 04:05:36 PM PST 24	Feb 29 04:12:11 PM PST 24	3525256678 ps
T899	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1088407432			Feb 29 03:55:30 PM PST 24	Feb 29 04:03:35 PM PST 24	4416312870 ps
T148	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2701545646			Feb 29 03:57:56 PM PST 24	Feb 29 05:07:44 PM PST 24	23128906162 ps
T15	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.436653063			Feb 29 04:02:12 PM PST 24	Feb 29 04:18:16 PM PST 24	5534435400 ps
T197	/workspace/coverage/default/4.chip_tap_straps_prod.163783362			Feb 29 03:59:46 PM PST 24	Feb 29 04:02:26 PM PST 24	2644715225 ps
T311	/workspace/coverage/default/80.chip_sw_all_escalation_resets.3064628687			Feb 29 04:07:51 PM PST 24	Feb 29 04:18:05 PM PST 24	4713458100 ps
T673	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3613962127			Feb 29 04:02:42 PM PST 24	Feb 29 04:07:11 PM PST 24	3585196636 ps
T273	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.4190061884			Feb 29 03:45:38 PM PST 24	Feb 29 03:50:57 PM PST 24	2922981800 ps
T187	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.82486445			Feb 29 03:40:56 PM PST 24	Feb 29 03:51:07 PM PST 24	4507087008 ps
T240	/workspace/coverage/default/67.chip_sw_all_escalation_resets.1377986601			Feb 29 04:08:20 PM PST 24	Feb 29 04:17:45 PM PST 24	4875612144 ps
T17	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.561906826			Feb 29 03:55:36 PM PST 24	Feb 29 04:26:08 PM PST 24	21988106280 ps
T317	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1441924849			Feb 29 03:33:10 PM PST 24	Feb 29 03:38:18 PM PST 24	3343437801 ps
T900	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2306152497			Feb 29 03:54:59 PM PST 24	Feb 29 04:01:58 PM PST 24	4577486708 ps
T901	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1375771580			Feb 29 03:54:05 PM PST 24	Feb 29 04:00:48 PM PST 24	3007769915 ps
T18	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3829532203			Feb 29 03:30:50 PM PST 24	Feb 29 03:58:11 PM PST 24	23113372160 ps
T902	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2368736716			Feb 29 03:46:06 PM PST 24	Feb 29 03:50:59 PM PST 24	3472071125 ps
T661	/workspace/coverage/default/54.chip_sw_all_escalation_resets.89488655			Feb 29 04:05:17 PM PST 24	Feb 29 04:15:28 PM PST 24	5243353906 ps
T181	/workspace/coverage/default/2.chip_sw_power_idle_load.1342284126			Feb 29 03:57:21 PM PST 24	Feb 29 04:08:25 PM PST 24	4719259024 ps
T395	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.243352096			Feb 29 03:42:58 PM PST 24	Feb 29 03:54:17 PM PST 24	4361728204 ps
T388	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1595846831			Feb 29 04:00:06 PM PST 24	Feb 29 04:04:54 PM PST 24	2436408878 ps
T258	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2516541702			Feb 29 03:41:46 PM PST 24	Feb 29 04:42:29 PM PST 24	12533874760 ps
T681	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1055519219			Feb 29 04:09:40 PM PST 24	Feb 29 04:15:53 PM PST 24	3422915080 ps
T808	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1525101060			Feb 29 04:02:16 PM PST 24	Feb 29 04:08:26 PM PST 24	4344633704 ps
T76	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.2329185758			Feb 29 03:52:56 PM PST 24	Feb 29 03:59:29 PM PST 24	3647126592 ps
T745	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1154650413			Feb 29 03:44:31 PM PST 24	Feb 29 03:50:32 PM PST 24	3367627378 ps
T903	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3603559178			Feb 29 03:34:31 PM PST 24	Feb 29 03:52:32 PM PST 24	5929707723 ps
T904	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2447605941			Feb 29 04:00:56 PM PST 24	Feb 29 04:40:10 PM PST 24	12769892550 ps
T176	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2237853984			Feb 29 03:56:12 PM PST 24	Feb 29 04:09:24 PM PST 24	12613709755 ps
T282	/workspace/coverage/default/1.chip_plic_all_irqs_0.3233364676			Feb 29 03:44:54 PM PST 24	Feb 29 04:05:14 PM PST 24	6028971096 ps
T744	/workspace/coverage/default/47.chip_sw_all_escalation_resets.3544228174			Feb 29 04:04:47 PM PST 24	Feb 29 04:18:35 PM PST 24	4753822120 ps
T219	/workspace/coverage/default/0.chip_sw_flash_init.1018668702			Feb 29 03:27:59 PM PST 24	Feb 29 03:59:51 PM PST 24	21168386309 ps
T167	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2332106215			Feb 29 03:28:40 PM PST 24	Feb 29 03:34:52 PM PST 24	3673225040 ps
T191	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.158592306			Feb 29 03:59:49 PM PST 24	Feb 29 04:16:47 PM PST 24	6050320172 ps
T274	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1539307188			Feb 29 03:46:12 PM PST 24	Feb 29 03:50:56 PM PST 24	2593112082 ps
T905	/workspace/coverage/default/1.chip_sw_uart_tx_rx.540336551			Feb 29 03:38:49 PM PST 24	Feb 29 03:54:50 PM PST 24	5761356774 ps
T656	/workspace/coverage/default/0.chip_sw_aes_masking_off.977329907			Feb 29 03:30:12 PM PST 24	Feb 29 03:34:57 PM PST 24	2774163023 ps
T906	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1367390390			Feb 29 03:51:14 PM PST 24	Feb 29 03:57:24 PM PST 24	4384995296 ps
T907	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2026365055			Feb 29 03:53:34 PM PST 24	Feb 29 04:03:32 PM PST 24	5101573810 ps
T680	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.693773798			Feb 29 03:31:26 PM PST 24	Feb 29 03:39:53 PM PST 24	4072183442 ps
T908	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1065461491			Feb 29 03:50:30 PM PST 24	Feb 29 03:57:22 PM PST 24	3439879128 ps
T138	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.372876038			Feb 29 03:30:05 PM PST 24	Feb 29 03:32:22 PM PST 24	2403980690 ps
T301	/workspace/coverage/default/81.chip_sw_all_escalation_resets.911912731			Feb 29 04:08:09 PM PST 24	Feb 29 04:20:48 PM PST 24	5459702996 ps
T909	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1833527678			Feb 29 03:38:22 PM PST 24	Feb 29 04:03:52 PM PST 24	7307226610 ps
T910	/workspace/coverage/default/0.chip_sw_aes_idle.2864835122			Feb 29 03:29:26 PM PST 24	Feb 29 03:34:37 PM PST 24	2593219628 ps
T911	/workspace/coverage/default/1.chip_sw_aon_timer_irq.3108764731			Feb 29 03:41:05 PM PST 24	Feb 29 03:47:13 PM PST 24	3930332170 ps
T291	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.672036390			Feb 29 03:45:58 PM PST 24	Feb 29 04:03:22 PM PST 24	5411768113 ps
T126	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1167339750			Feb 29 03:49:45 PM PST 24	Feb 29 03:54:18 PM PST 24	2766164409 ps
T793	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3141774044			Feb 29 04:08:07 PM PST 24	Feb 29 04:16:20 PM PST 24	3306080984 ps
T177	/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.470191510			Feb 29 04:04:33 PM PST 24	Feb 29 04:11:05 PM PST 24	5812016424 ps
T912	/workspace/coverage/default/41.chip_sw_all_escalation_resets.2200256688			Feb 29 04:03:55 PM PST 24	Feb 29 04:15:11 PM PST 24	4610131472 ps
T913	/workspace/coverage/default/2.chip_sw_kmac_idle.2712538418			Feb 29 03:53:52 PM PST 24	Feb 29 03:58:33 PM PST 24	2949559826 ps
T119	/workspace/coverage/default/2.chip_plic_all_irqs_10.4185282296			Feb 29 03:56:01 PM PST 24	Feb 29 04:04:32 PM PST 24	3813969586 ps
T657	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.423165239			Feb 29 04:01:59 PM PST 24	Feb 29 04:09:28 PM PST 24	3218117090 ps
T914	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.104172424			Feb 29 03:40:08 PM PST 24	Feb 29 04:39:48 PM PST 24	12066200145 ps
T915	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.502071949			Feb 29 03:57:31 PM PST 24	Feb 29 04:01:47 PM PST 24	2834685064 ps
T916	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3615638132			Feb 29 03:52:17 PM PST 24	Feb 29 04:01:53 PM PST 24	4529101216 ps
T679	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3610406236			Feb 29 04:02:18 PM PST 24	Feb 29 04:07:44 PM PST 24	3716265420 ps
T917	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2496082310			Feb 29 03:59:16 PM PST 24	Feb 29 04:17:24 PM PST 24	5954967880 ps
T188	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.979783527			Feb 29 03:28:08 PM PST 24	Feb 29 03:37:08 PM PST 24	4966660325 ps
T312	/workspace/coverage/default/15.chip_sw_all_escalation_resets.3079421650			Feb 29 04:03:15 PM PST 24	Feb 29 04:13:33 PM PST 24	4514897080 ps
T162	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3830261364			Feb 29 03:44:30 PM PST 24	Feb 29 04:04:01 PM PST 24	9561494400 ps
T192	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1698037793			Feb 29 04:01:21 PM PST 24	Feb 29 04:14:28 PM PST 24	4696899232 ps
T259	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.3548352333			Feb 29 03:49:51 PM PST 24	Feb 29 04:01:42 PM PST 24	4770065420 ps
T137	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.497209291			Feb 29 03:50:01 PM PST 24	Feb 29 05:16:53 PM PST 24	48479870661 ps
T918	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1011561364			Feb 29 03:50:58 PM PST 24	Feb 29 04:11:07 PM PST 24	13547704095 ps
T761	/workspace/coverage/default/8.chip_sw_all_escalation_resets.1231999883			Feb 29 04:00:47 PM PST 24	Feb 29 04:15:00 PM PST 24	5757778106 ps
T220	/workspace/coverage/default/2.chip_sw_flash_init.908494647			Feb 29 03:49:23 PM PST 24	Feb 29 04:19:10 PM PST 24	18569928148 ps
T919	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3962125199			Feb 29 03:40:29 PM PST 24	Feb 29 03:44:53 PM PST 24	3486109640 ps
T375	/workspace/coverage/default/2.chip_sw_kmac_app_rom.2162841283			Feb 29 03:53:37 PM PST 24	Feb 29 03:58:25 PM PST 24	3217340460 ps
T920	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.285285026			Feb 29 03:51:36 PM PST 24	Feb 29 04:25:36 PM PST 24	8931681413 ps
T78	/workspace/coverage/default/0.chip_sw_usbdev_vbus.1314042186			Feb 29 03:27:38 PM PST 24	Feb 29 03:30:40 PM PST 24	2928530204 ps