Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	143865	1			T69	71		T70	47		T71	6
values[2]	8523	1			T69	6		T485	5		T397	2
values[3]	4182	1			T487	1		T354	2		T486	5
values[4]	2442	1			T487	1		T354	2		T486	4
values[5]	1623	1			T487	1		T354	2		T486	1
values[6]	1133	1			T487	1		T354	2		T486	2
values[7]	925	1			T487	1		T354	2		T486	5
values[8]	779	1			T487	1		T354	2		T486	1
values[9]	665	1			T487	1		T354	2		T486	4
values[10]	624	1			T487	1		T354	2		T486	7
values[11]	574	1			T487	1		T354	2		T486	4
values[12]	472	1			T487	1		T354	2		T486	2
values[13]	475	1			T487	1		T354	2		T486	2
values[14]	451	1			T487	1		T354	2		T486	3
values[15]	461	1			T487	1		T354	2		T486	1
values[16]	487	1			T487	1		T354	2		T486	4
values[17]	458	1			T487	1		T354	2		T486	4
values[18]	486	1			T487	1		T354	2		T486	4
values[19]	420	1			T487	1		T354	2		T486	1
values[20]	462	1			T487	1		T354	2		T486	3
values[21]	441	1			T487	1		T354	2		T486	4
values[22]	496	1			T487	1		T354	2		T486	2
values[23]	444	1			T487	1		T354	2		T486	2
values[24]	421	1			T487	1		T354	2		T486	6
values[25]	421	1			T487	1		T354	2		T486	9
values[26]	390	1			T487	1		T354	2		T486	7
values[27]	385	1			T487	1		T354	2		T486	7
values[28]	488	1			T487	1		T354	2		T486	4
values[29]	382	1			T487	1		T354	2		T486	2
values[30]	371	1			T487	1		T354	2		T486	8
values[31]	349	1			T487	2		T354	2		T486	7
values[32]	385	1			T487	1		T354	2		T486	2
values[33]	367	1			T487	1		T354	2		T486	1
values[34]	378	1			T487	1		T354	2		T486	2
values[35]	393	1			T487	1		T354	2		T486	5
values[36]	380	1			T487	1		T354	2		T486	3
values[37]	385	1			T487	1		T354	2		T486	5
values[38]	403	1			T487	1		T354	2		T486	6
values[39]	333	1			T487	1		T354	2		T486	1
values[40]	326	1			T487	1		T354	2		T486	2
values[41]	288	1			T487	1		T354	2		T486	2
values[42]	245	1			T487	1		T354	2		T486	3
values[43]	233	1			T487	1		T354	2		T486	2
values[44]	240	1			T487	1		T354	3		T486	2
values[45]	274	1			T487	1		T354	2		T486	11
values[46]	249	1			T487	1		T354	2		T486	2
values[47]	240	1			T487	1		T354	2		T486	1
values[48]	306	1			T487	1		T354	2		T486	1
values[49]	230	1			T487	1		T354	2		T486	3
values[50]	209	1			T487	1		T354	2		T486	5
values[51]	173	1			T487	1		T354	2		T486	1
values[52]	152	1			T487	1		T354	2		T486	2
values[53]	126	1			T487	1		T354	2		T486	6
values[54]	138	1			T487	1		T354	2		T486	8
values[55]	114	1			T487	1		T354	2		T486	1
values[56]	93	1			T487	1		T354	2		T486	1
values[57]	90	1			T487	1		T354	2		T486	2
values[58]	82	1			T487	1		T354	2		T486	2
values[59]	57	1			T487	1		T354	2		T486	2
values[60]	54	1			T487	1		T354	2		T486	3
values[61]	49	1			T487	1		T354	2		T486	11
values[62]	42	1			T487	1		T354	2		T486	8
values[63]	59	1			T487	1		T354	2		T486	19
values[64]	71	1			T487	1		T354	2		T486	17
values[65]	59	1			T487	1		T354	2		T486	10
values[66]	54	1			T487	1		T354	2		T486	14
values[67]	39	1			T487	1		T354	2		T486	6
values[68]	41	1			T487	1		T354	2		T486	5
values[69]	39	1			T487	1		T354	2		T486	8
values[70]	39	1			T487	1		T354	2		T486	9
values[71]	50	1			T487	1		T354	2		T486	9
values[72]	41	1			T487	1		T354	2		T486	1
values[73]	50	1			T487	1		T354	2		T486	8
values[74]	50	1			T487	1		T354	2		T486	2
values[75]	46	1			T487	1		T354	2		T486	8
values[76]	52	1			T487	1		T354	2		T486	14
values[77]	37	1			T487	1		T354	2		T486	3
values[78]	61	1			T487	1		T354	2		T486	10
values[79]	40	1			T487	1		T354	2		T486	4
values[80]	44	1			T487	1		T354	3		T486	4
values[81]	46	1			T487	1		T354	2		T486	6
values[82]	61	1			T487	1		T354	2		T486	4
values[83]	52	1			T487	1		T354	2		T486	5
values[84]	55	1			T487	1		T354	2		T486	7
values[85]	64	1			T487	1		T354	2		T486	15
values[86]	60	1			T487	1		T354	2		T486	7
values[87]	60	1			T487	1		T354	6		T486	6
values[88]	60	1			T487	2		T354	5		T486	6
values[89]	62	1			T487	2		T354	6		T486	11
values[90]	50	1			T487	1		T354	3		T486	9
values[91]	60	1			T487	2		T354	5		T486	16
values[92]	65	1			T487	4		T354	2		T486	21
values[93]	69	1			T487	8		T354	3		T486	10
values[94]	57	1			T487	2		T354	5		T486	6
values[95]	50	1			T487	4		T354	9		T486	4
values[96]	41	1			T487	2		T354	3		T486	1
values[97]	36	1			T487	2		T354	2		T816	1
values[98]	51	1			T487	1		T354	7		T816	1
values[99]	42	1			T487	1		T354	4		T816	1
values[100]	48	1			T487	1		T354	3		T816	1
values[101]	51	1			T487	3		T354	4		T816	1
values[102]	42	1			T487	3		T354	2		T816	1
values[103]	49	1			T487	3		T354	3		T816	1
values[104]	47	1			T487	2		T354	2		T816	1
values[105]	38	1			T487	1		T354	3		T816	1
values[106]	43	1			T487	1		T354	2		T816	1
values[107]	58	1			T487	1		T354	2		T816	1
values[108]	58	1			T487	1		T354	2		T816	2
values[109]	55	1			T487	3		T354	4		T816	2
values[110]	59	1			T487	3		T354	3		T816	3
values[111]	62	1			T487	3		T354	4		T816	2
values[112]	60	1			T487	1		T354	4		T816	2
values[113]	49	1			T487	1		T354	3		T816	2
values[114]	53	1			T487	1		T354	3		T816	1
values[115]	53	1			T487	2		T354	3		T816	2
values[116]	58	1			T487	4		T354	5		T816	2
values[117]	73	1			T487	3		T354	7		T816	2
values[118]	48	1			T487	2		T354	2		T816	3
values[119]	50	1			T487	3		T354	2		T816	4
values[120]	40	1			T487	1		T354	5		T816	2
values[121]	48	1			T487	1		T354	4		T816	2
values[122]	52	1			T487	1		T354	2		T816	3
values[123]	52	1			T487	2		T354	5		T816	1
values[124]	54	1			T487	2		T354	4		T816	2
values[125]	56	1			T487	2		T354	4		T816	3
values[126]	132	1			T487	4		T354	9		T816	5
values[127]	1650	1			T487	61		T354	115		T816	55
values[128]	7453	1			T487	216		T354	540		T816	289