Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
122921 |
1 |
|
|
T69 |
75 |
|
T70 |
40 |
|
T71 |
3 |
| auto[1] |
66149 |
1 |
|
|
T69 |
9 |
|
T70 |
16 |
|
T71 |
2 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
47904 |
1 |
|
|
T69 |
9 |
|
T70 |
13 |
|
T71 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
133127 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
55943 |
1 |
|
|
T69 |
21 |
|
T70 |
18 |
|
T71 |
2 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14821 |
1 |
|
|
T69 |
2 |
|
T70 |
4 |
|
T71 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
133690 |
1 |
|
|
T69 |
55 |
|
T70 |
19 |
|
T71 |
1 |
| auto[1] |
70575 |
1 |
|
|
T69 |
27 |
|
T70 |
22 |
|
T71 |
3 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
51632 |
1 |
|
|
T69 |
18 |
|
T70 |
9 |
|
T71 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
143598 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
60667 |
1 |
|
|
T69 |
19 |
|
T70 |
14 |
|
T71 |
2 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
16236 |
1 |
|
|
T69 |
3 |
|
T70 |
1 |
|
T71 |
2 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
130297 |
1 |
|
|
T69 |
31 |
|
T70 |
40 |
|
T71 |
1 |
| auto[1] |
62984 |
1 |
|
|
T69 |
51 |
|
T70 |
10 |
|
T71 |
1 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49454 |
1 |
|
|
T69 |
10 |
|
T70 |
16 |
|
T71 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
135680 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
57601 |
1 |
|
|
T69 |
21 |
|
T70 |
17 |
|
T111 |
1 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15446 |
1 |
|
|
T69 |
3 |
|
T70 |
8 |
|
T491 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129883 |
1 |
|
|
T69 |
23 |
|
T70 |
24 |
|
T71 |
4 |
| auto[1] |
66872 |
1 |
|
|
T69 |
57 |
|
T70 |
15 |
|
T71 |
1 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
50430 |
1 |
|
|
T69 |
11 |
|
T70 |
10 |
|
T71 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
138415 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
58340 |
1 |
|
|
T69 |
15 |
|
T70 |
10 |
|
T111 |
4 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15423 |
1 |
|
|
T69 |
2 |
|
T70 |
1 |
|
T111 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126021 |
1 |
|
|
T69 |
50 |
|
T70 |
41 |
|
T71 |
4 |
| auto[1] |
63875 |
1 |
|
|
T69 |
30 |
|
T70 |
10 |
|
T71 |
1 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49290 |
1 |
|
|
T69 |
15 |
|
T70 |
22 |
|
T71 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
133176 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
56720 |
1 |
|
|
T69 |
17 |
|
T70 |
20 |
|
T71 |
1 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15298 |
1 |
|
|
T69 |
1 |
|
T70 |
9 |
|
T111 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123172 |
1 |
|
|
T69 |
26 |
|
T70 |
37 |
|
T111 |
3 |
| auto[1] |
69288 |
1 |
|
|
T69 |
60 |
|
T70 |
8 |
|
T71 |
2 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
48373 |
1 |
|
|
T69 |
10 |
|
T70 |
14 |
|
T111 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
135346 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
57114 |
1 |
|
|
T69 |
22 |
|
T70 |
13 |
|
T111 |
2 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15081 |
1 |
|
|
T69 |
1 |
|
T70 |
6 |
|
T111 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
121213 |
1 |
|
|
T69 |
59 |
|
T70 |
19 |
|
T71 |
7 |
| auto[1] |
65191 |
1 |
|
|
T69 |
5 |
|
T70 |
28 |
|
T71 |
1 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
46477 |
1 |
|
|
T69 |
13 |
|
T70 |
12 |
|
T71 |
3 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
131348 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
55056 |
1 |
|
|
T69 |
19 |
|
T70 |
20 |
|
T71 |
5 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14464 |
1 |
|
|
T69 |
2 |
|
T70 |
5 |
|
T71 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123337 |
1 |
|
|
T69 |
29 |
|
T70 |
32 |
|
T71 |
5 |
| auto[1] |
71557 |
1 |
|
|
T69 |
40 |
|
T70 |
18 |
|
T71 |
1 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49793 |
1 |
|
|
T69 |
11 |
|
T70 |
15 |
|
T71 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
137051 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
57843 |
1 |
|
|
T69 |
18 |
|
T70 |
19 |
|
T71 |
2 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15474 |
1 |
|
|
T69 |
2 |
|
T70 |
3 |
|
T71 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126619 |
1 |
|
|
T69 |
57 |
|
T70 |
29 |
|
T111 |
1 |
| auto[1] |
63998 |
1 |
|
|
T69 |
8 |
|
T70 |
23 |
|
T71 |
3 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49687 |
1 |
|
|
T69 |
8 |
|
T70 |
16 |
|
T71 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
133581 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
57036 |
1 |
|
|
T69 |
10 |
|
T70 |
19 |
|
T71 |
1 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15613 |
1 |
|
|
T69 |
4 |
|
T70 |
6 |
|
T484 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
134323 |
1 |
|
|
T69 |
73 |
|
T70 |
45 |
|
T111 |
4 |
| auto[1] |
67101 |
1 |
|
|
T69 |
7 |
|
T70 |
10 |
|
T71 |
3 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
50729 |
1 |
|
|
T69 |
11 |
|
T70 |
20 |
|
T111 |
4 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
142065 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
59359 |
1 |
|
|
T69 |
20 |
|
T70 |
20 |
|
T111 |
1 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15724 |
1 |
|
|
T69 |
1 |
|
T70 |
7 |
|
T111 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
118989 |
1 |
|
|
T69 |
66 |
|
T70 |
50 |
|
T71 |
5 |
| auto[1] |
71479 |
1 |
|
|
T69 |
12 |
|
T70 |
5 |
|
T71 |
1 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
47304 |
1 |
|
|
T69 |
11 |
|
T70 |
20 |
|
T71 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
134194 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
56274 |
1 |
|
|
T69 |
22 |
|
T70 |
23 |
|
T71 |
1 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14767 |
1 |
|
|
T69 |
2 |
|
T70 |
6 |
|
T111 |
2 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
964499 |
1 |
|
|
T69 |
511 |
|
T70 |
132 |
|
T71 |
6 |
| auto[1] |
537783 |
1 |
|
|
T69 |
85 |
|
T70 |
267 |
|
T71 |
26 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
385526 |
1 |
|
|
T69 |
76 |
|
T70 |
134 |
|
T71 |
14 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
1045099 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
457183 |
1 |
|
|
T69 |
155 |
|
T70 |
146 |
|
T71 |
6 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
122562 |
1 |
|
|
T69 |
23 |
|
T70 |
52 |
|
T71 |
3 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
128691 |
1 |
|
|
T69 |
75 |
|
T70 |
26 |
|
T71 |
3 |
| auto[1] |
64782 |
1 |
|
|
T69 |
17 |
|
T70 |
26 |
|
T71 |
3 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
48871 |
1 |
|
|
T69 |
15 |
|
T70 |
19 |
|
T71 |
4 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
136126 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
57347 |
1 |
|
|
T69 |
29 |
|
T70 |
11 |
|
T71 |
3 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15259 |
1 |
|
|
T69 |
4 |
|
T70 |
4 |
|
T71 |
3 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
120892 |
1 |
|
|
T69 |
64 |
|
T70 |
39 |
|
T71 |
3 |
| auto[1] |
64899 |
1 |
|
|
T69 |
6 |
|
T70 |
22 |
|
T71 |
3 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
47353 |
1 |
|
|
T69 |
11 |
|
T70 |
29 |
|
T71 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
130595 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
55196 |
1 |
|
|
T69 |
17 |
|
T70 |
17 |
|
T71 |
1 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14730 |
1 |
|
|
T69 |
5 |
|
T70 |
9 |
|
T71 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125170 |
1 |
|
|
T69 |
32 |
|
T70 |
27 |
|
T71 |
1 |
| auto[1] |
65168 |
1 |
|
|
T69 |
57 |
|
T70 |
27 |
|
T484 |
1 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
48695 |
1 |
|
|
T69 |
11 |
|
T70 |
19 |
|
T71 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
132277 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
58061 |
1 |
|
|
T69 |
23 |
|
T70 |
9 |
|
T111 |
1 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15583 |
1 |
|
|
T69 |
2 |
|
T70 |
2 |
|
T491 |
2 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126640 |
1 |
|
|
T69 |
44 |
|
T70 |
24 |
|
T71 |
3 |
| auto[1] |
66386 |
1 |
|
|
T69 |
24 |
|
T70 |
24 |
|
T71 |
3 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49384 |
1 |
|
|
T69 |
12 |
|
T70 |
20 |
|
T71 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
135796 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
57230 |
1 |
|
|
T69 |
22 |
|
T70 |
15 |
|
T71 |
3 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15330 |
1 |
|
|
T69 |
6 |
|
T70 |
6 |
|
T71 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123891 |
1 |
|
|
T69 |
73 |
|
T70 |
17 |
|
T111 |
6 |
| auto[1] |
70466 |
1 |
|
|
T70 |
26 |
|
T71 |
8 |
|
T484 |
2 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
50179 |
1 |
|
|
T69 |
8 |
|
T70 |
14 |
|
T71 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
136572 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
57785 |
1 |
|
|
T69 |
22 |
|
T70 |
16 |
|
T71 |
3 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15569 |
1 |
|
|
T69 |
1 |
|
T70 |
4 |
|
T71 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125120 |
1 |
|
|
T69 |
65 |
|
T70 |
33 |
|
T71 |
2 |
| auto[1] |
65185 |
1 |
|
|
T69 |
9 |
|
T70 |
14 |
|
T71 |
2 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
48481 |
1 |
|
|
T69 |
9 |
|
T70 |
13 |
|
T71 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
133539 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
56766 |
1 |
|
|
T69 |
24 |
|
T70 |
16 |
|
T71 |
1 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15184 |
1 |
|
|
T69 |
2 |
|
T70 |
3 |
|
T484 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
128053 |
1 |
|
|
T69 |
69 |
|
T70 |
45 |
|
T71 |
1 |
| auto[1] |
68838 |
1 |
|
|
T69 |
6 |
|
T70 |
3 |
|
T71 |
5 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
50568 |
1 |
|
|
T69 |
10 |
|
T70 |
15 |
|
T111 |
1 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
137982 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
58909 |
1 |
|
|
T69 |
22 |
|
T70 |
12 |
|
T71 |
2 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15945 |
1 |
|
|
T69 |
3 |
|
T70 |
5 |
|
T111 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136562 |
1 |
|
|
T69 |
55 |
|
T70 |
33 |
|
T71 |
3 |
| auto[1] |
64936 |
1 |
|
|
T69 |
10 |
|
T70 |
20 |
|
T71 |
3 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
52013 |
1 |
|
|
T69 |
5 |
|
T70 |
17 |
|
T71 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
140460 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
61038 |
1 |
|
|
T69 |
13 |
|
T70 |
18 |
|
T71 |
2 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
16472 |
1 |
|
|
T70 |
7 |
|
T71 |
1 |
|
T111 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
120733 |
1 |
|
|
T69 |
37 |
|
T70 |
28 |
|
T71 |
9 |
| auto[1] |
66117 |
1 |
|
|
T69 |
42 |
|
T70 |
16 |
|
T71 |
1 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
47466 |
1 |
|
|
T69 |
8 |
|
T70 |
22 |
|
T71 |
4 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
131428 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
55422 |
1 |
|
|
T69 |
14 |
|
T70 |
16 |
|
T71 |
2 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14833 |
1 |
|
|
T69 |
3 |
|
T70 |
8 |
|
T71 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
128745 |
1 |
|
|
T69 |
69 |
|
T70 |
39 |
|
T71 |
4 |
| auto[1] |
75565 |
1 |
|
|
T69 |
6 |
|
T70 |
24 |
|
T71 |
2 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
53010 |
1 |
|
|
T69 |
10 |
|
T70 |
22 |
|
T71 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
141778 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
62532 |
1 |
|
|
T69 |
16 |
|
T70 |
20 |
|
T71 |
2 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
17083 |
1 |
|
|
T69 |
1 |
|
T70 |
10 |
|
T71 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
128251 |
1 |
|
|
T69 |
49 |
|
T70 |
42 |
|
T71 |
4 |
| auto[1] |
66657 |
1 |
|
|
T69 |
19 |
|
T70 |
14 |
|
T111 |
1 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
50955 |
1 |
|
|
T69 |
5 |
|
T70 |
20 |
|
T71 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
135085 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
59823 |
1 |
|
|
T69 |
14 |
|
T70 |
13 |
|
T71 |
3 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
16450 |
1 |
|
|
T69 |
2 |
|
T70 |
4 |
|
T71 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
119607 |
1 |
|
|
T69 |
42 |
|
T70 |
25 |
|
T71 |
3 |
| auto[1] |
61176 |
1 |
|
|
T69 |
35 |
|
T70 |
34 |
|
T71 |
2 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
47019 |
1 |
|
|
T69 |
12 |
|
T70 |
15 |
|
T71 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
126787 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
53996 |
1 |
|
|
T69 |
13 |
|
T70 |
14 |
|
T71 |
2 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14760 |
1 |
|
|
T69 |
2 |
|
T70 |
4 |
|
T71 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125518 |
1 |
|
|
T69 |
60 |
|
T70 |
35 |
|
T111 |
6 |
| auto[1] |
65411 |
1 |
|
|
T69 |
30 |
|
T70 |
1 |
|
T71 |
3 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
47764 |
1 |
|
|
T69 |
19 |
|
T70 |
13 |
|
T111 |
4 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
134456 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
56473 |
1 |
|
|
T69 |
21 |
|
T70 |
8 |
|
T71 |
1 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
14792 |
1 |
|
|
T69 |
3 |
|
T70 |
3 |
|
T111 |
2 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125685 |
1 |
|
|
T69 |
24 |
|
T70 |
36 |
|
T71 |
9 |
| auto[1] |
66057 |
1 |
|
|
T69 |
54 |
|
T70 |
3 |
|
T484 |
4 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49240 |
1 |
|
|
T69 |
10 |
|
T70 |
15 |
|
T71 |
2 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
133845 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
57897 |
1 |
|
|
T69 |
22 |
|
T70 |
8 |
|
T71 |
4 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15593 |
1 |
|
|
T69 |
2 |
|
T70 |
1 |
|
T71 |
1 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
120177 |
1 |
|
|
T69 |
29 |
|
T70 |
26 |
|
T71 |
3 |
| auto[1] |
70727 |
1 |
|
|
T69 |
46 |
|
T70 |
17 |
|
T71 |
1 |