Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	470	1			T396	5		T366	3		T495	1
all_values[1]	427	1			T396	3		T397	1		T366	1
all_values[2]	466	1			T396	1		T397	2		T363	1
all_values[3]	489	1			T396	5		T354	1		T486	1
all_values[4]	517	1			T396	4		T397	1		T492	1
all_values[5]	490	1			T396	4		T397	2		T492	1
all_values[6]	469	1			T366	1		T492	1		T487	1
all_values[7]	459	1			T396	6		T397	1		T486	2
all_values[8]	453	1			T396	5		T366	2		T487	1
all_values[9]	465	1			T396	1		T487	2		T354	2
all_values[10]	434	1			T396	3		T397	1		T363	1
all_values[11]	476	1			T396	1		T397	1		T354	1
all_values[12]	498	1			T396	3		T397	4		T366	1
all_values[13]	490	1			T396	2		T397	1		T363	1
all_values[14]	442	1			T396	1		T366	1		T492	1
all_values[15]	473	1			T396	3		T363	1		T492	1
all_values[16]	431	1			T396	2		T397	1		T492	1
all_values[17]	463	1			T396	1		T397	1		T495	1
all_values[18]	487	1			T396	2		T397	2		T492	1
all_values[19]	468	1			T396	2		T492	1		T486	2
all_values[20]	458	1			T396	1		T397	1		T492	1
all_values[21]	464	1			T396	2		T397	1		T492	1
all_values[22]	512	1			T396	3		T397	1		T366	1
all_values[23]	499	1			T396	6		T492	3		T495	1
all_values[24]	487	1			T396	1		T366	2		T495	1
all_values[25]	515	1			T396	1		T397	1		T366	2
all_values[26]	452	1			T396	2		T397	2		T366	2
all_values[27]	466	1			T396	6		T397	1		T492	3
all_values[28]	478	1			T396	5		T397	4		T366	1
all_values[29]	458	1			T396	2		T397	1		T487	2
all_values[30]	446	1			T396	2		T397	1		T492	1
all_values[31]	508	1			T396	6		T397	1		T363	1
all_values[32]	473	1			T396	6		T397	1		T366	1
all_values[33]	482	1			T396	3		T354	1		T486	1
all_values[34]	452	1			T396	3		T397	2		T363	1
all_values[35]	483	1			T396	4		T366	1		T495	2
all_values[36]	511	1			T396	7		T363	1		T492	1
all_values[37]	461	1			T396	2		T397	1		T492	1
all_values[38]	475	1			T396	3		T397	1		T366	2
all_values[39]	503	1			T396	4		T397	1		T492	1
all_values[40]	463	1			T396	2		T397	1		T366	1
all_values[41]	444	1			T396	2		T834	3		T839	1
all_values[42]	469	1			T396	2		T397	2		T868	1
all_values[43]	467	1			T396	2		T397	3		T363	1
all_values[44]	484	1			T396	4		T397	1		T492	1
all_values[45]	498	1			T396	3		T492	1		T487	1
all_values[46]	493	1			T396	3		T397	3		T492	1
all_values[47]	501	1			T396	6		T366	1		T492	1
all_values[48]	469	1			T397	2		T366	1		T363	1
all_values[49]	491	1			T396	1		T366	1		T492	1