Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3635	1			T396	32		T397	2		T366	1
all_values[1]	3701	1			T211	2		T396	40		T397	3
all_values[2]	3703	1			T396	43		T397	3		T366	3
all_values[3]	3741	1			T396	44		T397	2		T366	3
all_values[4]	3660	1			T211	1		T396	32		T397	2
all_values[5]	3596	1			T211	3		T396	38		T397	2
all_values[6]	3658	1			T211	2		T396	37		T397	3
all_values[7]	3634	1			T211	1		T396	46		T397	5
all_values[8]	3818	1			T211	2		T396	41		T397	3
all_values[9]	3696	1			T211	1		T396	37		T397	4
all_values[10]	3799	1			T396	29		T397	1		T366	5
all_values[11]	3646	1			T211	1		T396	37		T397	2
all_values[12]	3757	1			T211	3		T396	44		T397	1
all_values[13]	3628	1			T211	1		T396	31		T397	2
all_values[14]	3644	1			T396	27		T397	1		T366	3
all_values[15]	3695	1			T211	1		T396	29		T397	1
all_values[16]	3792	1			T396	35		T397	2		T366	1
all_values[17]	3714	1			T211	1		T396	36		T397	4
all_values[18]	3714	1			T211	2		T396	37		T397	6
all_values[19]	3716	1			T211	2		T396	26		T397	2
all_values[20]	3827	1			T396	28		T397	1		T366	4
all_values[21]	3685	1			T211	1		T396	30		T397	6
all_values[22]	3739	1			T396	34		T366	1		T363	3
all_values[23]	3685	1			T211	4		T396	31		T397	1
all_values[24]	3671	1			T211	1		T396	25		T397	6
all_values[25]	3788	1			T211	1		T396	40		T397	2
all_values[26]	3702	1			T396	28		T397	4		T366	2
all_values[27]	3792	1			T396	37		T397	1		T363	4
all_values[28]	3757	1			T211	2		T396	37		T366	4
all_values[29]	3766	1			T211	2		T396	29		T397	2
all_values[30]	3727	1			T396	31		T397	3		T363	4
all_values[31]	3682	1			T396	29		T397	1		T366	4
all_values[32]	3736	1			T211	4		T396	37		T397	1
all_values[33]	3726	1			T211	1		T396	34		T397	2
all_values[34]	3666	1			T211	1		T396	30		T397	2
all_values[35]	3724	1			T211	1		T396	42		T397	1
all_values[36]	3677	1			T211	1		T396	36		T397	2
all_values[37]	3754	1			T211	2		T396	42		T397	1
all_values[38]	3728	1			T211	1		T396	32		T397	2
all_values[39]	3884	1			T211	4		T396	34		T397	1
all_values[40]	3733	1			T211	3		T396	39		T397	3
all_values[41]	3711	1			T396	45		T397	1		T366	1
all_values[42]	3755	1			T211	2		T396	25		T397	4
all_values[43]	3688	1			T211	1		T396	34		T397	3
all_values[44]	3682	1			T211	1		T396	37		T397	2
all_values[45]	3683	1			T211	3		T396	30		T397	2
all_values[46]	3720	1			T211	1		T396	36		T366	2
all_values[47]	3705	1			T211	2		T396	38		T397	2
all_values[48]	3739	1			T211	1		T396	25		T397	1
all_values[49]	3758	1			T211	1		T396	36		T397	1
all_values[50]	3770	1			T211	2		T396	18		T397	3
all_values[51]	3844	1			T211	1		T396	29		T363	1
all_values[52]	3738	1			T396	30		T397	4		T366	4
all_values[53]	3751	1			T211	1		T396	36		T366	5
all_values[54]	3768	1			T396	34		T397	2		T366	4
all_values[55]	3710	1			T211	1		T396	37		T397	4
all_values[56]	3771	1			T396	39		T397	3		T363	3
all_values[57]	3628	1			T211	1		T396	32		T397	4
all_values[58]	3606	1			T396	37		T366	2		T363	5
all_values[59]	3855	1			T396	37		T397	1		T366	6
all_values[60]	3904	1			T396	40		T366	6		T363	2
all_values[61]	3717	1			T211	1		T396	36		T366	2
all_values[62]	3710	1			T211	1		T396	40		T397	2
all_values[63]	3780	1			T211	3		T396	35		T397	2