Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	490	1			T470	1		T478	2		T472	2
all_values[1]	484	1			T73	1		T372	1		T367	1
all_values[2]	451	1			T372	1		T470	1		T347	1
all_values[3]	552	1			T73	2		T470	2		T478	2
all_values[4]	486	1			T836	1		T720	1		T891	1
all_values[5]	468	1			T367	2		T470	2		T472	1
all_values[6]	510	1			T73	1		T367	1		T666	1
all_values[7]	450	1			T372	1		T373	1		T848	1
all_values[8]	497	1			T470	1		T478	1		T669	4
all_values[9]	459	1			T73	1		T367	1		T470	3
all_values[10]	488	1			T367	1		T470	1		T835	1
all_values[11]	499	1			T478	1		T472	1		T835	1
all_values[12]	479	1			T478	1		T472	1		T474	1
all_values[13]	477	1			T372	1		T470	1		T478	2
all_values[14]	477	1			T367	1		T470	1		T474	2
all_values[15]	512	1			T470	1		T478	1		T835	1
all_values[16]	482	1			T73	1		T478	3		T835	1
all_values[17]	451	1			T367	1		T472	2		T669	2
all_values[18]	465	1			T470	2		T347	1		T472	1
all_values[19]	473	1			T372	1		T470	2		T347	1
all_values[20]	474	1			T73	1		T478	2		T474	1
all_values[21]	514	1			T836	1		T669	1		T848	1
all_values[22]	470	1			T347	1		T478	1		T472	1
all_values[23]	494	1			T73	1		T367	1		T470	2
all_values[24]	420	1			T73	1		T372	1		T347	1
all_values[25]	490	1			T372	1		T347	1		T669	2
all_values[26]	488	1			T372	1		T470	1		T474	1
all_values[27]	485	1			T347	1		T472	1		T373	1
all_values[28]	489	1			T474	1		T835	2		T373	1
all_values[29]	493	1			T347	1		T478	1		T472	1
all_values[30]	504	1			T367	1		T470	2		T472	1
all_values[31]	478	1			T372	1		T470	1		T347	2
all_values[32]	487	1			T372	1		T478	1		T835	1
all_values[33]	485	1			T73	1		T367	1		T470	1
all_values[34]	470	1			T372	2		T470	2		T347	1
all_values[35]	475	1			T367	2		T474	1		T373	1
all_values[36]	448	1			T367	1		T470	2		T669	1
all_values[37]	481	1			T470	1		T472	1		T373	1
all_values[38]	480	1			T372	1		T347	1		T373	1
all_values[39]	446	1			T470	1		T472	1		T373	1
all_values[40]	496	1			T347	1		T373	3		T720	1
all_values[41]	504	1			T73	1		T478	1		T373	1
all_values[42]	463	1			T347	1		T478	1		T669	4
all_values[43]	521	1			T478	1		T373	2		T666	1
all_values[44]	512	1			T372	1		T478	1		T474	1
all_values[45]	496	1			T347	2		T669	1		T848	1
all_values[46]	423	1			T472	1		T835	1		T373	1
all_values[47]	494	1			T835	1		T669	2		T848	1
all_values[48]	473	1			T478	1		T474	1		T835	1
all_values[49]	489	1			T347	2		T478	1		T669	2