Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.12	95.41	94.25	95.00		94.90	97.57	99.58

Total tests in report: 2849

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.60	40.60	39.04	39.04	39.15	39.15	47.69	47.69			55.84	55.84	61.67	61.67	0.19	0.19	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2086844692
56.65	16.06	59.13	20.09	56.32	17.17	59.12	11.43			74.61	18.77	90.00	28.33	0.73	0.54	/workspace/coverage/default/1.chip_jtag_csr_rw.396856594
63.43	6.78	66.38	7.25	59.25	2.93	60.85	1.73			75.23	0.62	90.00	0.00	28.86	28.13	/workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.3306928950
67.08	3.65	66.38	0.00	59.56	0.31	60.85	0.00			75.23	0.00	90.00	0.00	50.46	21.60	/workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.538219303
70.33	3.25	73.34	6.96	65.12	5.57	63.66	2.81			78.22	2.99	91.11	1.11	50.52	0.06	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.519113450
73.27	2.94	76.34	3.00	72.54	7.41	64.31	0.65			83.65	5.43	91.11	0.00	51.67	1.15	/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1602511397
75.89	2.62	76.58	0.24	74.42	1.88	67.28	2.97			84.04	0.39	91.11	0.00	61.89	10.22	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.3778778962
78.17	2.29	81.75	5.17	78.12	3.70	70.66	3.38			85.52	1.48	91.11	0.00	61.89	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1264656989
80.42	2.25	81.75	0.00	78.12	0.00	70.66	0.00			85.52	0.00	91.11	0.00	75.37	13.48	/workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.3687462167
82.18	1.76	81.84	0.09	78.13	0.01	80.67	10.01			85.53	0.01	91.48	0.37	75.42	0.05	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.110560551
83.92	1.74	85.30	3.46	80.30	2.17	82.97	2.30			88.04	2.51	91.48	0.00	75.42	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.2556065788
85.32	1.40	87.62	2.32	80.67	0.37	83.69	0.72			88.10	0.06	91.48	0.00	80.36	4.95	/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.491090079
86.47	1.15	87.63	0.01	81.36	0.69	83.69	0.00			88.18	0.08	91.48	0.00	86.45	6.09	/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.32443209
87.42	0.95	88.92	1.29	83.46	2.10	84.00	0.31			90.17	1.99	91.48	0.00	86.45	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.4109126382
88.19	0.77	89.08	0.16	83.56	0.10	84.21	0.21			90.26	0.09	95.56	4.07	86.45	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2114334416
88.89	0.70	89.08	0.00	83.56	0.00	84.21	0.00			90.26	0.00	95.56	0.00	90.66	4.21	/workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.3595812900
89.51	0.62	90.34	1.26	84.59	1.03	84.48	0.27			91.46	1.20	95.56	0.00	90.66	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.3492246854
90.07	0.55	90.34	0.00	84.62	0.03	86.12	1.65			91.46	0.00	95.56	0.00	92.30	1.65	/workspace/coverage/default/2.chip_sw_alert_test.4096321576
90.61	0.54	90.35	0.01	87.46	2.84	86.12	0.00			91.46	0.00	95.56	0.00	92.71	0.41	/workspace/coverage/cover_reg_top/15.chip_tl_errors.152669834
91.13	0.52	91.28	0.93	88.42	0.97	86.53	0.41			92.30	0.84	95.56	0.00	92.71	0.00	/workspace/coverage/default/1.chip_sw_gpio_smoketest.2892808727
91.63	0.49	91.28	0.00	88.42	0.00	86.53	0.00			92.30	0.00	95.56	0.00	95.66	2.95	/workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.3127068930
92.02	0.39	91.28	0.01	88.47	0.05	87.37	0.84			92.31	0.01	95.56	0.00	97.13	1.47	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.3288755902
92.40	0.38	91.84	0.56	88.75	0.28	88.46	1.09			92.48	0.17	95.74	0.19	97.14	0.01	/workspace/coverage/default/1.rom_e2e_shutdown_output.2405184374
92.74	0.33	92.29	0.45	89.13	0.37	88.65	0.19			92.90	0.42	96.30	0.56	97.14	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3685110582
92.99	0.26	92.80	0.52	89.58	0.45	88.77	0.12			93.35	0.45	96.30	0.00	97.14	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.1449774423
93.21	0.22	92.82	0.01	89.59	0.01	90.09	1.33			93.35	0.00	96.30	0.00	97.14	0.00	/workspace/coverage/default/1.chip_sw_edn_auto_mode.4292758212
93.42	0.20	93.06	0.24	89.76	0.18	90.50	0.41			93.53	0.18	96.48	0.19	97.16	0.01	/workspace/coverage/default/57.chip_sw_all_escalation_resets.2570692940
93.61	0.20	93.84	0.78	89.92	0.16	90.66	0.16			93.62	0.08	96.48	0.00	97.16	0.00	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.968016948
93.78	0.17	94.10	0.26	90.25	0.33	91.09	0.42			93.62	0.00	96.48	0.00	97.16	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1656765878
93.91	0.13	94.10	0.00	90.29	0.04	91.09	0.00			93.62	0.00	96.48	0.00	97.91	0.75	/workspace/coverage/cover_reg_top/39.xbar_random_large_delays.2480197134
94.03	0.11	94.11	0.01	90.29	0.00	91.75	0.66			93.62	0.00	96.48	0.00	97.91	0.00	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.241587550
94.13	0.10	94.11	0.00	90.29	0.00	92.38	0.63			93.62	0.00	96.48	0.00	97.91	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2554519857
94.23	0.10	94.13	0.02	90.33	0.04	92.87	0.50			93.67	0.05	96.48	0.00	97.91	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1978917459
94.33	0.10	94.13	0.00	90.61	0.28	92.88	0.01			93.98	0.32	96.48	0.00	97.91	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2470297704
94.42	0.09	94.13	0.00	91.17	0.56	92.88	0.00			93.98	0.00	96.48	0.00	97.91	0.00	/workspace/coverage/cover_reg_top/9.chip_tl_errors.1078386557
94.50	0.08	94.13	0.01	91.19	0.02	93.13	0.26			93.98	0.00	96.67	0.19	97.91	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1658407159
94.57	0.07	94.27	0.13	91.30	0.11	93.19	0.05			94.11	0.12	96.67	0.00	97.91	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.4018652869
94.64	0.07	94.30	0.03	91.60	0.30	93.20	0.01			94.17	0.07	96.67	0.00	97.92	0.01	/workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.728651199
94.71	0.07	94.45	0.15	91.74	0.14	93.20	0.00			94.27	0.10	96.67	0.00	97.92	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.2096203806
94.77	0.06	94.54	0.10	91.77	0.03	93.21	0.01			94.30	0.02	96.85	0.19	97.93	0.01	/workspace/coverage/default/7.chip_sw_all_escalation_resets.3805760772
94.83	0.06	94.54	0.00	91.92	0.15	93.21	0.00			94.31	0.02	96.85	0.00	98.12	0.19	/workspace/coverage/cover_reg_top/43.xbar_stress_all.923306788
94.88	0.06	94.55	0.01	92.06	0.14	93.25	0.04			94.47	0.16	96.85	0.00	98.12	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.405914685
94.93	0.05	94.55	0.00	92.06	0.00	93.55	0.31			94.47	0.00	96.85	0.00	98.12	0.00	/workspace/coverage/default/0.chip_sw_kmac_entropy.642355530
94.98	0.05	94.55	0.00	92.33	0.27	93.55	0.00			94.47	0.00	96.85	0.00	98.12	0.00	/workspace/coverage/cover_reg_top/18.chip_tl_errors.736257606
95.02	0.04	94.55	0.00	92.33	0.00	93.82	0.27			94.47	0.00	96.85	0.00	98.12	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2645584672
95.07	0.04	94.56	0.01	92.35	0.01	93.82	0.01			94.50	0.02	97.04	0.19	98.13	0.01	/workspace/coverage/default/67.chip_sw_all_escalation_resets.1215306024
95.11	0.04	94.57	0.01	92.36	0.01	93.86	0.04			94.51	0.01	97.22	0.19	98.13	0.00	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.1283457131
95.15	0.04	94.57	0.00	92.36	0.00	94.10	0.24			94.51	0.00	97.22	0.00	98.13	0.00	/workspace/coverage/default/0.chip_sw_flash_init.1231538894
95.18	0.04	94.57	0.01	92.37	0.01	94.10	0.00			94.51	0.01	97.41	0.19	98.14	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.782408984
95.22	0.04	94.58	0.01	92.38	0.01	94.11	0.01			94.52	0.01	97.59	0.19	98.16	0.01	/workspace/coverage/default/45.chip_sw_all_escalation_resets.1633040880
95.25	0.03	94.58	0.00	92.47	0.08	94.11	0.00			94.56	0.03	97.59	0.00	98.23	0.07	/workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.3544862456
95.28	0.03	94.65	0.08	92.51	0.04	94.11	0.00			94.61	0.05	97.59	0.00	98.23	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.501508962
95.31	0.03	94.70	0.04	92.57	0.05	94.15	0.05			94.63	0.02	97.59	0.00	98.23	0.00	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3862484540
95.34	0.03	94.70	0.00	92.73	0.17	94.15	0.00			94.63	0.00	97.59	0.00	98.23	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.2076881899
95.37	0.03	94.70	0.00	92.73	0.00	94.32	0.17			94.63	0.00	97.59	0.00	98.23	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3031940347
95.39	0.03	94.70	0.00	92.73	0.00	94.32	0.00			94.63	0.00	97.59	0.00	98.39	0.16	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.3531104864
95.42	0.03	94.76	0.06	92.80	0.07	94.33	0.01			94.66	0.02	97.59	0.00	98.39	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3175365568
95.45	0.03	94.83	0.08	92.80	0.00	94.40	0.07			94.66	0.01	97.59	0.00	98.39	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.2185162922
95.47	0.02	94.83	0.00	92.87	0.08	94.40	0.00			94.66	0.00	97.59	0.00	98.46	0.07	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.1026454100
95.49	0.02	94.84	0.01	92.94	0.07	94.41	0.01			94.71	0.05	97.59	0.00	98.46	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2576445269
95.52	0.02	94.84	0.00	93.08	0.14	94.41	0.00			94.71	0.00	97.59	0.00	98.46	0.00	/workspace/coverage/cover_reg_top/28.chip_tl_errors.486093490
95.54	0.02	94.90	0.05	93.14	0.05	94.41	0.00			94.73	0.02	97.59	0.00	98.46	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2693424464
95.56	0.02	94.91	0.01	93.21	0.07	94.42	0.01			94.76	0.03	97.59	0.00	98.46	0.00	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.4018322397
95.58	0.02	94.93	0.03	93.27	0.07	94.45	0.02			94.76	0.00	97.59	0.00	98.46	0.00	/workspace/coverage/default/2.chip_jtag_csr_rw.520937995
95.60	0.02	94.97	0.04	93.32	0.04	94.45	0.00			94.79	0.02	97.59	0.00	98.46	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1256350049
95.61	0.02	95.00	0.03	93.36	0.04	94.45	0.01			94.81	0.02	97.59	0.00	98.46	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.168356879
95.63	0.02	95.00	0.00	93.36	0.00	94.45	0.00			94.81	0.00	97.59	0.00	98.55	0.09	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1304627995
95.64	0.02	95.00	0.00	93.43	0.07	94.45	0.00			94.83	0.02	97.59	0.00	98.57	0.01	/workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.3038103712
95.66	0.01	95.02	0.03	93.44	0.01	94.50	0.05			94.83	0.00	97.59	0.00	98.57	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1755466999
95.67	0.01	95.03	0.01	93.44	0.00	94.57	0.07			94.84	0.01	97.59	0.00	98.57	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3280272771
95.69	0.01	95.06	0.03	93.47	0.03	94.58	0.01			94.85	0.02	97.59	0.00	98.57	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.541939450
95.70	0.01	95.06	0.00	93.54	0.07	94.58	0.00			94.85	0.00	97.59	0.00	98.57	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.3859098711
95.71	0.01	95.06	0.00	93.56	0.02	94.64	0.05			94.85	0.00	97.59	0.00	98.57	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1434558106
95.72	0.01	95.06	0.00	93.60	0.04	94.64	0.00			94.85	0.00	97.59	0.00	98.59	0.02	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.3503728557
95.73	0.01	95.06	0.01	93.65	0.05	94.64	0.00			94.86	0.01	97.59	0.00	98.59	0.00	/workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.2455607084
95.74	0.01	95.06	0.00	93.69	0.04	94.64	0.00			94.86	0.00	97.59	0.00	98.61	0.02	/workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.1103245026
95.75	0.01	95.06	0.00	93.75	0.06	94.64	0.00			94.86	0.00	97.59	0.00	98.61	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.2291476725
95.76	0.01	95.09	0.03	93.76	0.01	94.64	0.00			94.88	0.02	97.59	0.00	98.61	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2475622947
95.77	0.01	95.09	0.00	93.82	0.05	94.64	0.00			94.88	0.00	97.59	0.00	98.61	0.00	/workspace/coverage/cover_reg_top/19.chip_tl_errors.3788207712
95.78	0.01	95.09	0.00	93.82	0.00	94.69	0.05			94.88	0.00	97.59	0.00	98.61	0.00	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3575701020
95.79	0.01	95.09	0.00	93.82	0.00	94.69	0.00			94.88	0.00	97.59	0.00	98.66	0.05	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.2656814772
95.80	0.01	95.09	0.00	93.84	0.02	94.69	0.00			94.88	0.00	97.59	0.00	98.68	0.02	/workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.4111359206
95.80	0.01	95.09	0.00	93.88	0.04	94.69	0.00			94.88	0.00	97.59	0.00	98.68	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.627859908
95.81	0.01	95.09	0.00	93.92	0.04	94.69	0.00			94.88	0.00	97.59	0.00	98.68	0.00	/workspace/coverage/cover_reg_top/97.xbar_stress_all.3024942501
95.81	0.01	95.09	0.00	93.92	0.00	94.72	0.04			94.88	0.00	97.59	0.00	98.68	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1839070387
95.82	0.01	95.09	0.00	93.92	0.00	94.72	0.00			94.88	0.00	97.59	0.00	98.72	0.04	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.610882886
95.83	0.01	95.09	0.00	93.94	0.02	94.72	0.00			94.88	0.00	97.59	0.00	98.73	0.01	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.2754950644
95.83	0.01	95.09	0.00	93.94	0.00	94.75	0.03			94.88	0.00	97.59	0.00	98.73	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2031639664
95.83	0.01	95.09	0.00	93.94	0.00	94.78	0.03			94.88	0.00	97.59	0.00	98.73	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2741102029
95.84	0.01	95.09	0.00	93.95	0.01	94.78	0.00			94.88	0.00	97.59	0.00	98.74	0.01	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.832985969
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96.03	0.01	95.09	0.00	94.14	0.00	94.91	0.00			94.88	0.00	97.59	0.00	99.58	0.01	/workspace/coverage/default/90.chip_sw_all_escalation_resets.3526017788
96.03	0.01	95.09	0.00	94.15	0.01	94.91	0.00			94.88	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/36.xbar_access_same_device.3334687073
96.04	0.01	95.09	0.00	94.16	0.01	94.91	0.00			94.88	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2677557403
96.04	0.01	95.10	0.01	94.16	0.00	94.92	0.01			94.88	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/11.chip_sw_all_escalation_resets.443539379
96.04	0.01	95.10	0.00	94.16	0.00	94.93	0.01			94.88	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.477270203
96.04	0.01	95.10	0.00	94.16	0.00	94.94	0.01			94.88	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.995030767
96.04	0.01	95.10	0.00	94.16	0.00	94.95	0.01			94.88	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.275008800
96.04	0.01	95.10	0.00	94.16	0.00	94.96	0.01			94.88	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2199059832
96.05	0.01	95.10	0.00	94.16	0.00	94.97	0.01			94.88	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2579538853
96.05	0.01	95.10	0.00	94.16	0.00	94.97	0.00			94.89	0.01	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.304941732
96.05	0.01	95.10	0.00	94.16	0.00	94.97	0.00			94.90	0.01	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_tap_straps_dev.3600279157
96.05	0.01	95.10	0.00	94.17	0.01	94.97	0.00			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/23.xbar_stress_all.702487910
96.05	0.01	95.10	0.00	94.18	0.01	94.97	0.00			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/26.xbar_access_same_device.3328218547
96.05	0.01	95.10	0.00	94.18	0.01	94.97	0.00			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.2917671650
96.05	0.01	95.10	0.00	94.19	0.01	94.97	0.00			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.712471999
96.05	0.01	95.10	0.00	94.20	0.01	94.97	0.00			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_gpio.1220315533
96.06	0.01	95.10	0.01	94.20	0.00	94.97	0.00			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.3049323878
96.06	0.01	95.11	0.01	94.20	0.00	94.97	0.00			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_pattgen_ios.4191524228
96.06	0.01	95.11	0.00	94.20	0.00	94.97	0.01			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.2148829821
96.06	0.01	95.11	0.00	94.20	0.00	94.98	0.01			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.649195893
96.06	0.01	95.11	0.01	94.20	0.00	94.98	0.01			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_power_idle_load.1939474591
96.06	0.01	95.12	0.01	94.20	0.00	94.99	0.01			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.154904581
96.06	0.01	95.12	0.00	94.20	0.00	94.99	0.01			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1760783297
96.06	0.01	95.12	0.00	94.20	0.01	94.99	0.00			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_rw.3090865767
96.06	0.01	95.12	0.00	94.21	0.01	94.99	0.00			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/13.chip_tl_errors.425210772
96.06	0.01	95.12	0.00	94.21	0.01	94.99	0.00			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.2919820883
96.06	0.01	95.12	0.00	94.21	0.01	94.99	0.00			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.1803731508
96.07	0.01	95.12	0.00	94.22	0.01	94.99	0.00			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.3219238383
96.07	0.01	95.12	0.00	94.22	0.01	94.99	0.00			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/2.xbar_error_random.2882558473
96.07	0.01	95.12	0.00	94.22	0.01	94.99	0.00			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.501484991
96.07	0.01	95.12	0.00	94.23	0.01	94.99	0.00			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.412351624
96.07	0.01	95.12	0.00	94.23	0.01	94.99	0.00			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.1329480556
96.07	0.01	95.12	0.00	94.24	0.01	94.99	0.00			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.2157317484
96.07	0.01	95.12	0.00	94.24	0.01	94.99	0.00			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.364515456
96.07	0.01	95.12	0.00	94.24	0.01	94.99	0.00			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.392238109
96.07	0.01	95.12	0.00	94.25	0.01	94.99	0.00			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx.4068553734
96.07	0.01	95.12	0.01	94.25	0.00	94.99	0.00			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1307515270
96.07	0.01	95.12	0.00	94.25	0.00	94.99	0.01			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3202080396
96.07	0.01	95.12	0.00	94.25	0.00	95.00	0.01			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.1537128443
96.07	0.01	95.12	0.00	94.25	0.00	95.00	0.01			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2859595059
96.07	0.01	95.12	0.00	94.25	0.00	95.00	0.01			94.90	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1969927844

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.331108280
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2469965210
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2463512035
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2555716828
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1413968403
/workspace/coverage/cover_reg_top/0.chip_tl_errors.3531891407
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1319307436
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.399133268
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2719938494
/workspace/coverage/cover_reg_top/0.xbar_error_random.762914148
/workspace/coverage/cover_reg_top/0.xbar_random.2085931192
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.64118486
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1524770750
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1934309303
/workspace/coverage/cover_reg_top/0.xbar_same_source.1140717617
/workspace/coverage/cover_reg_top/0.xbar_smoke.1705343680
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.593034461
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.959557150
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1906326633
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3608153170
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1994862232
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.82924035
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1150760443
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.28793539
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.448399740
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3599266679
/workspace/coverage/cover_reg_top/1.chip_csr_rw.2826514229
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.3195364790
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.904568478
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.400811062
/workspace/coverage/cover_reg_top/1.chip_tl_errors.2483222046
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2703135404
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3818103448
/workspace/coverage/cover_reg_top/1.xbar_error_random.3251917799
/workspace/coverage/cover_reg_top/1.xbar_random.121708638
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.1241248936
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3268530765
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1710086605
/workspace/coverage/cover_reg_top/1.xbar_same_source.2897728594
/workspace/coverage/cover_reg_top/1.xbar_smoke.1840063626
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.692298954
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1912441080
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1658667791
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2907007696
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.93282921
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2279358729
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.830678356
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3484929065
/workspace/coverage/cover_reg_top/10.chip_csr_rw.747809227
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2498194920
/workspace/coverage/cover_reg_top/10.chip_tl_errors.1932458204
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.4032088671
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3033038926
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1958069367
/workspace/coverage/cover_reg_top/10.xbar_error_random.2126357947
/workspace/coverage/cover_reg_top/10.xbar_random.2525054206
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2930651278
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1733345251
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3358848046
/workspace/coverage/cover_reg_top/10.xbar_same_source.1445718351
/workspace/coverage/cover_reg_top/10.xbar_smoke.20309069
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2946552394
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2392410827
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.4061722854
/workspace/coverage/cover_reg_top/10.xbar_stress_all.2067203805
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.627616820
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.806268478
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.23910778
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1080776473
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3484929069
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.3725208199
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3218934777
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.347383315
/workspace/coverage/cover_reg_top/11.xbar_error_random.2875129515
/workspace/coverage/cover_reg_top/11.xbar_random.1097673974
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.67542534
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2920311006
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1118931411
/workspace/coverage/cover_reg_top/11.xbar_same_source.1256406479
/workspace/coverage/cover_reg_top/11.xbar_smoke.1999745523
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.146902067
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2442153539
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3077102452
/workspace/coverage/cover_reg_top/11.xbar_stress_all.4234407827
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.4089917643
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.794969657
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2866296366
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2018427928
/workspace/coverage/cover_reg_top/12.chip_csr_rw.159732226
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3662966753
/workspace/coverage/cover_reg_top/12.chip_tl_errors.778666362
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.2169154756
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.890497663
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1067951431
/workspace/coverage/cover_reg_top/12.xbar_error_random.1898379467
/workspace/coverage/cover_reg_top/12.xbar_random.3664800948
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2522792171
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.865231331
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1352933951
/workspace/coverage/cover_reg_top/12.xbar_same_source.1195959956
/workspace/coverage/cover_reg_top/12.xbar_smoke.1646180205
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2197029831
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.4230945399
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2553090365
/workspace/coverage/cover_reg_top/12.xbar_stress_all.1188237359
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.759094268
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.4228968763
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1942971323
/workspace/coverage/cover_reg_top/13.chip_csr_rw.1093366207
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2722878572
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.3107032210
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2388636428
/workspace/coverage/cover_reg_top/13.xbar_error_random.1263969100
/workspace/coverage/cover_reg_top/13.xbar_random.641284410
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2453000477
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.4143124754
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.532070772
/workspace/coverage/cover_reg_top/13.xbar_same_source.2428022041
/workspace/coverage/cover_reg_top/13.xbar_smoke.1845075389
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3748261526
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.705699968
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2559741686
/workspace/coverage/cover_reg_top/13.xbar_stress_all.531180344
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.531933117
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.4282686198
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2803078011
/workspace/coverage/cover_reg_top/14.chip_csr_rw.825939446
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.2094890439
/workspace/coverage/cover_reg_top/14.chip_tl_errors.2190243333
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.3423763073
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.2233949549
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2839054578
/workspace/coverage/cover_reg_top/14.xbar_error_random.755106536
/workspace/coverage/cover_reg_top/14.xbar_random.697247137
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.2424127116
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.2600129060
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.1781446321
/workspace/coverage/cover_reg_top/14.xbar_same_source.2874185954
/workspace/coverage/cover_reg_top/14.xbar_smoke.57157077
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.2947224519
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1455330338
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3446914613
/workspace/coverage/cover_reg_top/14.xbar_stress_all.3029481702
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.4042062111
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.1860202969
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1143119147
/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.1443425758
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/workspace/coverage/default/30.chip_sw_all_escalation_resets.2240436135
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3334681278
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2301583249
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3888527765
/workspace/coverage/default/34.chip_sw_all_escalation_resets.3911147095
/workspace/coverage/default/35.chip_sw_all_escalation_resets.1204926299
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2058739350
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3926781038
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.174432985
/workspace/coverage/default/39.chip_sw_all_escalation_resets.1946541316
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3464115008
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.4083171607
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3360311689
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1497908055
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1198895442
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.761841182
/workspace/coverage/default/4.chip_sw_uart_tx_rx.3290517461
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1621125552
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1101059501
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3666019769
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3698192844
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2403643890
/workspace/coverage/default/4.chip_tap_straps_dev.546949607
/workspace/coverage/default/4.chip_tap_straps_prod.3063456537
/workspace/coverage/default/4.chip_tap_straps_rma.3068380584
/workspace/coverage/default/4.chip_tap_straps_testunlock0.3956325982
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.672282596
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3952881568
/workspace/coverage/default/44.chip_sw_all_escalation_resets.3810819391
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3076994459
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2529915755
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1626853187
/workspace/coverage/default/48.chip_sw_all_escalation_resets.1681183819
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1386823420
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1363321612
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2420032924
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1694526492
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2715881996
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2230826416
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1884451648
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1574039842
/workspace/coverage/default/52.chip_sw_all_escalation_resets.3390343490
/workspace/coverage/default/53.chip_sw_all_escalation_resets.1826918224
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1382125971
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2661254729
/workspace/coverage/default/55.chip_sw_all_escalation_resets.4204047780
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1342798476
/workspace/coverage/default/56.chip_sw_all_escalation_resets.4009785566
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.259397703
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2187544931
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3675751837
/workspace/coverage/default/59.chip_sw_all_escalation_resets.537034628
/workspace/coverage/default/6.chip_sw_all_escalation_resets.3459690042
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2021303547
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1972672079
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1499654994
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1578280594
/workspace/coverage/default/61.chip_sw_all_escalation_resets.3042040739
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2470609094
/workspace/coverage/default/62.chip_sw_all_escalation_resets.3165865577
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1215573055
/workspace/coverage/default/63.chip_sw_all_escalation_resets.2330360944
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3595880048
/workspace/coverage/default/66.chip_sw_all_escalation_resets.1979919364
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2108957158
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1677029953
/workspace/coverage/default/68.chip_sw_all_escalation_resets.1374238180
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.719141496
/workspace/coverage/default/69.chip_sw_all_escalation_resets.2054378577
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2603241746
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2032204089
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1017939033
/workspace/coverage/default/70.chip_sw_all_escalation_resets.93091194
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1671557149
/workspace/coverage/default/71.chip_sw_all_escalation_resets.146856214
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2377648285
/workspace/coverage/default/72.chip_sw_all_escalation_resets.945060628
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.860615684
/workspace/coverage/default/73.chip_sw_all_escalation_resets.2983572857
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3843359096
/workspace/coverage/default/74.chip_sw_all_escalation_resets.763723328
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.778599357
/workspace/coverage/default/75.chip_sw_all_escalation_resets.2941554340
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1666403209
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.767736869
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1807773263
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1317176470
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1946416191
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1594248789
/workspace/coverage/default/79.chip_sw_all_escalation_resets.1075039809
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3849906520
/workspace/coverage/default/8.chip_sw_all_escalation_resets.4206529095
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1018881253
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.266503858
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.928704978
/workspace/coverage/default/80.chip_sw_all_escalation_resets.3939576664
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3111857642
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1011329337
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3184206809
/workspace/coverage/default/83.chip_sw_all_escalation_resets.237648739
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2824410226
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.472833089
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2974713561
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.967890949
/workspace/coverage/default/86.chip_sw_all_escalation_resets.3803747114
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.208023732
/workspace/coverage/default/87.chip_sw_all_escalation_resets.2192399514
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1033038518
/workspace/coverage/default/88.chip_sw_all_escalation_resets.1414606562
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1853335470
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3746392587
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2782495924
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4228268224
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3953607471
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3185248903
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2255088480
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2801424956
/workspace/coverage/default/95.chip_sw_all_escalation_resets.3129668060
/workspace/coverage/default/96.chip_sw_all_escalation_resets.3618656097
/workspace/coverage/default/97.chip_sw_all_escalation_resets.806631482
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1017209471
/workspace/coverage/default/99.chip_sw_all_escalation_resets.3854222883
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.136392355
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3425499889
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2917969015
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1555769994
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3696803592
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.425933622
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.463945292
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3047021399

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Total test records in report: 2849

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.519113450			Mar 03 04:05:00 PM PST 24	Mar 03 04:11:22 PM PST 24	3693120300 ps
T2	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.35342587			Mar 03 03:43:32 PM PST 24	Mar 03 03:47:09 PM PST 24	2261254214 ps
T3	/workspace/coverage/default/1.chip_sw_uart_tx_rx.808269369			Mar 03 03:45:43 PM PST 24	Mar 03 04:01:51 PM PST 24	5227026480 ps
T34	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2086844692			Mar 03 03:46:48 PM PST 24	Mar 03 04:56:07 PM PST 24	15765201624 ps
T4	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2645584672			Mar 03 03:48:34 PM PST 24	Mar 03 03:51:09 PM PST 24	3612234169 ps
T79	/workspace/coverage/default/2.chip_sw_otbn_smoketest.3309798282			Mar 03 04:05:40 PM PST 24	Mar 03 04:38:37 PM PST 24	9117491978 ps
T5	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1961651902			Mar 03 03:44:34 PM PST 24	Mar 03 03:57:45 PM PST 24	9452290426 ps
T6	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1497908055			Mar 03 04:07:20 PM PST 24	Mar 03 04:19:35 PM PST 24	10803640236 ps
T13	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3862484540			Mar 03 03:54:41 PM PST 24	Mar 03 04:12:23 PM PST 24	4962596360 ps
T80	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2071972936			Mar 03 03:44:49 PM PST 24	Mar 03 03:50:02 PM PST 24	2333651686 ps
T60	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3165965965			Mar 03 03:58:10 PM PST 24	Mar 03 04:18:22 PM PST 24	8569443532 ps
T59	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1995951938			Mar 03 03:56:47 PM PST 24	Mar 03 03:59:00 PM PST 24	2699089573 ps
T133	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1658407159			Mar 03 03:48:01 PM PST 24	Mar 03 03:59:39 PM PST 24	5401719436 ps
T250	/workspace/coverage/default/2.chip_sw_csrng_kat_test.166529856			Mar 03 04:00:14 PM PST 24	Mar 03 04:04:13 PM PST 24	2373799838 ps
T55	/workspace/coverage/default/2.chip_sw_alert_test.4096321576			Mar 03 03:58:42 PM PST 24	Mar 03 04:02:31 PM PST 24	2652662250 ps
T108	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1728160103			Mar 03 03:49:15 PM PST 24	Mar 03 04:53:29 PM PST 24	15169246002 ps
T61	/workspace/coverage/default/34.chip_sw_all_escalation_resets.3911147095			Mar 03 04:11:17 PM PST 24	Mar 03 04:20:46 PM PST 24	5158097136 ps
T226	/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1763490135			Mar 03 03:59:31 PM PST 24	Mar 03 04:11:29 PM PST 24	4714090440 ps
T58	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.110560551			Mar 03 03:49:22 PM PST 24	Mar 03 05:19:27 PM PST 24	48044689692 ps
T62	/workspace/coverage/default/57.chip_sw_all_escalation_resets.2570692940			Mar 03 04:13:08 PM PST 24	Mar 03 04:23:37 PM PST 24	4946064552 ps
T149	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2741102029			Mar 03 03:44:49 PM PST 24	Mar 03 03:55:50 PM PST 24	4306209000 ps
T132	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.828051906			Mar 03 03:46:21 PM PST 24	Mar 03 03:54:35 PM PST 24	5396582738 ps
T118	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1755466999			Mar 03 03:56:55 PM PST 24	Mar 03 04:38:50 PM PST 24	26909481907 ps
T170	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3950042045			Mar 03 04:03:55 PM PST 24	Mar 03 04:22:46 PM PST 24	5130034816 ps
T284	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.174432985			Mar 03 04:11:32 PM PST 24	Mar 03 04:20:35 PM PST 24	3049744508 ps
T198	/workspace/coverage/default/42.chip_sw_all_escalation_resets.726377260			Mar 03 04:08:12 PM PST 24	Mar 03 04:19:28 PM PST 24	6060455468 ps
T356	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2113812251			Mar 03 03:46:18 PM PST 24	Mar 03 03:51:44 PM PST 24	3662428898 ps
T128	/workspace/coverage/default/0.rom_keymgr_functest.2000313411			Mar 03 03:47:09 PM PST 24	Mar 03 03:58:37 PM PST 24	4859958156 ps
T134	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2114334416			Mar 03 03:44:50 PM PST 24	Mar 03 03:48:55 PM PST 24	2551558056 ps
T103	/workspace/coverage/default/0.chip_sw_otbn_smoketest.1040400159			Mar 03 03:45:53 PM PST 24	Mar 03 04:23:40 PM PST 24	8645533936 ps
T119	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3364032444			Mar 03 04:02:41 PM PST 24	Mar 03 04:12:47 PM PST 24	18904555702 ps
T262	/workspace/coverage/default/2.chip_sw_aes_enc.2685733410			Mar 03 04:03:05 PM PST 24	Mar 03 04:07:08 PM PST 24	2633097960 ps
T120	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1675831199			Mar 03 03:44:39 PM PST 24	Mar 03 03:46:29 PM PST 24	1936822736 ps
T155	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.765939879			Mar 03 04:02:16 PM PST 24	Mar 03 04:11:02 PM PST 24	5367257550 ps
T152	/workspace/coverage/default/1.chip_sw_edn_kat.1000964122			Mar 03 03:47:19 PM PST 24	Mar 03 03:58:50 PM PST 24	3325004264 ps
T20	/workspace/coverage/default/1.chip_jtag_csr_rw.396856594			Mar 03 03:37:55 PM PST 24	Mar 03 04:18:54 PM PST 24	21054832335 ps
T144	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.3134134798			Mar 03 03:46:12 PM PST 24	Mar 03 03:49:30 PM PST 24	2143909167 ps
T224	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.2747413068			Mar 03 04:05:37 PM PST 24	Mar 03 04:10:45 PM PST 24	3579773376 ps
T153	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3579740665			Mar 03 03:46:12 PM PST 24	Mar 03 04:14:27 PM PST 24	6840358482 ps
T175	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.4018652869			Mar 03 03:47:58 PM PST 24	Mar 03 03:53:00 PM PST 24	2856626501 ps
T126	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2021303547			Mar 03 04:03:56 PM PST 24	Mar 03 04:18:21 PM PST 24	9502545961 ps
T302	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1342798476			Mar 03 04:08:41 PM PST 24	Mar 03 04:14:15 PM PST 24	3543870572 ps
T41	/workspace/coverage/default/1.rom_e2e_shutdown_output.2405184374			Mar 03 03:53:32 PM PST 24	Mar 03 04:44:08 PM PST 24	25179475713 ps
T303	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.4102706577			Mar 03 04:06:26 PM PST 24	Mar 03 04:13:09 PM PST 24	3247262000 ps
T214	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.1283457131			Mar 03 03:54:01 PM PST 24	Mar 03 04:05:23 PM PST 24	4902596408 ps
T44	/workspace/coverage/default/1.rom_e2e_smoke.2082171600			Mar 03 03:50:23 PM PST 24	Mar 03 04:21:57 PM PST 24	8590216768 ps
T42	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.556520279			Mar 03 03:50:49 PM PST 24	Mar 03 04:32:12 PM PST 24	10533175000 ps
T179	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2062653528			Mar 03 03:46:12 PM PST 24	Mar 03 04:01:40 PM PST 24	4970972840 ps
T123	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2554519857			Mar 03 03:48:05 PM PST 24	Mar 03 05:09:42 PM PST 24	46969611290 ps
T169	/workspace/coverage/default/3.chip_tap_straps_prod.3058842517			Mar 03 04:02:51 PM PST 24	Mar 03 04:05:37 PM PST 24	2879700300 ps
T197	/workspace/coverage/default/87.chip_sw_all_escalation_resets.2192399514			Mar 03 04:10:41 PM PST 24	Mar 03 04:20:49 PM PST 24	4527047862 ps
T212	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1242185504			Mar 03 04:00:43 PM PST 24	Mar 03 04:20:50 PM PST 24	5127102312 ps
T239	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.506270222			Mar 03 03:47:53 PM PST 24	Mar 03 03:54:58 PM PST 24	10050551597 ps
T104	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1736524876			Mar 03 03:47:23 PM PST 24	Mar 03 04:54:15 PM PST 24	16758109584 ps
T191	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3651962153			Mar 03 04:00:37 PM PST 24	Mar 03 04:46:40 PM PST 24	25570755558 ps
T14	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.54191130			Mar 03 04:03:30 PM PST 24	Mar 03 04:21:03 PM PST 24	5886858020 ps
T145	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2090376123			Mar 03 03:46:07 PM PST 24	Mar 03 03:52:31 PM PST 24	3605344550 ps
T699	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1215573055			Mar 03 04:09:39 PM PST 24	Mar 03 04:15:54 PM PST 24	3898963642 ps
T66	/workspace/coverage/default/0.chip_jtag_mem_access.476388441			Mar 03 03:35:50 PM PST 24	Mar 03 03:57:38 PM PST 24	13441390760 ps
T362	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3083682822			Mar 03 03:59:38 PM PST 24	Mar 03 04:05:28 PM PST 24	3188206740 ps
T45	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3115556365			Mar 03 03:51:08 PM PST 24	Mar 03 04:26:25 PM PST 24	8703900540 ps
T363	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3666369922			Mar 03 04:01:25 PM PST 24	Mar 03 04:06:14 PM PST 24	3322170888 ps
T282	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3038797689			Mar 03 03:46:43 PM PST 24	Mar 03 03:57:43 PM PST 24	5710026324 ps
T332	/workspace/coverage/default/64.chip_sw_all_escalation_resets.2984497615			Mar 03 04:08:09 PM PST 24	Mar 03 04:19:08 PM PST 24	4405684152 ps
T114	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3304274369			Mar 03 03:57:41 PM PST 24	Mar 03 04:22:25 PM PST 24	10462509840 ps
T43	/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.1123402302			Mar 03 03:51:42 PM PST 24	Mar 03 04:26:51 PM PST 24	8908464280 ps
T124	/workspace/coverage/default/68.chip_sw_all_escalation_resets.1374238180			Mar 03 04:09:07 PM PST 24	Mar 03 04:21:26 PM PST 24	5368329252 ps
T127	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1385797629			Mar 03 03:55:24 PM PST 24	Mar 03 04:02:44 PM PST 24	4384251518 ps
T899	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.228953315			Mar 03 03:46:28 PM PST 24	Mar 03 03:52:13 PM PST 24	2925267000 ps
T900	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.913115907			Mar 03 04:05:36 PM PST 24	Mar 03 04:11:17 PM PST 24	3187644880 ps
T292	/workspace/coverage/default/86.chip_sw_all_escalation_resets.3803747114			Mar 03 04:10:28 PM PST 24	Mar 03 04:23:15 PM PST 24	6257361552 ps
T293	/workspace/coverage/default/93.chip_sw_all_escalation_resets.2255088480			Mar 03 04:11:32 PM PST 24	Mar 03 04:22:45 PM PST 24	5102477012 ps
T215	/workspace/coverage/default/7.chip_sw_all_escalation_resets.3805760772			Mar 03 04:04:23 PM PST 24	Mar 03 04:16:45 PM PST 24	5964902176 ps
T130	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.779651982			Mar 03 03:45:32 PM PST 24	Mar 03 03:48:01 PM PST 24	3966041611 ps
T233	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3595880048			Mar 03 04:15:00 PM PST 24	Mar 03 04:20:47 PM PST 24	3387124200 ps
T234	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.25978802			Mar 03 03:44:50 PM PST 24	Mar 03 03:48:55 PM PST 24	2686339700 ps
T190	/workspace/coverage/default/1.chip_tap_straps_dev.2431903653			Mar 03 03:48:33 PM PST 24	Mar 03 03:51:27 PM PST 24	2914419397 ps
T235	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3386697549			Mar 03 03:42:51 PM PST 24	Mar 03 03:53:06 PM PST 24	6491559086 ps
T236	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1486095572			Mar 03 03:46:26 PM PST 24	Mar 03 03:55:16 PM PST 24	5910423736 ps
T171	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.416687771			Mar 03 04:06:09 PM PST 24	Mar 03 04:43:31 PM PST 24	14809016838 ps
T237	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.4202963336			Mar 03 03:59:17 PM PST 24	Mar 03 04:12:36 PM PST 24	5086796556 ps
T150	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4132793691			Mar 03 03:46:56 PM PST 24	Mar 03 03:57:17 PM PST 24	3368474670 ps
T189	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.734083112			Mar 03 04:04:43 PM PST 24	Mar 03 04:19:39 PM PST 24	5678590740 ps
T710	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.989643120			Mar 03 03:59:44 PM PST 24	Mar 03 04:03:38 PM PST 24	3111671280 ps
T901	/workspace/coverage/default/0.chip_sw_kmac_idle.1211785801			Mar 03 03:48:09 PM PST 24	Mar 03 03:52:19 PM PST 24	3124198510 ps
T151	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1044414736			Mar 03 03:49:49 PM PST 24	Mar 03 04:00:23 PM PST 24	3720080834 ps
T696	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3184206809			Mar 03 04:11:44 PM PST 24	Mar 03 04:17:14 PM PST 24	3640124632 ps
T154	/workspace/coverage/default/1.chip_sw_edn_auto_mode.4292758212			Mar 03 03:47:44 PM PST 24	Mar 03 04:03:04 PM PST 24	3889234818 ps
T238	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1870647560			Mar 03 03:46:03 PM PST 24	Mar 03 03:47:54 PM PST 24	2168939893 ps
T16	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3175365568			Mar 03 03:44:21 PM PST 24	Mar 03 03:47:51 PM PST 24	3546014568 ps
T94	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1231271903			Mar 03 03:48:49 PM PST 24	Mar 03 04:00:57 PM PST 24	6737879786 ps
T95	/workspace/coverage/default/2.chip_sw_edn_auto_mode.1720163464			Mar 03 03:59:26 PM PST 24	Mar 03 04:16:04 PM PST 24	4391958968 ps
T96	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1978917459			Mar 03 03:47:10 PM PST 24	Mar 03 03:58:18 PM PST 24	5513598072 ps
T97	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1201426009			Mar 03 04:09:55 PM PST 24	Mar 03 04:28:33 PM PST 24	10115087978 ps
T98	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1610532893			Mar 03 03:48:33 PM PST 24	Mar 03 03:52:58 PM PST 24	2801597000 ps
T99	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2576445269			Mar 03 04:01:30 PM PST 24	Mar 03 04:14:18 PM PST 24	4983775371 ps
T100	/workspace/coverage/default/2.chip_sw_uart_tx_rx.882546236			Mar 03 03:54:34 PM PST 24	Mar 03 04:13:17 PM PST 24	6432298088 ps
T101	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1370830936			Mar 03 03:46:39 PM PST 24	Mar 03 05:05:48 PM PST 24	18204574088 ps
T102	/workspace/coverage/default/48.chip_sw_all_escalation_resets.1681183819			Mar 03 04:07:57 PM PST 24	Mar 03 04:20:56 PM PST 24	6016486444 ps
T186	/workspace/coverage/default/2.chip_sw_pattgen_ios.2280998467			Mar 03 03:54:34 PM PST 24	Mar 03 03:58:41 PM PST 24	2023356454 ps
T129	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1639055698			Mar 03 03:45:56 PM PST 24	Mar 03 04:23:31 PM PST 24	21846722900 ps
T902	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1867991653			Mar 03 03:45:19 PM PST 24	Mar 03 03:56:35 PM PST 24	4306606952 ps
T137	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2529824337			Mar 03 03:53:08 PM PST 24	Mar 03 04:46:02 PM PST 24	12463889015 ps
T67	/workspace/coverage/default/2.chip_jtag_mem_access.477863919			Mar 03 03:53:56 PM PST 24	Mar 03 04:22:45 PM PST 24	13047717144 ps
T180	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3666019769			Mar 03 04:07:23 PM PST 24	Mar 03 04:22:27 PM PST 24	6005741322 ps
T337	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3489830355			Mar 03 03:53:25 PM PST 24	Mar 03 04:18:20 PM PST 24	7339910460 ps
T163	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1748491736			Mar 03 03:56:54 PM PST 24	Mar 03 04:03:34 PM PST 24	6058134996 ps
T240	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2204496185			Mar 03 03:49:09 PM PST 24	Mar 03 03:57:03 PM PST 24	4066883159 ps
T68	/workspace/coverage/default/1.chip_tap_straps_rma.3228434445			Mar 03 03:47:48 PM PST 24	Mar 03 03:54:47 PM PST 24	4442884563 ps
T338	/workspace/coverage/default/0.rom_e2e_static_critical.307033390			Mar 03 03:49:42 PM PST 24	Mar 03 04:28:59 PM PST 24	10578548632 ps
T675	/workspace/coverage/default/2.chip_sw_edn_kat.2374528436			Mar 03 03:58:52 PM PST 24	Mar 03 04:09:25 PM PST 24	3485321320 ps
T146	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2652568873			Mar 03 03:46:13 PM PST 24	Mar 03 03:55:25 PM PST 24	5673082060 ps
T15	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2708398304			Mar 03 03:46:57 PM PST 24	Mar 03 04:03:27 PM PST 24	5964630712 ps
T903	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3575701020			Mar 03 03:47:04 PM PST 24	Mar 03 04:05:45 PM PST 24	10749935926 ps
T676	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3076994459			Mar 03 04:07:20 PM PST 24	Mar 03 04:14:08 PM PST 24	3576704072 ps
T904	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1897393974			Mar 03 03:48:16 PM PST 24	Mar 03 04:21:03 PM PST 24	8597039474 ps
T905	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.729264697			Mar 03 03:45:27 PM PST 24	Mar 03 04:05:21 PM PST 24	10563211131 ps
T196	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.275008800			Mar 03 03:45:49 PM PST 24	Mar 03 05:18:08 PM PST 24	50413563525 ps
T25	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.2096203806			Mar 03 03:47:26 PM PST 24	Mar 03 03:52:46 PM PST 24	4076147450 ps
T115	/workspace/coverage/default/26.chip_sw_all_escalation_resets.3740954111			Mar 03 04:08:48 PM PST 24	Mar 03 04:20:33 PM PST 24	5498718640 ps
T182	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.296705956			Mar 03 03:47:22 PM PST 24	Mar 03 03:52:54 PM PST 24	4762616808 ps
T17	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1736857855			Mar 03 03:52:51 PM PST 24	Mar 03 04:00:05 PM PST 24	4692310484 ps
T181	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1434558106			Mar 03 03:48:05 PM PST 24	Mar 03 03:59:08 PM PST 24	6368525796 ps
T200	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1121458810			Mar 03 03:49:23 PM PST 24	Mar 03 03:56:41 PM PST 24	4748424460 ps
T203	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2685339271			Mar 03 04:01:29 PM PST 24	Mar 03 04:07:36 PM PST 24	4465810480 ps
T906	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3326840586			Mar 03 03:46:21 PM PST 24	Mar 03 03:54:56 PM PST 24	7607261540 ps
T192	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1167281768			Mar 03 03:50:36 PM PST 24	Mar 03 03:57:51 PM PST 24	5388611544 ps
T907	/workspace/coverage/default/1.chip_sw_csrng_smoketest.1970562696			Mar 03 03:52:41 PM PST 24	Mar 03 03:56:03 PM PST 24	3013007744 ps
T10	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3182890080			Mar 03 03:47:04 PM PST 24	Mar 03 03:52:37 PM PST 24	3000470908 ps
T908	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2129746831			Mar 03 03:44:24 PM PST 24	Mar 03 03:48:44 PM PST 24	3772469881 ps
T283	/workspace/coverage/default/55.chip_sw_all_escalation_resets.4204047780			Mar 03 04:07:22 PM PST 24	Mar 03 04:16:40 PM PST 24	5222236224 ps
T210	/workspace/coverage/default/0.chip_sw_flash_init.1231538894			Mar 03 03:47:12 PM PST 24	Mar 03 04:25:32 PM PST 24	18219722912 ps
T909	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.203336294			Mar 03 03:44:10 PM PST 24	Mar 03 03:59:47 PM PST 24	5739948424 ps
T910	/workspace/coverage/default/2.chip_sw_example_flash.3921234087			Mar 03 03:54:34 PM PST 24	Mar 03 03:59:45 PM PST 24	3153323560 ps
T46	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2693424464			Mar 03 03:55:54 PM PST 24	Mar 03 04:01:59 PM PST 24	5016829818 ps
T228	/workspace/coverage/default/0.chip_sw_edn_auto_mode.250065286			Mar 03 03:47:52 PM PST 24	Mar 03 04:03:32 PM PST 24	4208233576 ps
T211	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3031940347			Mar 03 03:47:34 PM PST 24	Mar 03 03:55:10 PM PST 24	4078473671 ps
T911	/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2077570528			Mar 03 04:06:14 PM PST 24	Mar 03 05:08:24 PM PST 24	23047625228 ps
T106	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2529568285			Mar 03 03:43:43 PM PST 24	Mar 03 06:43:35 PM PST 24	58083354475 ps
T912	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3710380105			Mar 03 03:48:44 PM PST 24	Mar 03 04:25:37 PM PST 24	8798025790 ps
T913	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.181233417			Mar 03 03:44:15 PM PST 24	Mar 03 03:57:32 PM PST 24	7011050952 ps
T914	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3681076730			Mar 03 03:49:28 PM PST 24	Mar 03 03:53:08 PM PST 24	3005455755 ps
T116	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2175051363			Mar 03 03:46:29 PM PST 24	Mar 03 07:19:47 PM PST 24	254820319280 ps
T195	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2549517486			Mar 03 03:45:33 PM PST 24	Mar 03 04:13:01 PM PST 24	7987673470 ps
T915	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3480239603			Mar 03 04:00:47 PM PST 24	Mar 03 04:13:17 PM PST 24	4190998890 ps
T916	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1600004711			Mar 03 03:47:10 PM PST 24	Mar 03 03:57:13 PM PST 24	4778189200 ps
T264	/workspace/coverage/default/1.chip_plic_all_irqs_20.3492246854			Mar 03 03:46:37 PM PST 24	Mar 03 03:56:01 PM PST 24	4640741810 ps
T329	/workspace/coverage/default/72.chip_sw_all_escalation_resets.945060628			Mar 03 04:12:39 PM PST 24	Mar 03 04:23:21 PM PST 24	5575250070 ps
T287	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1131216759			Mar 03 03:50:33 PM PST 24	Mar 03 03:55:00 PM PST 24	2724307927 ps
T296	/workspace/coverage/default/39.chip_sw_all_escalation_resets.1946541316			Mar 03 04:08:53 PM PST 24	Mar 03 04:18:28 PM PST 24	4320296026 ps
T328	/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2850289266			Mar 03 03:47:34 PM PST 24	Mar 03 03:55:00 PM PST 24	4532884432 ps
T917	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1283372695			Mar 03 03:48:06 PM PST 24	Mar 03 03:54:11 PM PST 24	3685821917 ps
T918	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2113845267			Mar 03 03:49:57 PM PST 24	Mar 03 04:11:29 PM PST 24	7408586262 ps
T919	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1221826314			Mar 03 03:45:47 PM PST 24	Mar 03 03:55:55 PM PST 24	6267304021 ps
T47	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.598654409			Mar 03 03:43:54 PM PST 24	Mar 03 03:51:30 PM PST 24	3940025064 ps
T185	/workspace/coverage/default/1.chip_sw_pattgen_ios.4191524228			Mar 03 03:46:47 PM PST 24	Mar 03 03:50:47 PM PST 24	2734049772 ps
T920	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1519831295			Mar 03 03:59:49 PM PST 24	Mar 03 04:09:00 PM PST 24	4953225088 ps
T204	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2572699311			Mar 03 03:44:01 PM PST 24	Mar 03 03:49:56 PM PST 24	5104297100 ps
T921	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.376081431			Mar 03 03:48:04 PM PST 24	Mar 03 03:51:30 PM PST 24	2949194394 ps
T922	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2538763958			Mar 03 03:57:38 PM PST 24	Mar 03 04:08:06 PM PST 24	5169968075 ps
T213	/workspace/coverage/default/5.chip_sw_all_escalation_resets.1619921591			Mar 03 04:06:32 PM PST 24	Mar 03 04:18:12 PM PST 24	6044089832 ps
T218	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3914687293			Mar 03 04:01:30 PM PST 24	Mar 03 04:11:12 PM PST 24	4839882904 ps
T297	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2779165861			Mar 03 03:46:55 PM PST 24	Mar 03 03:58:53 PM PST 24	4534066856 ps
T923	/workspace/coverage/default/0.chip_sw_uart_tx_rx.4068553734			Mar 03 03:48:30 PM PST 24	Mar 03 04:03:44 PM PST 24	5924512704 ps
T924	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2638288599			Mar 03 03:49:49 PM PST 24	Mar 03 04:43:59 PM PST 24	12122391525 ps
T748	/workspace/coverage/default/1.chip_sw_all_escalation_resets.624350675			Mar 03 03:45:54 PM PST 24	Mar 03 03:57:28 PM PST 24	6026143492 ps
T762	/workspace/coverage/default/97.chip_sw_all_escalation_resets.806631482			Mar 03 04:11:28 PM PST 24	Mar 03 04:20:32 PM PST 24	5633965104 ps
T925	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.4224306458			Mar 03 04:02:30 PM PST 24	Mar 03 04:20:53 PM PST 24	5981024384 ps
T926	/workspace/coverage/default/1.rom_e2e_asm_init_rma.1683458449			Mar 03 03:55:25 PM PST 24	Mar 03 04:30:27 PM PST 24	8119404784 ps
T927	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.363252551			Mar 03 03:47:09 PM PST 24	Mar 03 03:57:39 PM PST 24	4827998516 ps
T63	/workspace/coverage/default/3.chip_tap_straps_rma.824436642			Mar 03 04:02:55 PM PST 24	Mar 03 04:17:12 PM PST 24	8189162301 ps
T697	/workspace/coverage/default/51.chip_sw_all_escalation_resets.4277883134			Mar 03 04:07:51 PM PST 24	Mar 03 04:20:21 PM PST 24	6296382400 ps
T928	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1101059501			Mar 03 04:04:32 PM PST 24	Mar 03 04:14:39 PM PST 24	5672486731 ps
T695	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.2609907525			Mar 03 03:50:35 PM PST 24	Mar 03 04:07:24 PM PST 24	6776588920 ps
T172	/workspace/coverage/default/0.chip_sw_power_idle_load.1939474591			Mar 03 03:47:36 PM PST 24	Mar 03 03:59:14 PM PST 24	4113984140 ps
T241	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.1685589076			Mar 03 03:45:28 PM PST 24	Mar 03 04:00:43 PM PST 24	6380527136 ps
T694	/workspace/coverage/default/65.chip_sw_all_escalation_resets.334334552			Mar 03 04:13:20 PM PST 24	Mar 03 04:23:20 PM PST 24	5556820880 ps
T929	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1474871869			Mar 03 03:46:01 PM PST 24	Mar 03 04:05:23 PM PST 24	5611474927 ps
T294	/workspace/coverage/default/59.chip_sw_all_escalation_resets.537034628			Mar 03 04:07:32 PM PST 24	Mar 03 04:20:28 PM PST 24	4871235000 ps
T930	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3307800855			Mar 03 03:46:13 PM PST 24	Mar 03 04:08:10 PM PST 24	6718073000 ps
T322	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1678395103			Mar 03 03:50:00 PM PST 24	Mar 03 04:38:12 PM PST 24	12363958178 ps
T931	/workspace/coverage/default/1.chip_sw_flash_crash_alert.952464599			Mar 03 03:50:06 PM PST 24	Mar 03 03:59:48 PM PST 24	6690887324 ps
T792	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1671557149			Mar 03 04:12:32 PM PST 24	Mar 03 04:17:44 PM PST 24	3709085464 ps
T161	/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1247708039			Mar 03 03:46:49 PM PST 24	Mar 03 03:58:00 PM PST 24	5240143514 ps
T932	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2032204089			Mar 03 04:04:54 PM PST 24	Mar 03 05:04:02 PM PST 24	23188097040 ps
T751	/workspace/coverage/default/88.chip_sw_all_escalation_resets.1414606562			Mar 03 04:10:44 PM PST 24	Mar 03 04:19:39 PM PST 24	3833664752 ps
T933	/workspace/coverage/default/2.rom_e2e_smoke.743548049			Mar 03 04:03:21 PM PST 24	Mar 03 04:33:40 PM PST 24	8177765488 ps
T934	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1080937028			Mar 03 04:00:48 PM PST 24	Mar 03 04:08:47 PM PST 24	3931140358 ps
T131	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3416969424			Mar 03 03:48:47 PM PST 24	Mar 03 03:50:44 PM PST 24	3313223645 ps
T935	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3066073682			Mar 03 03:45:14 PM PST 24	Mar 03 03:53:09 PM PST 24	3560751800 ps
T738	/workspace/coverage/default/62.chip_sw_all_escalation_resets.3165865577			Mar 03 04:10:11 PM PST 24	Mar 03 04:20:32 PM PST 24	4895575192 ps
T936	/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.295990500			Mar 03 03:49:20 PM PST 24	Mar 03 03:58:42 PM PST 24	4107250044 ps
T937	/workspace/coverage/default/9.chip_sw_all_escalation_resets.3746392587			Mar 03 04:07:18 PM PST 24	Mar 03 04:16:56 PM PST 24	5019799350 ps
T11	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.1293063109			Mar 03 03:50:35 PM PST 24	Mar 03 04:03:09 PM PST 24	5069556983 ps
T938	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2100943817			Mar 03 03:46:08 PM PST 24	Mar 03 04:12:03 PM PST 24	9632472522 ps
T682	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1726278425			Mar 03 03:47:30 PM PST 24	Mar 03 03:49:13 PM PST 24	2136231796 ps
T824	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3926781038			Mar 03 04:07:08 PM PST 24	Mar 03 04:13:05 PM PST 24	3689454928 ps
T939	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.725582751			Mar 03 03:46:12 PM PST 24	Mar 03 03:51:47 PM PST 24	7684662438 ps
T364	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.649195893			Mar 03 03:48:14 PM PST 24	Mar 03 04:04:06 PM PST 24	4640177392 ps
T270	/workspace/coverage/default/1.chip_sival_flash_info_access.2606492983			Mar 03 03:47:11 PM PST 24	Mar 03 03:53:26 PM PST 24	3610103974 ps
T940	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.4027542085			Mar 03 03:46:14 PM PST 24	Mar 03 03:55:51 PM PST 24	7084357688 ps
T941	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.1891000129			Mar 03 03:47:57 PM PST 24	Mar 03 04:08:44 PM PST 24	5724851310 ps
T942	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4145247211			Mar 03 03:57:55 PM PST 24	Mar 03 04:07:53 PM PST 24	6153426248 ps
T18	/workspace/coverage/default/0.chip_sw_usbdev_config_host.1349019867			Mar 03 03:47:56 PM PST 24	Mar 03 04:16:24 PM PST 24	8570932888 ps
T943	/workspace/coverage/default/3.chip_sw_uart_tx_rx.123555005			Mar 03 04:03:28 PM PST 24	Mar 03 04:19:17 PM PST 24	6056001582 ps
T366	/workspace/coverage/default/1.chip_sw_otbn_randomness.3237416664			Mar 03 03:45:44 PM PST 24	Mar 03 04:04:04 PM PST 24	6030061300 ps
T944	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.87265276			Mar 03 03:52:39 PM PST 24	Mar 03 03:57:13 PM PST 24	2737272136 ps
T945	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.4115861808			Mar 03 04:04:26 PM PST 24	Mar 03 04:19:05 PM PST 24	5078752310 ps
T946	/workspace/coverage/default/2.rom_e2e_asm_init_prod.1534789491			Mar 03 04:06:04 PM PST 24	Mar 03 04:38:28 PM PST 24	8521739548 ps
T947	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1971019818			Mar 03 03:47:07 PM PST 24	Mar 03 03:50:54 PM PST 24	2179489766 ps
T828	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2692040676			Mar 03 04:06:17 PM PST 24	Mar 03 04:11:42 PM PST 24	3606665600 ps
T193	/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3646495641			Mar 03 04:01:13 PM PST 24	Mar 03 04:09:31 PM PST 24	4446124924 ps
T948	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1760783297			Mar 03 03:46:02 PM PST 24	Mar 03 03:55:35 PM PST 24	6433544184 ps
T949	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2403116966			Mar 03 03:48:32 PM PST 24	Mar 03 03:55:08 PM PST 24	4263366754 ps
T808	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2927801652			Mar 03 04:09:14 PM PST 24	Mar 03 04:17:22 PM PST 24	3836653384 ps
T950	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2782495924			Mar 03 04:04:23 PM PST 24	Mar 03 04:22:46 PM PST 24	8852830716 ps
T951	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2246125005			Mar 03 03:45:37 PM PST 24	Mar 03 04:24:30 PM PST 24	9873303698 ps
T268	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1330488404			Mar 03 03:45:04 PM PST 24	Mar 03 03:55:54 PM PST 24	4519995848 ps
T12	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.968016948			Mar 03 03:56:47 PM PST 24	Mar 03 04:08:48 PM PST 24	4550509989 ps
T952	/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.95048200			Mar 03 04:04:43 PM PST 24	Mar 03 04:13:33 PM PST 24	5282148969 ps
T351	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3843359096			Mar 03 04:08:53 PM PST 24	Mar 03 04:14:36 PM PST 24	3335443502 ps
T953	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.135954317			Mar 03 03:53:41 PM PST 24	Mar 03 04:51:29 PM PST 24	11542964047 ps
T349	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.237904701			Mar 03 03:59:29 PM PST 24	Mar 03 04:08:13 PM PST 24	9191626983 ps
T954	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.4156710687			Mar 03 03:56:21 PM PST 24	Mar 03 03:59:17 PM PST 24	2769169888 ps
T19	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1655214459			Mar 03 03:46:53 PM PST 24	Mar 03 04:06:52 PM PST 24	19938501080 ps
T955	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3889244625			Mar 03 04:00:00 PM PST 24	Mar 03 04:14:14 PM PST 24	8120749720 ps
T833	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3601259412			Mar 03 04:05:51 PM PST 24	Mar 03 04:13:02 PM PST 24	3768138058 ps
T184	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.733462588			Mar 03 03:45:56 PM PST 24	Mar 03 04:10:13 PM PST 24	9411030948 ps
T763	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2470609094			Mar 03 04:09:17 PM PST 24	Mar 03 04:16:27 PM PST 24	4136875600 ps
T113	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3466199203			Mar 03 03:58:52 PM PST 24	Mar 03 07:22:59 PM PST 24	255045153990 ps
T107	/workspace/coverage/default/1.rom_raw_unlock.928975715			Mar 03 03:52:34 PM PST 24	Mar 03 04:23:42 PM PST 24	14854712528 ps
T956	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3893108725			Mar 03 03:46:29 PM PST 24	Mar 03 04:01:05 PM PST 24	5644453870 ps
T957	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1085961125			Mar 03 03:44:53 PM PST 24	Mar 03 03:57:28 PM PST 24	4451658448 ps
T162	/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1483773903			Mar 03 04:00:54 PM PST 24	Mar 03 04:10:37 PM PST 24	5791384536 ps
T76	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.241587550			Mar 03 04:00:07 PM PST 24	Mar 03 04:25:10 PM PST 24	11629508640 ps
T64	/workspace/coverage/default/3.chip_tap_straps_testunlock0.1757767076			Mar 03 04:08:45 PM PST 24	Mar 03 04:17:56 PM PST 24	6105981883 ps
T958	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3426443423			Mar 03 03:44:01 PM PST 24	Mar 03 04:02:13 PM PST 24	10975521647 ps
T834	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.860615684			Mar 03 04:08:27 PM PST 24	Mar 03 04:16:05 PM PST 24	3557563154 ps
T698	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1386823420			Mar 03 04:12:25 PM PST 24	Mar 03 04:18:13 PM PST 24	3326567180 ps
T365	/workspace/coverage/default/0.chip_sw_kmac_entropy.642355530			Mar 03 03:46:23 PM PST 24	Mar 03 03:50:23 PM PST 24	2424760672 ps
T280	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1867785503			Mar 03 04:06:19 PM PST 24	Mar 03 04:16:53 PM PST 24	4280308376 ps
T156	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3972078911			Mar 03 03:48:00 PM PST 24	Mar 03 03:56:49 PM PST 24	5927608336 ps
T187	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2158361491			Mar 03 03:54:12 PM PST 24	Mar 03 07:31:07 PM PST 24	78209261895 ps
T677	/workspace/coverage/default/1.chip_sw_aes_masking_off.3783943929			Mar 03 03:46:25 PM PST 24	Mar 03 03:50:51 PM PST 24	3202338167 ps
T352	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3313991611			Mar 03 03:48:37 PM PST 24	Mar 03 03:55:57 PM PST 24	4205653556 ps
T142	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1310953313			Mar 03 03:48:32 PM PST 24	Mar 03 04:02:34 PM PST 24	4380985584 ps
T319	/workspace/coverage/default/67.chip_sw_all_escalation_resets.1215306024			Mar 03 04:15:01 PM PST 24	Mar 03 04:24:41 PM PST 24	6235032750 ps
T26	/workspace/coverage/default/1.chip_sw_gpio_smoketest.2892808727			Mar 03 03:52:15 PM PST 24	Mar 03 03:57:19 PM PST 24	2904689947 ps
T959	/workspace/coverage/default/0.chip_sw_example_concurrency.3996289628			Mar 03 03:43:08 PM PST 24	Mar 03 03:46:13 PM PST 24	2360890552 ps
T752	/workspace/coverage/default/41.chip_sw_all_escalation_resets.2973637901			Mar 03 04:06:40 PM PST 24	Mar 03 04:16:58 PM PST 24	4775834068 ps