Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3514	1			T75	1		T470	8		T478	3
all_values[1]	3593	1			T75	2		T367	4		T470	17
all_values[2]	3421	1			T75	3		T470	12		T472	1
all_values[3]	3504	1			T367	1		T470	11		T472	3
all_values[4]	3498	1			T75	2		T367	1		T470	11
all_values[5]	3465	1			T367	1		T470	8		T472	3
all_values[6]	3557	1			T75	2		T470	9		T472	2
all_values[7]	3471	1			T75	2		T470	10		T472	3
all_values[8]	3493	1			T75	3		T367	1		T470	12
all_values[9]	3608	1			T75	4		T367	1		T470	15
all_values[10]	3521	1			T75	1		T367	1		T470	7
all_values[11]	3447	1			T75	4		T367	1		T470	6
all_values[12]	3527	1			T75	5		T470	15		T478	1
all_values[13]	3461	1			T367	2		T470	12		T478	1
all_values[14]	3582	1			T367	5		T470	14		T478	2
all_values[15]	3550	1			T75	2		T367	1		T470	11
all_values[16]	3553	1			T75	4		T367	4		T470	7
all_values[17]	3571	1			T75	2		T367	1		T470	11
all_values[18]	3615	1			T367	4		T470	15		T478	2
all_values[19]	3602	1			T75	1		T367	1		T470	10
all_values[20]	3515	1			T75	2		T367	1		T470	10
all_values[21]	3604	1			T75	2		T367	2		T470	7
all_values[22]	3394	1			T75	3		T367	3		T470	11
all_values[23]	3598	1			T75	3		T470	11		T472	6
all_values[24]	3381	1			T75	3		T470	12		T472	3
all_values[25]	3494	1			T75	1		T470	8		T478	2
all_values[26]	3557	1			T75	1		T367	2		T470	12
all_values[27]	3554	1			T367	1		T470	11		T478	1
all_values[28]	3565	1			T75	4		T470	9		T478	3
all_values[29]	3511	1			T367	1		T470	12		T478	3
all_values[30]	3521	1			T75	4		T367	1		T470	16
all_values[31]	3446	1			T367	2		T470	13		T478	1
all_values[32]	3518	1			T367	2		T470	9		T478	1
all_values[33]	3476	1			T75	2		T367	3		T470	12
all_values[34]	3451	1			T75	1		T367	4		T470	11
all_values[35]	3545	1			T75	2		T367	1		T470	9
all_values[36]	3576	1			T470	9		T478	1		T472	3
all_values[37]	3502	1			T75	4		T470	13		T478	1
all_values[38]	3513	1			T75	1		T367	1		T470	13
all_values[39]	3462	1			T75	1		T367	1		T470	10
all_values[40]	3497	1			T75	1		T367	1		T470	11
all_values[41]	3441	1			T75	2		T470	17		T478	1
all_values[42]	3503	1			T75	2		T367	1		T470	11
all_values[43]	3574	1			T75	2		T470	9		T478	1
all_values[44]	3499	1			T75	1		T367	1		T470	15
all_values[45]	3406	1			T75	5		T367	1		T470	12
all_values[46]	3462	1			T75	3		T470	9		T478	1
all_values[47]	3687	1			T75	1		T367	2		T470	13
all_values[48]	3599	1			T75	1		T367	3		T470	13
all_values[49]	3487	1			T75	2		T367	5		T470	9
all_values[50]	3473	1			T75	1		T470	11		T478	2
all_values[51]	3487	1			T75	2		T367	3		T470	10
all_values[52]	3551	1			T75	4		T367	1		T470	5
all_values[53]	3516	1			T75	2		T367	1		T470	10
all_values[54]	3535	1			T75	1		T367	2		T470	20
all_values[55]	3469	1			T75	3		T367	2		T470	10
all_values[56]	3475	1			T75	2		T367	1		T470	13
all_values[57]	3652	1			T75	2		T367	1		T470	8
all_values[58]	3540	1			T75	2		T367	2		T470	10
all_values[59]	3472	1			T75	1		T470	6		T472	3
all_values[60]	3585	1			T75	3		T367	2		T470	11
all_values[61]	3581	1			T75	5		T367	4		T470	13
all_values[62]	3520	1			T75	4		T367	1		T470	6
all_values[63]	3522	1			T75	3		T470	5		T478	2