Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	144272	1			T77	206		T81	25		T82	142
values[2]	10745	1			T82	2		T491	163		T501	1
values[3]	4247	1			T491	116		T401	60		T572	1
values[4]	2547	1			T491	55		T401	29		T591	18
values[5]	1640	1			T491	35		T401	18		T591	2
values[6]	1127	1			T491	16		T401	8		T458	1
values[7]	789	1			T491	1		T401	7		T751	1
values[8]	592	1			T491	3		T401	6		T751	1
values[9]	446	1			T401	1		T751	1		T748	2
values[10]	364	1			T401	1		T751	1		T748	2
values[11]	297	1			T751	1		T748	2		T760	1
values[12]	291	1			T751	1		T748	2		T760	1
values[13]	297	1			T751	1		T748	2		T760	1
values[14]	250	1			T751	1		T748	2		T760	1
values[15]	262	1			T751	1		T748	2		T760	1
values[16]	294	1			T751	1		T748	2		T760	1
values[17]	244	1			T751	1		T748	2		T760	1
values[18]	230	1			T751	1		T748	2		T760	1
values[19]	241	1			T751	1		T748	2		T760	1
values[20]	232	1			T751	1		T748	2		T760	1
values[21]	316	1			T751	1		T748	2		T760	1
values[22]	269	1			T751	1		T748	2		T760	1
values[23]	245	1			T751	1		T748	2		T760	1
values[24]	227	1			T751	1		T748	2		T760	1
values[25]	259	1			T751	1		T748	2		T760	1
values[26]	232	1			T751	1		T748	2		T760	1
values[27]	259	1			T751	1		T748	2		T760	1
values[28]	254	1			T751	1		T748	2		T760	1
values[29]	291	1			T751	1		T748	2		T760	1
values[30]	200	1			T751	1		T748	2		T760	1
values[31]	236	1			T751	1		T748	2		T760	1
values[32]	270	1			T751	1		T748	2		T760	1
values[33]	261	1			T751	1		T748	2		T760	1
values[34]	253	1			T751	1		T748	2		T760	1
values[35]	288	1			T751	1		T748	2		T760	1
values[36]	256	1			T751	1		T748	2		T760	1
values[37]	243	1			T751	1		T748	2		T760	1
values[38]	215	1			T751	1		T748	2		T760	1
values[39]	241	1			T751	1		T748	2		T760	1
values[40]	237	1			T751	1		T748	2		T760	1
values[41]	222	1			T751	1		T748	2		T760	1
values[42]	254	1			T751	1		T748	2		T760	1
values[43]	226	1			T751	1		T748	2		T760	1
values[44]	218	1			T751	1		T748	2		T760	1
values[45]	233	1			T751	1		T748	2		T760	1
values[46]	252	1			T751	1		T748	2		T760	1
values[47]	213	1			T751	1		T748	2		T760	1
values[48]	242	1			T751	1		T748	2		T760	1
values[49]	269	1			T751	1		T748	2		T760	1
values[50]	263	1			T751	1		T748	2		T760	1
values[51]	238	1			T751	1		T748	2		T760	1
values[52]	201	1			T751	1		T748	2		T760	1
values[53]	198	1			T751	1		T748	2		T760	1
values[54]	180	1			T751	1		T748	2		T760	1
values[55]	231	1			T751	1		T748	2		T760	1
values[56]	200	1			T751	1		T748	2		T760	2
values[57]	206	1			T751	1		T748	2		T760	1
values[58]	197	1			T751	1		T748	2		T760	1
values[59]	199	1			T751	1		T748	2		T760	1
values[60]	200	1			T751	1		T748	2		T760	1
values[61]	172	1			T751	1		T748	2		T760	1
values[62]	194	1			T751	1		T748	2		T760	1
values[63]	244	1			T751	1		T748	2		T760	1
values[64]	213	1			T751	1		T748	2		T760	1
values[65]	203	1			T751	1		T748	2		T760	1
values[66]	255	1			T751	1		T748	2		T760	1
values[67]	193	1			T751	1		T748	2		T760	1
values[68]	156	1			T751	1		T748	2		T760	1
values[69]	162	1			T751	1		T748	2		T760	1
values[70]	149	1			T751	1		T748	2		T760	1
values[71]	135	1			T751	1		T748	2		T760	1
values[72]	132	1			T751	1		T748	2		T760	1
values[73]	110	1			T751	1		T748	2		T760	1
values[74]	80	1			T751	1		T748	2		T760	1
values[75]	78	1			T751	1		T748	2		T760	1
values[76]	67	1			T751	1		T748	2		T760	1
values[77]	95	1			T751	1		T748	2		T760	1
values[78]	108	1			T751	1		T748	2		T760	1
values[79]	65	1			T751	1		T748	2		T760	1
values[80]	78	1			T751	1		T748	2		T760	1
values[81]	98	1			T751	1		T748	2		T760	1
values[82]	74	1			T751	1		T748	2		T760	1
values[83]	74	1			T751	1		T748	2		T760	1
values[84]	65	1			T751	1		T748	2		T760	1
values[85]	82	1			T751	2		T748	2		T760	1
values[86]	75	1			T751	1		T748	2		T760	1
values[87]	71	1			T751	1		T748	2		T760	1
values[88]	83	1			T751	1		T748	2		T760	1
values[89]	88	1			T751	1		T748	2		T760	1
values[90]	80	1			T751	1		T748	2		T760	1
values[91]	79	1			T751	1		T748	2		T760	1
values[92]	97	1			T751	1		T748	3		T760	1
values[93]	95	1			T751	1		T748	2		T760	1
values[94]	84	1			T751	1		T748	2		T760	1
values[95]	94	1			T751	1		T748	2		T760	1
values[96]	91	1			T751	1		T748	2		T760	1
values[97]	70	1			T751	1		T748	2		T760	1
values[98]	71	1			T751	1		T748	4		T760	1
values[99]	74	1			T751	1		T748	2		T760	1
values[100]	80	1			T751	1		T748	3		T760	1
values[101]	72	1			T751	1		T748	2		T760	1
values[102]	97	1			T751	1		T748	4		T760	1
values[103]	98	1			T751	1		T748	4		T760	1
values[104]	84	1			T751	1		T748	8		T760	1
values[105]	86	1			T751	1		T748	2		T760	1
values[106]	74	1			T751	2		T748	7		T760	1
values[107]	72	1			T751	1		T748	3		T760	1
values[108]	76	1			T751	1		T748	2		T760	1
values[109]	95	1			T751	1		T748	4		T760	1
values[110]	84	1			T751	2		T748	8		T760	1
values[111]	102	1			T751	7		T748	4		T760	1
values[112]	93	1			T751	4		T748	3		T760	1
values[113]	89	1			T751	1		T748	4		T760	1
values[114]	95	1			T751	3		T748	4		T760	1
values[115]	77	1			T751	5		T748	3		T760	1
values[116]	71	1			T751	2		T748	3		T760	1
values[117]	74	1			T751	2		T748	3		T760	1
values[118]	88	1			T751	3		T748	5		T760	1
values[119]	79	1			T751	1		T748	7		T760	2
values[120]	63	1			T751	2		T748	4		T760	3
values[121]	85	1			T751	2		T748	7		T760	5
values[122]	84	1			T751	5		T748	3		T760	1
values[123]	86	1			T751	6		T748	3		T760	1
values[124]	65	1			T751	4		T748	3		T760	1
values[125]	81	1			T751	2		T748	3		T760	2
values[126]	141	1			T751	5		T748	12		T760	2
values[127]	994	1			T751	23		T748	62		T760	29
values[128]	8876	1			T751	263		T748	682		T760	272