Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	95.45	94.14	95.17		94.70	97.38	99.55

Total tests in report: 2845

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
38.88	38.88	39.66	39.66	39.61	39.61	35.36	35.36			56.19	56.19	62.11	62.11	0.38	0.38	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2901258812
47.71	8.83	45.28	5.62	51.86	12.25	35.82	0.46			65.44	9.25	86.51	24.40	1.35	0.98	/workspace/coverage/cover_reg_top/15.chip_csr_rw.2386108166
55.31	7.60	58.32	13.04	58.67	6.80	43.63	7.81			67.62	2.17	86.51	0.00	17.11	15.76	/workspace/coverage/cover_reg_top/51.xbar_stress_all.1562431045
60.52	5.21	69.78	11.46	65.97	7.30	46.16	2.52			77.61	9.99	86.51	0.00	17.11	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.575103000
64.07	3.55	76.17	6.39	69.95	3.98	49.53	3.38			79.91	2.30	91.68	5.18	17.16	0.05	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2017727544
67.61	3.54	76.17	0.00	69.95	0.00	49.53	0.00			79.91	0.00	91.68	0.00	38.39	21.23	/workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.729770868
70.39	2.78	76.17	0.00	70.15	0.20	49.53	0.00			79.97	0.07	91.68	0.00	54.82	16.43	/workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.2180588709
72.79	2.41	81.64	5.47	74.10	3.94	53.01	3.47			81.53	1.55	91.68	0.00	54.82	0.00	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3162757389
74.83	2.04	83.60	1.96	76.66	2.56	58.53	5.52			83.35	1.83	92.05	0.37	54.82	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1918944208
76.66	1.83	83.60	0.00	76.66	0.00	69.51	10.98			83.35	0.00	92.05	0.00	54.82	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3063227711
78.29	1.63	83.60	0.00	76.97	0.31	69.51	0.00			83.48	0.13	92.05	0.00	64.14	9.32	/workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.120914619
79.74	1.45	85.86	2.27	79.10	2.13	71.37	1.86			85.92	2.44	92.05	0.00	64.14	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.1579001238
81.09	1.35	87.87	2.00	82.23	3.13	71.68	0.31			88.60	2.67	92.05	0.00	64.14	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1361184585
82.41	1.32	87.87	0.01	82.53	0.30	72.39	0.71			88.63	0.03	92.05	0.00	70.99	6.85	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.263114743
83.66	1.25	87.90	0.03	82.53	0.00	79.88	7.50			88.63	0.00	92.05	0.00	70.99	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3413117543
84.54	0.88	88.65	0.75	82.75	0.23	79.90	0.02			88.85	0.22	96.12	4.07	70.99	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1720607957
85.42	0.87	88.65	0.00	82.75	0.00	79.90	0.00			88.85	0.00	96.12	0.00	76.22	5.23	/workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.1665529706
86.21	0.80	90.01	1.35	83.67	0.91	80.69	0.79			90.15	1.29	96.12	0.00	76.65	0.43	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.810041157
86.97	0.76	90.01	0.00	83.69	0.03	80.69	0.00			90.15	0.00	96.12	0.00	81.18	4.52	/workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.4195534621
87.63	0.66	90.02	0.02	83.73	0.04	82.86	2.17			90.15	0.00	96.12	0.00	82.93	1.75	/workspace/coverage/default/0.chip_sw_alert_test.439229013
88.29	0.66	90.02	0.00	83.88	0.15	82.86	0.00			90.15	0.00	96.12	0.00	86.73	3.81	/workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.4271393262
88.89	0.60	90.02	0.00	84.55	0.68	82.86	0.00			90.33	0.18	96.12	0.00	89.47	2.74	/workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.437846195
89.44	0.55	90.04	0.01	84.56	0.01	86.12	3.26			90.33	0.00	96.12	0.00	89.47	0.00	/workspace/coverage/default/1.chip_sw_edn_auto_mode.3732743883
89.98	0.54	91.07	1.04	85.52	0.96	86.55	0.44			91.15	0.82	96.12	0.00	89.47	0.00	/workspace/coverage/default/0.chip_sw_gpio.4257003321
90.46	0.48	91.07	0.00	85.52	0.00	86.55	0.00			91.15	0.00	96.12	0.00	92.36	2.89	/workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.3634073907
90.90	0.44	91.12	0.05	87.64	2.12	86.57	0.01			91.18	0.02	96.12	0.00	92.78	0.42	/workspace/coverage/cover_reg_top/7.chip_tl_errors.3922599629
91.31	0.41	91.89	0.77	88.44	0.81	86.88	0.32			91.73	0.55	96.12	0.00	92.80	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1110078377
91.71	0.40	92.46	0.57	88.93	0.49	87.68	0.80			92.25	0.52	96.12	0.00	92.80	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.3232784170
92.06	0.35	92.95	0.48	89.34	0.40	88.65	0.97			92.51	0.27	96.12	0.00	92.80	0.00	/workspace/coverage/default/2.chip_jtag_csr_rw.3659425339
92.40	0.34	93.30	0.36	90.03	0.69	88.82	0.18			93.31	0.80	96.12	0.00	92.83	0.04	/workspace/coverage/default/1.chip_jtag_csr_rw.1063378371
92.71	0.31	93.30	0.00	90.03	0.00	88.83	0.01			93.31	0.00	96.12	0.00	94.70	1.87	/workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.3716534166
93.01	0.30	93.30	0.00	90.03	0.00	88.83	0.00			93.31	0.00	96.12	0.00	96.49	1.79	/workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.3719060722
93.19	0.18	93.36	0.05	90.04	0.01	89.85	1.02			93.32	0.01	96.12	0.00	96.49	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2783656725
93.37	0.17	93.65	0.29	90.36	0.33	90.28	0.43			93.32	0.00	96.12	0.00	96.49	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2731707718
93.54	0.17	93.92	0.28	90.87	0.50	90.32	0.05			93.51	0.19	96.12	0.00	96.49	0.00	/workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.1476992201
93.70	0.16	93.92	0.00	90.98	0.11	90.32	0.00			93.53	0.02	96.12	0.00	97.31	0.82	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.1983160331
93.85	0.15	94.01	0.08	91.05	0.07	90.82	0.50			93.58	0.05	96.30	0.18	97.33	0.02	/workspace/coverage/default/6.chip_sw_all_escalation_resets.4152978036
93.98	0.13	94.24	0.24	91.26	0.21	90.82	0.00			93.90	0.32	96.30	0.00	97.33	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1111881926
94.10	0.12	94.50	0.26	91.40	0.15	91.08	0.26			93.95	0.05	96.30	0.00	97.33	0.00	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.52567454
94.21	0.11	94.50	0.00	91.41	0.01	91.08	0.00			93.95	0.00	96.30	0.00	97.99	0.66	/workspace/coverage/cover_reg_top/35.xbar_random_large_delays.2267759804
94.32	0.11	94.50	0.00	91.41	0.00	91.74	0.65			93.95	0.00	96.30	0.00	97.99	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.3853585113
94.42	0.10	94.50	0.00	92.03	0.62	91.74	0.00			93.95	0.00	96.30	0.00	97.99	0.00	/workspace/coverage/cover_reg_top/8.chip_tl_errors.791294240
94.51	0.10	94.52	0.01	92.09	0.07	92.02	0.29			93.97	0.02	96.49	0.18	97.99	0.00	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1632677893
94.60	0.08	94.52	0.00	92.09	0.00	92.52	0.50			93.97	0.00	96.49	0.00	97.99	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2712360768
94.68	0.08	94.55	0.03	92.29	0.19	92.56	0.04			94.19	0.22	96.49	0.00	97.99	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3917218780
94.74	0.06	94.55	0.00	92.29	0.00	92.93	0.38			94.19	0.00	96.49	0.00	97.99	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3897894522
94.80	0.06	94.60	0.05	92.31	0.03	93.18	0.25			94.22	0.02	96.49	0.00	97.99	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.117880130
94.85	0.05	94.60	0.00	92.33	0.02	93.20	0.02			94.22	0.00	96.49	0.00	98.27	0.28	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.3084764020
94.90	0.05	94.66	0.06	92.49	0.16	93.20	0.00			94.31	0.10	96.49	0.00	98.27	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.3221585871
94.95	0.05	94.66	0.00	92.68	0.19	93.20	0.00			94.35	0.03	96.49	0.00	98.33	0.06	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.2147947374
95.00	0.04	94.67	0.01	92.80	0.12	93.20	0.01			94.48	0.13	96.49	0.00	98.33	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3202509384
95.04	0.04	94.67	0.00	92.80	0.00	93.46	0.25			94.48	0.00	96.49	0.00	98.33	0.00	/workspace/coverage/default/0.chip_sw_kmac_entropy.575946732
95.08	0.04	94.67	0.00	92.80	0.00	93.71	0.25			94.48	0.00	96.49	0.00	98.33	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3816651831
95.12	0.04	94.67	0.01	92.81	0.01	93.74	0.03			94.49	0.01	96.67	0.18	98.34	0.01	/workspace/coverage/default/92.chip_sw_all_escalation_resets.4222379661
95.16	0.04	94.69	0.01	92.82	0.01	93.74	0.00			94.51	0.02	96.86	0.18	98.35	0.01	/workspace/coverage/default/3.chip_sw_all_escalation_resets.2172256933
95.20	0.04	94.69	0.00	92.82	0.00	93.97	0.23			94.51	0.00	96.86	0.00	98.35	0.00	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1142040038
95.24	0.04	94.71	0.03	92.83	0.01	93.97	0.01			94.52	0.01	97.04	0.18	98.35	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2813449134
95.28	0.04	94.72	0.01	92.84	0.01	93.97	0.00			94.53	0.01	97.23	0.18	98.37	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.907173401
95.31	0.04	94.72	0.00	92.84	0.01	93.99	0.02			94.53	0.00	97.41	0.18	98.37	0.00	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.3803826163
95.34	0.03	94.72	0.00	92.84	0.00	94.19	0.19			94.53	0.00	97.41	0.00	98.37	0.00	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3939345234
95.37	0.03	94.80	0.08	92.84	0.00	94.27	0.08			94.54	0.01	97.41	0.00	98.37	0.00	/workspace/coverage/default/1.chip_tap_straps_rma.1286829528
95.40	0.03	94.80	0.00	93.00	0.15	94.27	0.00			94.54	0.00	97.41	0.00	98.37	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.4239971067
95.42	0.02	94.83	0.03	93.02	0.03	94.33	0.06			94.56	0.02	97.41	0.00	98.37	0.00	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2936438065
95.44	0.02	94.84	0.01	93.04	0.02	94.41	0.08			94.58	0.02	97.41	0.00	98.37	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.166826728
95.46	0.02	94.89	0.06	93.09	0.05	94.41	0.00			94.60	0.02	97.41	0.00	98.37	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2811036946
95.48	0.02	94.89	0.00	93.10	0.01	94.41	0.00			94.60	0.00	97.41	0.00	98.48	0.12	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.1411119456
95.50	0.02	94.95	0.06	93.15	0.05	94.41	0.00			94.61	0.02	97.41	0.00	98.48	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2718465522
95.52	0.02	95.01	0.05	93.19	0.05	94.41	0.00			94.63	0.02	97.41	0.00	98.48	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.171000382
95.54	0.02	95.01	0.01	93.22	0.03	94.50	0.09			94.63	0.00	97.41	0.00	98.48	0.00	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.903638170
95.56	0.02	95.04	0.03	93.26	0.04	94.52	0.02			94.65	0.02	97.41	0.00	98.48	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.668238180
95.58	0.02	95.04	0.00	93.37	0.11	94.52	0.00			94.65	0.00	97.41	0.00	98.48	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.594459319
95.60	0.02	95.04	0.00	93.38	0.01	94.52	0.00			94.65	0.00	97.41	0.00	98.58	0.09	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.788353826
95.61	0.02	95.04	0.00	93.48	0.09	94.52	0.00			94.65	0.00	97.41	0.00	98.58	0.00	/workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.2815642878
95.63	0.01	95.06	0.02	93.48	0.01	94.57	0.04			94.66	0.01	97.41	0.00	98.58	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.125722907
95.64	0.01	95.06	0.00	93.55	0.07	94.57	0.00			94.66	0.00	97.41	0.00	98.58	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.415269843
95.65	0.01	95.06	0.00	93.57	0.02	94.62	0.05			94.66	0.00	97.41	0.00	98.58	0.00	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.1941615034
95.66	0.01	95.06	0.00	93.57	0.00	94.62	0.00			94.66	0.00	97.41	0.00	98.65	0.07	/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.208978051
95.67	0.01	95.06	0.00	93.59	0.01	94.66	0.04			94.66	0.01	97.41	0.00	98.65	0.00	/workspace/coverage/default/1.rom_e2e_shutdown_output.875502393
95.68	0.01	95.06	0.00	93.59	0.00	94.71	0.05			94.66	0.00	97.41	0.00	98.66	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.2991644999
95.69	0.01	95.08	0.01	93.61	0.02	94.74	0.03			94.66	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2138157187
95.70	0.01	95.08	0.00	93.67	0.06	94.74	0.00			94.66	0.00	97.41	0.00	98.66	0.00	/workspace/coverage/cover_reg_top/15.chip_tl_errors.2435822414
95.71	0.01	95.10	0.03	93.69	0.01	94.74	0.00			94.68	0.02	97.41	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1258740308
95.72	0.01	95.10	0.00	93.69	0.00	94.78	0.04			94.68	0.00	97.41	0.00	98.67	0.01	/workspace/coverage/default/63.chip_sw_all_escalation_resets.4012041203
95.73	0.01	95.10	0.00	93.73	0.05	94.78	0.00			94.68	0.00	97.41	0.00	98.67	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.351616065
95.74	0.01	95.10	0.00	93.73	0.00	94.78	0.00			94.68	0.00	97.41	0.00	98.72	0.05	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.2194697595
95.74	0.01	95.10	0.00	93.77	0.04	94.78	0.00			94.68	0.00	97.41	0.00	98.72	0.00	/workspace/coverage/cover_reg_top/28.chip_tl_errors.428315607
95.75	0.01	95.10	0.00	93.77	0.00	94.82	0.04			94.68	0.00	97.41	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.4275189353
95.76	0.01	95.10	0.00	93.80	0.03	94.82	0.01			94.68	0.00	97.41	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2361186381
95.76	0.01	95.10	0.00	93.83	0.03	94.83	0.01			94.68	0.00	97.41	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1578154518
95.77	0.01	95.10	0.00	93.84	0.01	94.86	0.03			94.68	0.00	97.41	0.00	98.72	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1837382707
95.77	0.01	95.10	0.00	93.84	0.00	94.90	0.03			94.68	0.00	97.41	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.87897442
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95.99	0.01	95.13	0.00	94.06	0.01	95.08	0.00			94.69	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.2912318513
95.99	0.01	95.13	0.00	94.07	0.01	95.08	0.00			94.69	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3934095438
95.99	0.01	95.13	0.00	94.08	0.01	95.08	0.00			94.69	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2999706805
95.99	0.01	95.14	0.01	94.08	0.00	95.08	0.00			94.69	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.3408368061
96.00	0.01	95.15	0.01	94.08	0.00	95.09	0.01			94.69	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/36.chip_sw_all_escalation_resets.1194362991
96.00	0.01	95.15	0.00	94.08	0.00	95.10	0.01			94.69	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3971506196
96.00	0.01	95.15	0.00	94.08	0.00	95.11	0.01			94.69	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2924030377
96.00	0.01	95.15	0.00	94.09	0.01	95.12	0.01			94.69	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc.1943280458
96.00	0.01	95.15	0.01	94.09	0.00	95.12	0.01			94.69	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2187390440
96.00	0.01	95.15	0.00	94.09	0.00	95.12	0.00			94.70	0.01	97.41	0.00	99.55	0.00	/workspace/coverage/default/3.chip_tap_straps_dev.273111847
96.00	0.01	95.15	0.00	94.09	0.01	95.12	0.00			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.3464917890
96.01	0.01	95.15	0.00	94.10	0.01	95.12	0.00			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/42.xbar_same_source.2495035470
96.01	0.01	95.15	0.00	94.11	0.01	95.12	0.00			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3638185254
96.01	0.01	95.15	0.01	94.11	0.01	95.12	0.00			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1368625074
96.01	0.01	95.15	0.00	94.11	0.00	95.13	0.01			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.3491040457
96.01	0.01	95.15	0.00	94.11	0.00	95.14	0.01			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3953111081
96.01	0.01	95.15	0.00	94.11	0.00	95.14	0.01			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.2314959675
96.01	0.01	95.15	0.00	94.11	0.00	95.15	0.01			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1193531427
96.01	0.01	95.15	0.00	94.11	0.00	95.15	0.01			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.499253913
96.01	0.01	95.15	0.00	94.11	0.00	95.16	0.01			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1098216034
96.02	0.01	95.15	0.00	94.11	0.00	95.16	0.01			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3232969211
96.02	0.01	95.15	0.00	94.12	0.01	95.16	0.00			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/16.chip_tl_errors.961933649
96.02	0.01	95.15	0.00	94.12	0.01	95.16	0.00			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/19.chip_tl_errors.3519422692
96.02	0.01	95.15	0.00	94.12	0.01	95.16	0.00			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.2325067084
96.02	0.01	95.15	0.00	94.13	0.01	95.16	0.00			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.1137473511
96.02	0.01	95.15	0.00	94.13	0.01	95.16	0.00			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.3474124926
96.02	0.01	95.15	0.00	94.13	0.01	95.16	0.00			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.3130080923
96.02	0.01	95.15	0.00	94.14	0.01	95.16	0.00			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1851756087
96.02	0.01	95.15	0.00	94.14	0.01	95.16	0.00			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.4013232580
96.02	0.01	95.15	0.00	94.14	0.01	95.16	0.00			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2823794436
96.02	0.01	95.16	0.01	94.14	0.00	95.16	0.00			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1247586153
96.02	0.01	95.16	0.00	94.14	0.00	95.17	0.01			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1902109763
96.02	0.01	95.16	0.00	94.14	0.00	95.17	0.01			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.2158025010
96.02	0.01	95.16	0.00	94.14	0.00	95.17	0.01			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.198564057
96.02	0.01	95.16	0.00	94.14	0.00	95.17	0.01			94.70	0.00	97.41	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3785114376

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.374670057
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2871367658
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1129753291
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.141250331
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3135475073
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.790730522
/workspace/coverage/cover_reg_top/0.chip_tl_errors.3492092918
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.423526104
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3905426062
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.373868527
/workspace/coverage/cover_reg_top/0.xbar_error_random.2904308830
/workspace/coverage/cover_reg_top/0.xbar_random.3946248090
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3801029731
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1992826797
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3359977309
/workspace/coverage/cover_reg_top/0.xbar_same_source.3456237966
/workspace/coverage/cover_reg_top/0.xbar_smoke.534952569
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3605784308
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1738204890
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2362173728
/workspace/coverage/cover_reg_top/0.xbar_stress_all.1226702129
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2412327636
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1343356348
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2502569232
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3351888671
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.4051356067
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3570110843
/workspace/coverage/cover_reg_top/1.chip_csr_rw.3949369736
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.1199869818
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.655148807
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1174474943
/workspace/coverage/cover_reg_top/1.chip_tl_errors.1790131358
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1890561736
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3171681635
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.678860806
/workspace/coverage/cover_reg_top/1.xbar_error_random.106405495
/workspace/coverage/cover_reg_top/1.xbar_random.726524988
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.1916174925
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3059035499
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1205869873
/workspace/coverage/cover_reg_top/1.xbar_same_source.2448628563
/workspace/coverage/cover_reg_top/1.xbar_smoke.2830721079
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.362004309
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.455317249
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1242320183
/workspace/coverage/cover_reg_top/1.xbar_stress_all.1193640267
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.3846925565
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3076567468
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3441307851
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.699055560
/workspace/coverage/cover_reg_top/10.chip_csr_rw.766737287
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.823782859
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.4275344834
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1978774780
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.212613554
/workspace/coverage/cover_reg_top/10.xbar_error_random.1169215951
/workspace/coverage/cover_reg_top/10.xbar_random.2572137451
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1475969176
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2425681891
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.513949477
/workspace/coverage/cover_reg_top/10.xbar_same_source.2070557057
/workspace/coverage/cover_reg_top/10.xbar_smoke.2164318272
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1289505902
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1205032580
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3699990162
/workspace/coverage/cover_reg_top/10.xbar_stress_all.3940747527
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1700271736
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3243694062
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1179254609
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.283055285
/workspace/coverage/cover_reg_top/11.chip_csr_rw.3667867834
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3535653779
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2320637990
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1101282166
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2210944437
/workspace/coverage/cover_reg_top/11.xbar_error_random.3518013173
/workspace/coverage/cover_reg_top/11.xbar_random.1077899849
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3147379485
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.4237113577
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2068323091
/workspace/coverage/cover_reg_top/11.xbar_same_source.589195024
/workspace/coverage/cover_reg_top/11.xbar_smoke.813900541
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.4027224041
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2721649079
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.271224191
/workspace/coverage/cover_reg_top/11.xbar_stress_all.3478667707
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.1228488605
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3514386445
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2048808045
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2491421022
/workspace/coverage/cover_reg_top/12.chip_csr_rw.2917505035
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3607868710
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2314760231
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.2697139889
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2215518687
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.940162728
/workspace/coverage/cover_reg_top/12.xbar_error_random.2498881394
/workspace/coverage/cover_reg_top/12.xbar_random.4284944791
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.285940082
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.971503603
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2223508042
/workspace/coverage/cover_reg_top/12.xbar_same_source.1950027682
/workspace/coverage/cover_reg_top/12.xbar_smoke.4065303678
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.4167830670
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.79332283
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3844398049
/workspace/coverage/cover_reg_top/12.xbar_stress_all.4226734972
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2304988138
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2948439133
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3725579474
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.873166539
/workspace/coverage/cover_reg_top/13.chip_csr_rw.276870740
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.4069662250
/workspace/coverage/cover_reg_top/13.chip_tl_errors.3025388558
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.2618103221
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3146297920
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3679067417
/workspace/coverage/cover_reg_top/13.xbar_error_random.4062439877
/workspace/coverage/cover_reg_top/13.xbar_random.3040333877
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2404451450
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.929149927
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1908756470
/workspace/coverage/cover_reg_top/13.xbar_same_source.3885623138
/workspace/coverage/cover_reg_top/13.xbar_smoke.3930733119
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3505344257
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1638832293
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.158783578
/workspace/coverage/cover_reg_top/13.xbar_stress_all.2499989403
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.2994537880
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1256742315
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1179360800
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2308115859
/workspace/coverage/cover_reg_top/14.chip_csr_rw.106665798
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.2153944567
/workspace/coverage/cover_reg_top/14.chip_tl_errors.3135649588
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.1231579339
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.2169014212
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.384257439
/workspace/coverage/cover_reg_top/14.xbar_error_random.2536891863
/workspace/coverage/cover_reg_top/14.xbar_random.173842685
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.2515263929
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1882577949
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.746164644
/workspace/coverage/cover_reg_top/14.xbar_same_source.509277913
/workspace/coverage/cover_reg_top/14.xbar_smoke.4199856095
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.3182622473
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.588796585
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.45965042
/workspace/coverage/cover_reg_top/14.xbar_stress_all.1198553338
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.162626570
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3344749733
/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.1911857132
/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.3707613600
/workspace/coverage/cover_reg_top/15.xbar_access_same_device.1305354193
/workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3324542254
/workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.4098157183
/workspace/coverage/cover_reg_top/15.xbar_error_random.1966315442
/workspace/coverage/cover_reg_top/15.xbar_random.2994101745
/workspace/coverage/cover_reg_top/15.xbar_random_large_delays.3063457657
/workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.3662749545
/workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.2603001589
/workspace/coverage/cover_reg_top/15.xbar_same_source.1074631601
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/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.863289221
/workspace/coverage/default/4.chip_sw_all_escalation_resets.581465247
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1494784728
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1361335270
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.468990072
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.656698952
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.18833535
/workspace/coverage/default/4.chip_sw_uart_tx_rx.1572338245
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3116547035
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2077264315
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1388087174
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.282707969
/workspace/coverage/default/4.chip_tap_straps_dev.1785488173
/workspace/coverage/default/4.chip_tap_straps_prod.3052896682
/workspace/coverage/default/4.chip_tap_straps_rma.3676853501
/workspace/coverage/default/4.chip_tap_straps_testunlock0.2215838728
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.367986626
/workspace/coverage/default/40.chip_sw_all_escalation_resets.2667883072
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2541043564
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.665668133
/workspace/coverage/default/42.chip_sw_all_escalation_resets.2585829106
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2646833086
/workspace/coverage/default/45.chip_sw_all_escalation_resets.3662623573
/workspace/coverage/default/46.chip_sw_all_escalation_resets.4094818008
/workspace/coverage/default/48.chip_sw_all_escalation_resets.2740230957
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.403930067
/workspace/coverage/default/5.chip_sw_all_escalation_resets.3055148291
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2161525967
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.735254230
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1503604601
/workspace/coverage/default/51.chip_sw_all_escalation_resets.1736236869
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2332075947
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3435530104
/workspace/coverage/default/53.chip_sw_all_escalation_resets.800784989
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3292926275
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3243002605
/workspace/coverage/default/56.chip_sw_all_escalation_resets.1847359152
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1811175165
/workspace/coverage/default/58.chip_sw_all_escalation_resets.718516314
/workspace/coverage/default/59.chip_sw_all_escalation_resets.1681588212
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3808371609
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3056068212
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.450981674
/workspace/coverage/default/60.chip_sw_all_escalation_resets.948859881
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.4159260397
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3572606091
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3540702260
/workspace/coverage/default/64.chip_sw_all_escalation_resets.1134146344
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.574422150
/workspace/coverage/default/65.chip_sw_all_escalation_resets.4218382765
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.913962429
/workspace/coverage/default/66.chip_sw_all_escalation_resets.4282838024
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3155655205
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3334371591
/workspace/coverage/default/69.chip_sw_all_escalation_resets.747058807
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.4219610682
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.393970383
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1204433295
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3868973111
/workspace/coverage/default/70.chip_sw_all_escalation_resets.2147681940
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.362522463
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2566776176
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2606937331
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3112623434
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.783037209
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1637197133
/workspace/coverage/default/75.chip_sw_all_escalation_resets.4070546388
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3306739368
/workspace/coverage/default/76.chip_sw_all_escalation_resets.3085818045
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2638518003
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3703646322
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1406240637
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3674068424
/workspace/coverage/default/79.chip_sw_all_escalation_resets.3453191564
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3755245519
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2646234589
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1337076917
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.4028191386
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1424930891
/workspace/coverage/default/80.chip_sw_all_escalation_resets.880110500
/workspace/coverage/default/81.chip_sw_all_escalation_resets.570615268
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3403952249
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1177588590
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2871445885
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1215157358
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1954138899
/workspace/coverage/default/84.chip_sw_all_escalation_resets.473853515
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3259487277
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.562671864
/workspace/coverage/default/86.chip_sw_all_escalation_resets.389977930
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.130732909
/workspace/coverage/default/87.chip_sw_all_escalation_resets.1119963527
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.473681132
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3105439056
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.282448465
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1744482971
/workspace/coverage/default/9.chip_sw_all_escalation_resets.2939739483
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3299151624
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3116560862
/workspace/coverage/default/90.chip_sw_all_escalation_resets.1003768931
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2331005848
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2972209068
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1581371821
/workspace/coverage/default/95.chip_sw_all_escalation_resets.519582051
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1322842666
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3657205331
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1005882522
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1163254743
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.622246216
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3103448921
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1791230621
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.4110875335
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1887036602
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2033982317
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1333973645
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2722724732

---

Total test records in report: 2845

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tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/0.chip_sw_aon_timer_irq.832661506			Mar 05 03:50:52 PM PST 24	Mar 05 03:56:43 PM PST 24	4043794274 ps
T2	/workspace/coverage/default/0.chip_sw_usbdev_vbus.3088530980			Mar 05 03:49:23 PM PST 24	Mar 05 03:53:26 PM PST 24	2736442056 ps
T3	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3785114376			Mar 05 03:52:57 PM PST 24	Mar 05 03:56:17 PM PST 24	2747334050 ps
T59	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2339041161			Mar 05 03:54:59 PM PST 24	Mar 05 04:01:12 PM PST 24	3746558920 ps
T60	/workspace/coverage/default/0.chip_sw_power_idle_load.2736671076			Mar 05 03:53:34 PM PST 24	Mar 05 04:03:35 PM PST 24	4646753172 ps
T32	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2901258812			Mar 05 04:12:19 PM PST 24	Mar 05 04:20:39 PM PST 24	5116195430 ps
T43	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1918944208			Mar 05 03:57:59 PM PST 24	Mar 05 04:37:43 PM PST 24	8412143646 ps
T86	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.903638170			Mar 05 04:17:12 PM PST 24	Mar 05 04:28:08 PM PST 24	4671169200 ps
T87	/workspace/coverage/default/2.chip_sw_rv_timer_irq.1956442758			Mar 05 04:07:36 PM PST 24	Mar 05 04:11:51 PM PST 24	2798331704 ps
T88	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.4180696918			Mar 05 04:00:58 PM PST 24	Mar 05 04:06:06 PM PST 24	2760546070 ps
T64	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1110078377			Mar 05 03:58:33 PM PST 24	Mar 05 04:05:11 PM PST 24	3152154868 ps
T65	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.3177752073			Mar 05 04:12:11 PM PST 24	Mar 05 04:27:46 PM PST 24	6806403132 ps
T175	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1801315883			Mar 05 04:15:58 PM PST 24	Mar 05 04:20:46 PM PST 24	2645132444 ps
T33	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1737568267			Mar 05 03:59:40 PM PST 24	Mar 05 04:07:23 PM PST 24	3966187892 ps
T34	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3816651831			Mar 05 03:50:27 PM PST 24	Mar 05 04:01:28 PM PST 24	5400665662 ps
T16	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2017727544			Mar 05 04:12:13 PM PST 24	Mar 05 04:20:12 PM PST 24	7700654780 ps
T67	/workspace/coverage/default/63.chip_sw_all_escalation_resets.4012041203			Mar 05 04:23:27 PM PST 24	Mar 05 04:34:49 PM PST 24	5379280156 ps
T68	/workspace/coverage/default/71.chip_sw_all_escalation_resets.2566776176			Mar 05 04:24:18 PM PST 24	Mar 05 04:36:30 PM PST 24	4860542000 ps
T107	/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.157129757			Mar 05 03:50:59 PM PST 24	Mar 05 07:39:08 PM PST 24	255465830682 ps
T108	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.232609808			Mar 05 04:21:55 PM PST 24	Mar 05 04:29:55 PM PST 24	3778695256 ps
T109	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3536501369			Mar 05 03:55:59 PM PST 24	Mar 05 04:07:12 PM PST 24	3799689491 ps
T110	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.665668133			Mar 05 04:23:17 PM PST 24	Mar 05 04:29:04 PM PST 24	3879309556 ps
T111	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3676071353			Mar 05 04:06:06 PM PST 24	Mar 05 04:19:42 PM PST 24	4522260320 ps
T44	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1570020288			Mar 05 04:20:44 PM PST 24	Mar 05 04:52:51 PM PST 24	9128999022 ps
T112	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2328367350			Mar 05 04:16:20 PM PST 24	Mar 05 05:17:32 PM PST 24	23058801488 ps
T172	/workspace/coverage/default/0.chip_sw_all_escalation_resets.1909408411			Mar 05 03:48:51 PM PST 24	Mar 05 03:59:07 PM PST 24	5998446208 ps
T141	/workspace/coverage/default/6.chip_sw_all_escalation_resets.4152978036			Mar 05 04:18:36 PM PST 24	Mar 05 04:30:36 PM PST 24	5957102632 ps
T123	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.153745199			Mar 05 03:48:58 PM PST 24	Mar 05 04:15:43 PM PST 24	9285805816 ps
T4	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3939345234			Mar 05 04:12:42 PM PST 24	Mar 05 04:15:11 PM PST 24	2972441207 ps
T184	/workspace/coverage/default/1.chip_sw_pattgen_ios.2379393308			Mar 05 03:56:01 PM PST 24	Mar 05 04:00:25 PM PST 24	2588584656 ps
T173	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.629159703			Mar 05 04:12:15 PM PST 24	Mar 05 04:18:13 PM PST 24	5020228216 ps
T152	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2936438065			Mar 05 04:16:14 PM PST 24	Mar 05 05:20:25 PM PST 24	22866930499 ps
T174	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.18275828			Mar 05 03:51:59 PM PST 24	Mar 05 04:04:18 PM PST 24	4140315408 ps
T13	/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3116560862			Mar 05 04:18:49 PM PST 24	Mar 05 04:30:04 PM PST 24	4529100592 ps
T20	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.117880130			Mar 05 03:58:12 PM PST 24	Mar 05 04:23:23 PM PST 24	21622454006 ps
T410	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3435530104			Mar 05 04:22:52 PM PST 24	Mar 05 04:28:13 PM PST 24	3685222510 ps
T643	/workspace/coverage/default/1.chip_sw_uart_smoketest.291284862			Mar 05 04:06:10 PM PST 24	Mar 05 04:11:56 PM PST 24	3017276756 ps
T290	/workspace/coverage/default/1.chip_sw_hmac_enc.3551510034			Mar 05 03:59:53 PM PST 24	Mar 05 04:05:23 PM PST 24	2665901312 ps
T137	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2680676914			Mar 05 04:00:40 PM PST 24	Mar 05 04:05:49 PM PST 24	3471255898 ps
T822	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3390283072			Mar 05 03:57:21 PM PST 24	Mar 05 04:03:46 PM PST 24	3840322254 ps
T155	/workspace/coverage/default/1.chip_sw_edn_boot_mode.58491442			Mar 05 03:58:20 PM PST 24	Mar 05 04:06:54 PM PST 24	3040485512 ps
T132	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3941445426			Mar 05 03:51:30 PM PST 24	Mar 05 04:02:12 PM PST 24	4450563620 ps
T14	/workspace/coverage/default/0.chip_sw_gpio.4257003321			Mar 05 03:49:00 PM PST 24	Mar 05 03:56:54 PM PST 24	3940983172 ps
T73	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3510584777			Mar 05 04:12:26 PM PST 24	Mar 05 04:22:24 PM PST 24	4327674370 ps
T72	/workspace/coverage/default/2.chip_tap_straps_testunlock0.2737184324			Mar 05 04:12:32 PM PST 24	Mar 05 04:18:14 PM PST 24	3733704636 ps
T409	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3306739368			Mar 05 04:24:05 PM PST 24	Mar 05 04:31:08 PM PST 24	4108602716 ps
T113	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3971506196			Mar 05 03:52:33 PM PST 24	Mar 05 04:52:45 PM PST 24	24704429843 ps
T204	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2176799526			Mar 05 03:52:34 PM PST 24	Mar 05 04:03:31 PM PST 24	5428598316 ps
T45	/workspace/coverage/default/2.chip_sw_uart_smoketest_signed.1676931083			Mar 05 04:17:57 PM PST 24	Mar 05 04:50:29 PM PST 24	8442193604 ps
T121	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.810041157			Mar 05 04:07:11 PM PST 24	Mar 05 04:36:37 PM PST 24	12193215070 ps
T185	/workspace/coverage/default/2.chip_sw_pattgen_ios.4220462810			Mar 05 04:09:19 PM PST 24	Mar 05 04:14:37 PM PST 24	2699212840 ps
T205	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3063227711			Mar 05 04:09:22 PM PST 24	Mar 05 04:19:32 PM PST 24	4643062624 ps
T614	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3755245519			Mar 05 04:18:44 PM PST 24	Mar 05 04:25:57 PM PST 24	3929499370 ps
T416	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3934085507			Mar 05 04:04:56 PM PST 24	Mar 05 04:25:50 PM PST 24	5968981968 ps
T823	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.281321133			Mar 05 04:05:50 PM PST 24	Mar 05 04:10:07 PM PST 24	2317754986 ps
T418	/workspace/coverage/default/0.chip_sw_kmac_entropy.575946732			Mar 05 03:49:50 PM PST 24	Mar 05 03:54:05 PM PST 24	3375466532 ps
T151	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.361740053			Mar 05 04:13:23 PM PST 24	Mar 05 04:22:18 PM PST 24	4091301725 ps
T824	/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2491031526			Mar 05 04:06:40 PM PST 24	Mar 05 04:13:48 PM PST 24	5692492732 ps
T372	/workspace/coverage/default/1.rom_e2e_smoke.3781803138			Mar 05 04:05:05 PM PST 24	Mar 05 04:37:51 PM PST 24	8550480650 ps
T825	/workspace/coverage/default/0.chip_sw_example_rom.1827277554			Mar 05 03:50:02 PM PST 24	Mar 05 03:52:21 PM PST 24	2637970980 ps
T826	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.4010090070			Mar 05 04:01:32 PM PST 24	Mar 05 04:08:00 PM PST 24	3055673992 ps
T17	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.361926241			Mar 05 03:49:03 PM PST 24	Mar 05 03:56:23 PM PST 24	3594203750 ps
T630	/workspace/coverage/default/1.chip_sw_aes_enc.2314920065			Mar 05 03:59:27 PM PST 24	Mar 05 04:04:24 PM PST 24	2879960180 ps
T354	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.473681132			Mar 05 04:25:30 PM PST 24	Mar 05 04:33:14 PM PST 24	3950492976 ps
T179	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.1834867112			Mar 05 03:58:14 PM PST 24	Mar 05 04:03:37 PM PST 24	3468793511 ps
T611	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3540702260			Mar 05 04:22:17 PM PST 24	Mar 05 04:26:55 PM PST 24	3212508928 ps
T827	/workspace/coverage/default/1.chip_sw_kmac_smoketest.546510716			Mar 05 04:05:36 PM PST 24	Mar 05 04:10:20 PM PST 24	2696839090 ps
T612	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3575924299			Mar 05 03:51:03 PM PST 24	Mar 05 03:57:05 PM PST 24	4344532790 ps
T18	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.601702060			Mar 05 04:05:18 PM PST 24	Mar 05 04:14:04 PM PST 24	4640407584 ps
T711	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1954138899			Mar 05 04:24:18 PM PST 24	Mar 05 04:29:59 PM PST 24	3764580940 ps
T120	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1748538790			Mar 05 04:20:55 PM PST 24	Mar 05 04:27:32 PM PST 24	3619629896 ps
T310	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.4277973313			Mar 05 03:58:31 PM PST 24	Mar 05 04:03:00 PM PST 24	2934063978 ps
T202	/workspace/coverage/default/44.chip_sw_all_escalation_resets.404947386			Mar 05 04:23:02 PM PST 24	Mar 05 04:30:50 PM PST 24	5058855212 ps
T308	/workspace/coverage/default/54.chip_sw_all_escalation_resets.2221105268			Mar 05 04:22:35 PM PST 24	Mar 05 04:33:55 PM PST 24	5483476620 ps
T828	/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3103186636			Mar 05 04:14:21 PM PST 24	Mar 05 04:17:58 PM PST 24	2831799000 ps
T142	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.780627790			Mar 05 04:01:23 PM PST 24	Mar 05 04:11:46 PM PST 24	7839997838 ps
T5	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.186814384			Mar 05 04:00:16 PM PST 24	Mar 05 04:51:30 PM PST 24	11583477144 ps
T829	/workspace/coverage/default/0.chip_sw_kmac_idle.3711561374			Mar 05 03:51:25 PM PST 24	Mar 05 03:55:15 PM PST 24	2309478694 ps
T193	/workspace/coverage/default/2.rom_keymgr_functest.1599024234			Mar 05 04:16:07 PM PST 24	Mar 05 04:25:36 PM PST 24	4409282276 ps
T830	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2631448422			Mar 05 03:51:39 PM PST 24	Mar 05 03:56:56 PM PST 24	3040418828 ps
T615	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.944312904			Mar 05 04:03:36 PM PST 24	Mar 05 04:25:54 PM PST 24	8140815380 ps
T21	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1738277778			Mar 05 03:50:11 PM PST 24	Mar 05 04:22:28 PM PST 24	21688865672 ps
T203	/workspace/coverage/default/24.chip_sw_all_escalation_resets.960321658			Mar 05 04:19:50 PM PST 24	Mar 05 04:30:29 PM PST 24	4749480746 ps
T631	/workspace/coverage/default/2.chip_sw_hmac_smoketest.3955330110			Mar 05 04:14:50 PM PST 24	Mar 05 04:19:07 PM PST 24	2638715292 ps
T15	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.3156893138			Mar 05 03:48:35 PM PST 24	Mar 05 04:03:50 PM PST 24	5260315856 ps
T610	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3357581536			Mar 05 04:22:00 PM PST 24	Mar 05 04:28:21 PM PST 24	3130661084 ps
T6	/workspace/coverage/default/1.rom_raw_unlock.3360948670			Mar 05 04:05:11 PM PST 24	Mar 05 04:43:39 PM PST 24	14800536151 ps
T613	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1593000415			Mar 05 03:57:07 PM PST 24	Mar 05 04:07:14 PM PST 24	5013890452 ps
T66	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.468990072			Mar 05 04:15:55 PM PST 24	Mar 05 04:22:40 PM PST 24	5778695727 ps
T181	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1204433295			Mar 05 04:18:11 PM PST 24	Mar 05 04:31:26 PM PST 24	5548429820 ps
T406	/workspace/coverage/default/2.chip_sw_kmac_app_rom.4071698557			Mar 05 04:11:19 PM PST 24	Mar 05 04:16:12 PM PST 24	2432589148 ps
T373	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.358666461			Mar 05 03:59:09 PM PST 24	Mar 05 04:33:42 PM PST 24	8659198534 ps
T322	/workspace/coverage/default/82.chip_sw_all_escalation_resets.1177588590			Mar 05 04:25:51 PM PST 24	Mar 05 04:35:26 PM PST 24	5868863400 ps
T114	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.127425709			Mar 05 03:58:40 PM PST 24	Mar 05 04:57:07 PM PST 24	17974515276 ps
T83	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.3853585113			Mar 05 03:49:59 PM PST 24	Mar 05 03:56:56 PM PST 24	3846753232 ps
T304	/workspace/coverage/default/18.chip_sw_all_escalation_resets.672329255			Mar 05 04:18:04 PM PST 24	Mar 05 04:28:56 PM PST 24	4871804676 ps
T489	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1633909032			Mar 05 03:51:40 PM PST 24	Mar 05 04:03:06 PM PST 24	6684719444 ps
T831	/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1562183362			Mar 05 03:56:00 PM PST 24	Mar 05 04:01:21 PM PST 24	2760038000 ps
T47	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3537729704			Mar 05 03:51:39 PM PST 24	Mar 05 03:58:09 PM PST 24	4093323032 ps
T156	/workspace/coverage/default/1.chip_sw_edn_auto_mode.3732743883			Mar 05 04:00:43 PM PST 24	Mar 05 04:12:45 PM PST 24	3436603530 ps
T225	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1013082064			Mar 05 03:49:49 PM PST 24	Mar 05 04:21:58 PM PST 24	12501442518 ps
T41	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.356072918			Mar 05 03:59:14 PM PST 24	Mar 05 04:41:32 PM PST 24	11762739886 ps
T227	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2966435097			Mar 05 04:20:49 PM PST 24	Mar 05 04:27:17 PM PST 24	3305286770 ps
T270	/workspace/coverage/default/2.chip_plic_all_irqs_20.575103000			Mar 05 04:12:08 PM PST 24	Mar 05 04:25:27 PM PST 24	4759268504 ps
T271	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.4219610682			Mar 05 04:20:01 PM PST 24	Mar 05 04:26:45 PM PST 24	3981228500 ps
T74	/workspace/coverage/default/0.chip_tap_straps_testunlock0.515800193			Mar 05 03:52:06 PM PST 24	Mar 05 04:01:48 PM PST 24	5126236335 ps
T272	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1442138610			Mar 05 03:51:55 PM PST 24	Mar 05 03:59:14 PM PST 24	4592257894 ps
T199	/workspace/coverage/default/89.chip_sw_all_escalation_resets.1376832494			Mar 05 04:24:50 PM PST 24	Mar 05 04:34:08 PM PST 24	5797638724 ps
T157	/workspace/coverage/default/0.chip_sw_edn_boot_mode.2314959675			Mar 05 03:51:26 PM PST 24	Mar 05 04:00:00 PM PST 24	2848613688 ps
T246	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3751919243			Mar 05 04:00:41 PM PST 24	Mar 05 04:09:18 PM PST 24	9390169618 ps
T273	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1389171349			Mar 05 04:06:11 PM PST 24	Mar 05 04:31:26 PM PST 24	7481678376 ps
T171	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.382060208			Mar 05 03:51:46 PM PST 24	Mar 05 03:59:32 PM PST 24	5357870081 ps
T620	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.772095277			Mar 05 04:07:22 PM PST 24	Mar 05 04:39:56 PM PST 24	23877111846 ps
T323	/workspace/coverage/default/47.chip_sw_all_escalation_resets.1579064658			Mar 05 04:21:19 PM PST 24	Mar 05 04:29:06 PM PST 24	5275302220 ps
T368	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.574422150			Mar 05 04:23:05 PM PST 24	Mar 05 04:29:32 PM PST 24	3879337146 ps
T707	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2111026911			Mar 05 04:18:44 PM PST 24	Mar 05 04:24:45 PM PST 24	3439100640 ps
T69	/workspace/coverage/default/1.chip_tap_straps_rma.1286829528			Mar 05 04:02:03 PM PST 24	Mar 05 04:04:27 PM PST 24	2767904149 ps
T127	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2783656725			Mar 05 04:07:22 PM PST 24	Mar 05 05:26:32 PM PST 24	48682121662 ps
T832	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1510197035			Mar 05 03:56:53 PM PST 24	Mar 05 04:07:29 PM PST 24	4480873794 ps
T641	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3685718519			Mar 05 03:59:49 PM PST 24	Mar 05 04:21:53 PM PST 24	13739822286 ps
T407	/workspace/coverage/default/1.chip_sw_kmac_app_rom.457162552			Mar 05 04:00:55 PM PST 24	Mar 05 04:05:00 PM PST 24	3189722524 ps
T309	/workspace/coverage/default/87.chip_sw_all_escalation_resets.1119963527			Mar 05 04:25:02 PM PST 24	Mar 05 04:35:01 PM PST 24	4153429486 ps
T128	/workspace/coverage/default/2.rom_volatile_raw_unlock.3857992088			Mar 05 04:15:39 PM PST 24	Mar 05 04:17:25 PM PST 24	1805281340 ps
T287	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2361186381			Mar 05 03:50:02 PM PST 24	Mar 05 04:02:49 PM PST 24	4396915062 ps
T176	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.4028191386			Mar 05 04:19:44 PM PST 24	Mar 05 04:54:47 PM PST 24	13067624248 ps
T117	/workspace/coverage/default/0.chip_plic_all_irqs_10.3232784170			Mar 05 03:54:29 PM PST 24	Mar 05 04:05:21 PM PST 24	4105619024 ps
T833	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2579144636			Mar 05 03:50:57 PM PST 24	Mar 05 03:57:49 PM PST 24	3613364360 ps
T19	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2619688952			Mar 05 04:01:50 PM PST 24	Mar 05 04:31:22 PM PST 24	19083559280 ps
T597	/workspace/coverage/default/2.chip_sw_aes_masking_off.349481901			Mar 05 04:09:11 PM PST 24	Mar 05 04:14:36 PM PST 24	2673880363 ps
T189	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3576431336			Mar 05 03:54:41 PM PST 24	Mar 05 05:19:19 PM PST 24	23060040683 ps
T180	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3152703348			Mar 05 03:56:55 PM PST 24	Mar 05 04:06:09 PM PST 24	4255890085 ps
T61	/workspace/coverage/default/2.chip_jtag_csr_rw.3659425339			Mar 05 04:04:49 PM PST 24	Mar 05 04:36:07 PM PST 24	17558999560 ps
T26	/workspace/coverage/default/0.chip_sw_gpio_smoketest.2334579695			Mar 05 03:54:22 PM PST 24	Mar 05 03:59:52 PM PST 24	2553672784 ps
T605	/workspace/coverage/default/2.chip_sw_power_idle_load.3093936762			Mar 05 04:13:14 PM PST 24	Mar 05 04:24:51 PM PST 24	4410112696 ps
T122	/workspace/coverage/default/29.chip_sw_all_escalation_resets.1885302144			Mar 05 04:20:39 PM PST 24	Mar 05 04:28:26 PM PST 24	4571264450 ps
T153	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4243797878			Mar 05 04:01:24 PM PST 24	Mar 05 04:11:34 PM PST 24	3873027256 ps
T190	/workspace/coverage/default/3.chip_tap_straps_dev.273111847			Mar 05 04:15:21 PM PST 24	Mar 05 04:30:03 PM PST 24	10468372575 ps
T194	/workspace/coverage/default/25.chip_sw_all_escalation_resets.4154046833			Mar 05 04:19:12 PM PST 24	Mar 05 04:29:07 PM PST 24	5794268852 ps
T834	/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.18833535			Mar 05 04:16:43 PM PST 24	Mar 05 04:52:33 PM PST 24	14177281384 ps
T642	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3478935710			Mar 05 04:07:38 PM PST 24	Mar 05 04:36:09 PM PST 24	13033664194 ps
T712	/workspace/coverage/default/45.chip_sw_all_escalation_resets.3662623573			Mar 05 04:21:20 PM PST 24	Mar 05 04:34:35 PM PST 24	5737176398 ps
T619	/workspace/coverage/default/99.chip_sw_all_escalation_resets.1163254743			Mar 05 04:25:59 PM PST 24	Mar 05 04:36:53 PM PST 24	6190060164 ps
T315	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.4130241469			Mar 05 03:51:58 PM PST 24	Mar 05 03:56:58 PM PST 24	3078007615 ps
T835	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3252002980			Mar 05 04:15:45 PM PST 24	Mar 05 04:20:30 PM PST 24	3884776615 ps
T660	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2646833086			Mar 05 04:21:26 PM PST 24	Mar 05 04:28:08 PM PST 24	3930660962 ps
T358	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.39842712			Mar 05 04:12:36 PM PST 24	Mar 05 04:17:07 PM PST 24	2854587740 ps
T143	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1632677893			Mar 05 04:15:48 PM PST 24	Mar 05 04:24:30 PM PST 24	4139660327 ps
T262	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1346415361			Mar 05 04:23:17 PM PST 24	Mar 05 04:29:11 PM PST 24	3902484948 ps
T263	/workspace/coverage/default/1.chip_sw_example_concurrency.851732292			Mar 05 03:54:24 PM PST 24	Mar 05 03:58:15 PM PST 24	3221134026 ps
T264	/workspace/coverage/default/65.chip_sw_all_escalation_resets.4218382765			Mar 05 04:23:23 PM PST 24	Mar 05 04:35:15 PM PST 24	6078451800 ps
T42	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.731590815			Mar 05 03:58:33 PM PST 24	Mar 05 04:28:28 PM PST 24	8390407866 ps
T265	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2917385764			Mar 05 03:58:59 PM PST 24	Mar 05 04:03:26 PM PST 24	2810703432 ps
T7	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1361184585			Mar 05 04:05:15 PM PST 24	Mar 05 04:10:40 PM PST 24	3149621916 ps
T140	/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.393970383			Mar 05 04:18:35 PM PST 24	Mar 05 04:26:42 PM PST 24	5372741291 ps
T46	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1282644097			Mar 05 04:03:22 PM PST 24	Mar 05 04:21:21 PM PST 24	17826604904 ps
T266	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3283187039			Mar 05 03:50:35 PM PST 24	Mar 05 03:55:28 PM PST 24	3549408258 ps
T836	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.4187321944			Mar 05 04:10:48 PM PST 24	Mar 05 04:15:33 PM PST 24	2297709408 ps
T321	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2497441192			Mar 05 03:56:25 PM PST 24	Mar 05 04:04:33 PM PST 24	3666782080 ps
T837	/workspace/coverage/default/0.chip_tap_straps_dev.1805496311			Mar 05 03:50:24 PM PST 24	Mar 05 03:55:28 PM PST 24	4328320533 ps
T617	/workspace/coverage/default/22.chip_sw_all_escalation_resets.720170963			Mar 05 04:18:32 PM PST 24	Mar 05 04:28:36 PM PST 24	5954615028 ps
T838	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1283298502			Mar 05 03:57:11 PM PST 24	Mar 05 04:07:43 PM PST 24	4635698608 ps
T616	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1390489409			Mar 05 04:24:31 PM PST 24	Mar 05 04:32:45 PM PST 24	3790931626 ps
T200	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.282448465			Mar 05 04:25:42 PM PST 24	Mar 05 04:31:28 PM PST 24	4008663686 ps
T839	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3738015689			Mar 05 04:10:41 PM PST 24	Mar 05 04:16:45 PM PST 24	3849972568 ps
T840	/workspace/coverage/default/2.chip_tap_straps_prod.4218080750			Mar 05 04:12:12 PM PST 24	Mar 05 04:14:42 PM PST 24	2621108329 ps
T417	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.751281517			Mar 05 03:53:53 PM PST 24	Mar 05 04:13:10 PM PST 24	5830751178 ps
T244	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1125889308			Mar 05 03:51:14 PM PST 24	Mar 05 03:52:58 PM PST 24	2380463478 ps
T841	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.692794881			Mar 05 04:10:16 PM PST 24	Mar 05 04:15:00 PM PST 24	2954082324 ps
T328	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2255746444			Mar 05 03:56:27 PM PST 24	Mar 05 04:24:20 PM PST 24	13214905973 ps
T842	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2040676776			Mar 05 04:08:18 PM PST 24	Mar 05 04:13:51 PM PST 24	3355477715 ps
T659	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3674068424			Mar 05 04:25:11 PM PST 24	Mar 05 04:31:51 PM PST 24	3569307212 ps
T843	/workspace/coverage/default/0.chip_sw_kmac_smoketest.324398388			Mar 05 03:53:40 PM PST 24	Mar 05 03:58:41 PM PST 24	3101666476 ps
T115	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3639611096			Mar 05 03:50:21 PM PST 24	Mar 05 04:48:34 PM PST 24	16584595004 ps
T220	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.50437502			Mar 05 04:08:56 PM PST 24	Mar 05 04:20:16 PM PST 24	3909426720 ps
T844	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.17604595			Mar 05 04:08:50 PM PST 24	Mar 05 04:13:11 PM PST 24	3091140888 ps
T221	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1361335270			Mar 05 04:16:50 PM PST 24	Mar 05 04:28:00 PM PST 24	5365103684 ps
T144	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3458886607			Mar 05 04:01:26 PM PST 24	Mar 05 04:14:25 PM PST 24	4226969360 ps
T618	/workspace/coverage/default/62.chip_sw_all_escalation_resets.3363820453			Mar 05 04:23:28 PM PST 24	Mar 05 04:37:07 PM PST 24	4984596456 ps
T23	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.166826728			Mar 05 03:49:52 PM PST 24	Mar 05 06:03:45 PM PST 24	31685063680 ps
T237	/workspace/coverage/default/36.chip_sw_all_escalation_resets.1194362991			Mar 05 04:20:01 PM PST 24	Mar 05 04:30:52 PM PST 24	5050165944 ps
T27	/workspace/coverage/default/1.chip_sw_gpio.538928670			Mar 05 03:56:27 PM PST 24	Mar 05 04:04:12 PM PST 24	4394046730 ps
T84	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.1262627014			Mar 05 04:00:29 PM PST 24	Mar 05 04:04:36 PM PST 24	2869016872 ps
T50	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.131665530			Mar 05 04:11:49 PM PST 24	Mar 05 04:35:55 PM PST 24	21654594716 ps
T845	/workspace/coverage/default/2.rom_e2e_smoke.4060640089			Mar 05 04:14:09 PM PST 24	Mar 05 04:44:50 PM PST 24	9073970152 ps
T195	/workspace/coverage/default/2.chip_sw_all_escalation_resets.3015857802			Mar 05 04:05:27 PM PST 24	Mar 05 04:16:21 PM PST 24	5632921858 ps
T846	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2569911729			Mar 05 04:17:29 PM PST 24	Mar 05 04:21:47 PM PST 24	2523683096 ps
T847	/workspace/coverage/default/1.chip_sw_csrng_smoketest.18094785			Mar 05 04:05:24 PM PST 24	Mar 05 04:09:16 PM PST 24	3180835908 ps
T848	/workspace/coverage/default/2.chip_sw_aes_smoketest.2482349499			Mar 05 04:15:57 PM PST 24	Mar 05 04:21:10 PM PST 24	2962427372 ps
T133	/workspace/coverage/default/1.rom_e2e_shutdown_output.875502393			Mar 05 04:08:55 PM PST 24	Mar 05 05:01:54 PM PST 24	25716919993 ps
T256	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.839407104			Mar 05 04:13:52 PM PST 24	Mar 05 04:23:25 PM PST 24	4354287042 ps
T849	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2344343912			Mar 05 03:58:21 PM PST 24	Mar 05 04:38:12 PM PST 24	8392471908 ps
T744	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1993390147			Mar 05 04:21:50 PM PST 24	Mar 05 04:28:40 PM PST 24	3568112568 ps
T288	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3436016724			Mar 05 04:06:15 PM PST 24	Mar 05 04:20:09 PM PST 24	4617354592 ps
T296	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.1941615034			Mar 05 04:09:45 PM PST 24	Mar 05 04:40:08 PM PST 24	8244435102 ps
T598	/workspace/coverage/default/1.chip_sw_aes_masking_off.1829867254			Mar 05 03:59:31 PM PST 24	Mar 05 04:04:30 PM PST 24	3283389369 ps
T138	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3958209630			Mar 05 03:51:08 PM PST 24	Mar 05 03:55:28 PM PST 24	4127228851 ps
T633	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.704226709			Mar 05 04:11:50 PM PST 24	Mar 05 04:51:01 PM PST 24	22267100200 ps
T634	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.4138458376			Mar 05 04:01:20 PM PST 24	Mar 05 04:42:04 PM PST 24	23856870200 ps
T654	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2541043564			Mar 05 04:21:17 PM PST 24	Mar 05 04:29:01 PM PST 24	3917625008 ps
T606	/workspace/coverage/default/1.chip_sw_power_idle_load.139921891			Mar 05 04:05:00 PM PST 24	Mar 05 04:17:36 PM PST 24	3808386452 ps
T62	/workspace/coverage/default/0.chip_sw_alert_test.439229013			Mar 05 03:51:47 PM PST 24	Mar 05 03:57:38 PM PST 24	3231967132 ps
T673	/workspace/coverage/default/60.chip_sw_all_escalation_resets.948859881			Mar 05 04:22:32 PM PST 24	Mar 05 04:32:18 PM PST 24	5873619200 ps
T89	/workspace/coverage/default/38.chip_sw_all_escalation_resets.4157096391			Mar 05 04:20:25 PM PST 24	Mar 05 04:33:05 PM PST 24	5957300260 ps
T95	/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.557655594			Mar 05 03:53:31 PM PST 24	Mar 05 04:19:23 PM PST 24	12113174304 ps
T96	/workspace/coverage/default/4.chip_tap_straps_dev.1785488173			Mar 05 04:15:46 PM PST 24	Mar 05 04:29:34 PM PST 24	7590455583 ps
T97	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1504141229			Mar 05 04:04:38 PM PST 24	Mar 05 04:14:06 PM PST 24	3902929268 ps
T98	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3069041360			Mar 05 03:49:34 PM PST 24	Mar 05 04:04:00 PM PST 24	8587022992 ps
T99	/workspace/coverage/default/1.chip_sw_gpio_smoketest.581775935			Mar 05 04:04:39 PM PST 24	Mar 05 04:08:38 PM PST 24	2267708950 ps
T100	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4125467433			Mar 05 04:02:45 PM PST 24	Mar 05 05:04:35 PM PST 24	25593068916 ps
T101	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2921706646			Mar 05 03:58:09 PM PST 24	Mar 05 04:50:29 PM PST 24	10864517290 ps
T102	/workspace/coverage/default/28.chip_sw_all_escalation_resets.3949548818			Mar 05 04:20:39 PM PST 24	Mar 05 04:31:20 PM PST 24	4323159880 ps
T103	/workspace/coverage/default/8.chip_sw_all_escalation_resets.2646234589			Mar 05 04:16:37 PM PST 24	Mar 05 04:27:55 PM PST 24	5565183076 ps
T850	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3621025532			Mar 05 04:18:59 PM PST 24	Mar 05 04:48:27 PM PST 24	13281568220 ps
T851	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2649906510			Mar 05 04:11:50 PM PST 24	Mar 05 04:18:56 PM PST 24	2964196370 ps
T355	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1193531427			Mar 05 04:00:53 PM PST 24	Mar 05 04:51:36 PM PST 24	11521241994 ps
T661	/workspace/coverage/default/41.chip_sw_all_escalation_resets.443075924			Mar 05 04:21:43 PM PST 24	Mar 05 04:32:56 PM PST 24	5437597626 ps
T163	/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2843070328			Mar 05 04:03:04 PM PST 24	Mar 05 04:08:25 PM PST 24	4193986320 ps
T852	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3108774006			Mar 05 03:57:34 PM PST 24	Mar 05 04:04:45 PM PST 24	6600573240 ps
T232	/workspace/coverage/default/0.chip_sw_power_sleep_load.1192304183			Mar 05 03:54:31 PM PST 24	Mar 05 04:01:07 PM PST 24	4851134968 ps
T692	/workspace/coverage/default/7.chip_sw_all_escalation_resets.271136819			Mar 05 04:18:34 PM PST 24	Mar 05 04:28:22 PM PST 24	5465819448 ps
T853	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3086657432			Mar 05 04:10:04 PM PST 24	Mar 05 05:02:59 PM PST 24	34360106374 ps
T247	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2161525967			Mar 05 04:17:43 PM PST 24	Mar 05 04:34:10 PM PST 24	6417232812 ps
T249	/workspace/coverage/default/75.chip_sw_all_escalation_resets.4070546388			Mar 05 04:26:07 PM PST 24	Mar 05 04:34:58 PM PST 24	6078521178 ps
T250	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3068923473			Mar 05 03:56:21 PM PST 24	Mar 05 04:03:16 PM PST 24	5787208904 ps
T134	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2462528703			Mar 05 04:05:42 PM PST 24	Mar 05 04:15:10 PM PST 24	5719392981 ps
T251	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.4130399868			Mar 05 04:06:13 PM PST 24	Mar 05 04:19:25 PM PST 24	6105239160 ps
T252	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3737650492			Mar 05 04:15:24 PM PST 24	Mar 05 04:20:20 PM PST 24	2535805160 ps
T253	/workspace/coverage/default/97.chip_sw_all_escalation_resets.3657205331			Mar 05 04:26:04 PM PST 24	Mar 05 04:35:59 PM PST 24	4098427240 ps
T254	/workspace/coverage/default/0.chip_sw_pattgen_ios.1033896255			Mar 05 03:49:17 PM PST 24	Mar 05 03:52:26 PM PST 24	2310114256 ps
T135	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3413117543			Mar 05 03:50:31 PM PST 24	Mar 05 05:25:17 PM PST 24	50319725345 ps
T255	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1057491541			Mar 05 03:56:46 PM PST 24	Mar 05 04:32:23 PM PST 24	8772891309 ps
T655	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.4159260397			Mar 05 04:22:36 PM PST 24	Mar 05 04:28:29 PM PST 24	4163013016 ps
T854	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2187390440			Mar 05 03:50:54 PM PST 24	Mar 05 04:12:13 PM PST 24	11653636552 ps
T154	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4146059123			Mar 05 03:50:13 PM PST 24	Mar 05 04:00:15 PM PST 24	3956063940 ps
T855	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.544297407			Mar 05 04:15:23 PM PST 24	Mar 05 04:19:20 PM PST 24	3247481750 ps
T856	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3012674722			Mar 05 04:11:14 PM PST 24	Mar 05 04:22:38 PM PST 24	7123000400 ps
T331	/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2499971237			Mar 05 04:13:02 PM PST 24	Mar 05 04:20:00 PM PST 24	6064626400 ps
T857	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3869116598			Mar 05 03:56:39 PM PST 24	Mar 05 04:22:23 PM PST 24	7051025348 ps
T858	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3042095191			Mar 05 04:06:48 PM PST 24	Mar 05 04:11:53 PM PST 24	3446211400 ps
T859	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3412315833			Mar 05 04:10:25 PM PST 24	Mar 05 04:21:07 PM PST 24	5320997528 ps
T596	/workspace/coverage/default/2.chip_sw_edn_sw_mode.489012269			Mar 05 04:08:59 PM PST 24	Mar 05 04:39:24 PM PST 24	8644134304 ps
T136	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3897894522			Mar 05 03:52:33 PM PST 24	Mar 05 04:28:08 PM PST 24	18355203229 ps
T860	/workspace/coverage/default/3.chip_tap_straps_prod.1941997313			Mar 05 04:15:47 PM PST 24	Mar 05 04:33:36 PM PST 24	9049890773 ps
T861	/workspace/coverage/default/2.rom_e2e_asm_init_prod.2568030299			Mar 05 04:20:23 PM PST 24	Mar 05 04:56:18 PM PST 24	8491231464 ps
T206	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4026800402			Mar 05 03:54:23 PM PST 24	Mar 05 04:03:14 PM PST 24	4429928478 ps
T90	/workspace/coverage/default/92.chip_sw_all_escalation_resets.4222379661			Mar 05 04:27:12 PM PST 24	Mar 05 04:36:00 PM PST 24	5192820356 ps
T125	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3232969211			Mar 05 04:08:04 PM PST 24	Mar 05 04:09:43 PM PST 24	2537207184 ps
T862	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.323444110			Mar 05 03:53:23 PM PST 24	Mar 05 03:56:12 PM PST 24	3034269058 ps
T704	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2154258837			Mar 05 04:22:42 PM PST 24	Mar 05 04:30:19 PM PST 24	3658290796 ps
T863	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.239081468			Mar 05 03:57:49 PM PST 24	Mar 05 04:06:37 PM PST 24	4429941672 ps