Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.pinmux_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	142736	1			T77	600		T81	27		T82	160
values[2]	9936	1			T77	105		T82	2		T551	1
values[3]	3506	1			T77	8		T424	6		T403	38
values[4]	2011	1			T403	37		T405	1		T587	8
values[5]	1266	1			T403	18		T405	1		T587	7
values[6]	892	1			T403	19		T405	1		T587	3
values[7]	734	1			T403	21		T405	1		T587	6
values[8]	655	1			T403	15		T405	1		T587	5
values[9]	602	1			T403	15		T405	1		T587	5
values[10]	513	1			T403	12		T405	1		T587	7
values[11]	477	1			T403	7		T405	1		T587	9
values[12]	389	1			T403	3		T405	1		T587	5
values[13]	371	1			T403	3		T405	1		T587	5
values[14]	342	1			T403	6		T405	1		T587	9
values[15]	342	1			T403	8		T405	1		T587	15
values[16]	324	1			T403	8		T405	1		T587	8
values[17]	334	1			T403	18		T405	1		T587	5
values[18]	353	1			T403	3		T405	1		T587	13
values[19]	375	1			T403	6		T405	1		T587	11
values[20]	354	1			T403	20		T405	1		T587	8
values[21]	326	1			T403	11		T405	1		T587	12
values[22]	344	1			T403	3		T405	1		T587	5
values[23]	326	1			T403	5		T405	1		T587	13
values[24]	340	1			T403	9		T405	1		T587	5
values[25]	310	1			T403	4		T405	1		T587	6
values[26]	325	1			T403	3		T405	1		T587	7
values[27]	306	1			T403	7		T405	1		T587	9
values[28]	332	1			T403	11		T405	1		T587	4
values[29]	313	1			T403	5		T405	1		T587	6
values[30]	292	1			T403	13		T405	1		T587	8
values[31]	343	1			T403	6		T405	1		T587	19
values[32]	297	1			T403	5		T405	1		T587	16
values[33]	297	1			T403	8		T405	1		T587	11
values[34]	278	1			T403	11		T405	1		T587	7
values[35]	306	1			T403	14		T405	1		T587	5
values[36]	327	1			T403	18		T405	1		T587	3
values[37]	259	1			T403	5		T405	1		T587	5
values[38]	307	1			T403	3		T405	1		T587	9
values[39]	294	1			T403	7		T405	1		T587	5
values[40]	276	1			T403	9		T405	1		T587	7
values[41]	296	1			T403	3		T405	1		T587	5
values[42]	275	1			T403	2		T405	1		T587	5
values[43]	307	1			T403	11		T405	1		T587	13
values[44]	301	1			T403	10		T405	1		T587	11
values[45]	269	1			T403	2		T405	1		T587	7
values[46]	240	1			T405	1		T587	4		T400	1
values[47]	317	1			T405	1		T587	7		T400	1
values[48]	305	1			T405	1		T587	12		T400	1
values[49]	299	1			T405	1		T587	11		T400	1
values[50]	261	1			T405	1		T587	6		T400	1
values[51]	287	1			T405	1		T587	7		T400	1
values[52]	223	1			T405	1		T587	3		T400	1
values[53]	252	1			T405	1		T587	18		T400	1
values[54]	231	1			T405	1		T587	9		T400	1
values[55]	252	1			T405	1		T587	5		T400	1
values[56]	257	1			T405	1		T587	6		T400	1
values[57]	227	1			T405	1		T587	4		T400	1
values[58]	256	1			T405	1		T587	4		T400	1
values[59]	222	1			T405	1		T587	8		T400	1
values[60]	232	1			T405	1		T587	8		T400	1
values[61]	224	1			T405	1		T587	5		T400	1
values[62]	210	1			T405	1		T400	1		T453	1
values[63]	238	1			T405	2		T400	1		T453	1
values[64]	192	1			T405	1		T400	1		T453	1
values[65]	177	1			T405	1		T400	1		T453	1
values[66]	176	1			T405	1		T400	1		T453	1
values[67]	172	1			T405	1		T400	1		T453	1
values[68]	175	1			T405	1		T400	1		T453	1
values[69]	138	1			T405	1		T400	1		T453	1
values[70]	157	1			T405	1		T400	1		T453	1
values[71]	125	1			T405	1		T400	1		T453	1
values[72]	126	1			T405	1		T400	1		T453	1
values[73]	152	1			T405	1		T400	1		T453	1
values[74]	132	1			T405	1		T400	1		T453	1
values[75]	166	1			T405	1		T400	1		T453	1
values[76]	146	1			T405	1		T400	1		T453	1
values[77]	157	1			T405	1		T400	1		T453	1
values[78]	142	1			T405	1		T400	1		T453	1
values[79]	126	1			T405	1		T400	1		T453	1
values[80]	132	1			T405	1		T400	1		T453	1
values[81]	139	1			T405	1		T400	1		T453	1
values[82]	131	1			T405	1		T400	1		T453	1
values[83]	145	1			T405	1		T400	1		T453	1
values[84]	147	1			T405	1		T400	1		T453	1
values[85]	107	1			T405	1		T400	1		T453	1
values[86]	115	1			T405	2		T400	1		T453	1
values[87]	127	1			T405	1		T400	1		T453	1
values[88]	89	1			T405	1		T400	1		T453	2
values[89]	109	1			T405	1		T400	1		T453	1
values[90]	108	1			T405	1		T400	1		T453	1
values[91]	105	1			T405	1		T400	1		T453	1
values[92]	100	1			T405	1		T400	1		T453	1
values[93]	77	1			T405	1		T400	1		T453	1
values[94]	101	1			T405	1		T400	1		T453	1
values[95]	96	1			T405	1		T400	1		T453	1
values[96]	97	1			T405	1		T400	1		T453	1
values[97]	108	1			T405	1		T400	2		T453	1
values[98]	106	1			T405	1		T400	1		T453	1
values[99]	87	1			T405	1		T400	1		T453	1
values[100]	107	1			T405	1		T400	1		T453	1
values[101]	96	1			T405	1		T400	1		T453	1
values[102]	89	1			T405	1		T400	1		T453	1
values[103]	103	1			T405	1		T400	1		T453	1
values[104]	107	1			T405	1		T400	1		T453	1
values[105]	99	1			T405	1		T400	1		T453	1
values[106]	116	1			T405	1		T400	1		T453	1
values[107]	103	1			T405	1		T400	1		T453	1
values[108]	100	1			T405	1		T400	1		T453	1
values[109]	105	1			T405	1		T400	1		T453	1
values[110]	85	1			T405	1		T400	1		T453	1
values[111]	104	1			T405	1		T400	4		T453	1
values[112]	82	1			T405	1		T400	1		T453	1
values[113]	89	1			T405	1		T400	1		T453	1
values[114]	95	1			T405	1		T400	2		T453	1
values[115]	114	1			T405	1		T400	1		T453	1
values[116]	95	1			T405	3		T400	3		T453	1
values[117]	98	1			T405	4		T400	5		T453	1
values[118]	93	1			T405	6		T400	1		T453	1
values[119]	104	1			T405	6		T400	2		T453	1
values[120]	79	1			T405	1		T400	2		T453	1
values[121]	101	1			T405	3		T400	5		T453	7
values[122]	100	1			T405	2		T400	1		T453	2
values[123]	96	1			T405	2		T400	2		T453	3
values[124]	95	1			T405	1		T400	1		T453	1
values[125]	97	1			T405	1		T400	1		T453	1
values[126]	195	1			T405	3		T400	2		T453	2
values[127]	1190	1			T405	39		T400	33		T453	28
values[128]	9048	1			T405	347		T400	344		T453	283