Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.ast_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	141563	1			T77	242		T81	18		T82	441
values[2]	11621	1			T82	75		T231	1		T404	1
values[3]	4856	1			T82	25		T664	1		T405	1
values[4]	2775	1			T82	15		T664	1		T405	1
values[5]	1662	1			T82	9		T664	1		T405	1
values[6]	1120	1			T82	10		T664	1		T405	1
values[7]	687	1			T82	17		T664	1		T405	1
values[8]	507	1			T82	10		T664	1		T405	1
values[9]	346	1			T82	4		T664	1		T405	1
values[10]	376	1			T82	17		T664	1		T405	1
values[11]	336	1			T82	10		T664	1		T405	1
values[12]	308	1			T82	3		T664	1		T405	1
values[13]	296	1			T82	2		T664	1		T405	1
values[14]	299	1			T82	1		T664	1		T405	1
values[15]	293	1			T82	1		T664	1		T405	1
values[16]	297	1			T82	2		T664	1		T405	1
values[17]	257	1			T82	1		T664	1		T405	1
values[18]	247	1			T664	1		T405	1		T442	6
values[19]	271	1			T664	1		T405	1		T442	3
values[20]	275	1			T664	1		T405	1		T442	3
values[21]	266	1			T664	1		T405	1		T442	11
values[22]	257	1			T664	1		T405	1		T442	4
values[23]	261	1			T664	1		T405	1		T442	10
values[24]	220	1			T664	1		T405	1		T442	7
values[25]	275	1			T664	1		T405	1		T442	5
values[26]	268	1			T664	1		T405	1		T442	7
values[27]	275	1			T664	1		T405	1		T442	3
values[28]	296	1			T664	1		T405	1		T442	3
values[29]	222	1			T664	1		T405	1		T442	5
values[30]	236	1			T664	1		T405	1		T442	7
values[31]	224	1			T664	1		T405	1		T442	5
values[32]	228	1			T664	1		T405	1		T442	5
values[33]	247	1			T664	1		T405	1		T442	7
values[34]	237	1			T664	1		T405	1		T442	7
values[35]	228	1			T664	1		T405	1		T442	4
values[36]	233	1			T664	1		T405	1		T442	6
values[37]	273	1			T664	1		T405	1		T442	12
values[38]	248	1			T664	1		T405	1		T442	4
values[39]	230	1			T664	1		T405	1		T442	7
values[40]	225	1			T664	1		T405	1		T442	12
values[41]	252	1			T664	1		T405	1		T442	6
values[42]	200	1			T664	1		T405	1		T442	3
values[43]	237	1			T664	1		T405	1		T442	4
values[44]	218	1			T664	1		T405	1		T442	11
values[45]	197	1			T664	1		T405	1		T442	8
values[46]	224	1			T664	1		T405	1		T442	4
values[47]	228	1			T664	1		T405	1		T442	7
values[48]	197	1			T664	1		T405	1		T442	9
values[49]	213	1			T664	1		T405	1		T442	9
values[50]	214	1			T664	1		T405	1		T442	6
values[51]	195	1			T664	1		T405	1		T442	4
values[52]	261	1			T664	1		T405	1		T442	7
values[53]	205	1			T664	1		T405	1		T442	3
values[54]	206	1			T664	1		T405	1		T442	3
values[55]	200	1			T664	1		T405	1		T442	12
values[56]	185	1			T664	1		T405	1		T442	6
values[57]	153	1			T664	1		T405	1		T442	7
values[58]	190	1			T664	1		T405	1		T442	13
values[59]	149	1			T664	1		T405	1		T442	3
values[60]	164	1			T664	1		T405	1		T442	16
values[61]	150	1			T664	1		T405	1		T442	12
values[62]	141	1			T664	1		T405	1		T442	10
values[63]	166	1			T664	1		T405	1		T442	11
values[64]	125	1			T664	1		T405	1		T442	9
values[65]	103	1			T664	1		T405	1		T442	4
values[66]	130	1			T664	1		T405	1		T442	12
values[67]	113	1			T664	1		T405	1		T442	10
values[68]	127	1			T664	1		T405	1		T442	8
values[69]	132	1			T664	1		T405	1		T442	2
values[70]	110	1			T664	1		T405	1		T478	12
values[71]	78	1			T664	1		T405	1		T478	5
values[72]	74	1			T664	1		T405	1		T461	7
values[73]	88	1			T664	1		T405	1		T461	11
values[74]	101	1			T664	1		T405	1		T461	6
values[75]	79	1			T664	1		T405	1		T461	1
values[76]	80	1			T664	1		T405	1		T461	4
values[77]	79	1			T664	1		T405	1		T461	4
values[78]	81	1			T664	1		T405	1		T461	2
values[79]	62	1			T664	1		T405	1		T461	3
values[80]	90	1			T664	1		T405	1		T461	2
values[81]	81	1			T664	1		T405	1		T461	2
values[82]	57	1			T664	1		T405	1		T461	1
values[83]	74	1			T664	1		T405	1		T461	2
values[84]	85	1			T664	2		T405	1		T461	1
values[85]	89	1			T664	1		T405	1		T461	2
values[86]	115	1			T664	1		T405	1		T461	1
values[87]	103	1			T664	1		T405	1		T461	3
values[88]	99	1			T664	1		T405	1		T461	3
values[89]	88	1			T664	1		T405	1		T461	8
values[90]	101	1			T664	1		T405	1		T461	5
values[91]	92	1			T664	1		T405	1		T461	2
values[92]	103	1			T664	1		T405	1		T461	2
values[93]	77	1			T664	1		T405	1		T461	3
values[94]	103	1			T664	1		T405	1		T461	1
values[95]	95	1			T664	1		T405	1		T461	1
values[96]	93	1			T664	1		T405	1		T461	2
values[97]	96	1			T664	1		T405	1		T461	1
values[98]	89	1			T664	1		T405	1		T461	2
values[99]	75	1			T664	1		T405	1		T461	2
values[100]	81	1			T664	1		T405	1		T461	5
values[101]	83	1			T664	1		T405	1		T461	1
values[102]	76	1			T664	1		T405	1		T461	2
values[103]	78	1			T664	1		T405	1		T461	2
values[104]	72	1			T664	1		T405	1		T461	2
values[105]	64	1			T664	1		T405	1		T461	2
values[106]	75	1			T664	1		T405	1		T461	7
values[107]	74	1			T664	2		T405	1		T461	3
values[108]	70	1			T664	3		T405	1		T461	1
values[109]	80	1			T664	2		T405	1		T461	2
values[110]	107	1			T664	2		T405	1		T461	1
values[111]	84	1			T664	1		T405	1		T461	1
values[112]	93	1			T664	4		T405	2		T461	2
values[113]	78	1			T664	1		T405	1		T461	2
values[114]	78	1			T664	2		T405	1		T461	5
values[115]	73	1			T664	4		T405	1		T461	1
values[116]	65	1			T664	3		T405	5		T461	1
values[117]	79	1			T664	1		T405	13		T461	2
values[118]	66	1			T664	2		T405	2		T461	1
values[119]	79	1			T664	2		T405	3		T461	2
values[120]	63	1			T664	1		T405	1		T461	3
values[121]	71	1			T664	4		T405	2		T461	7
values[122]	63	1			T664	1		T405	2		T461	1
values[123]	92	1			T664	1		T405	3		T461	3
values[124]	77	1			T664	2		T405	2		T461	3
values[125]	85	1			T664	1		T405	1		T461	1
values[126]	203	1			T664	3		T405	1		T461	27
values[127]	984	1			T664	44		T405	32		T461	62
values[128]	6843	1			T664	287		T405	329		T461	26