Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	145552	1			T77	269		T81	20		T82	139
values[2]	10450	1			T82	1		T491	151		T512	2
values[3]	3946	1			T491	124		T490	1		T403	9
values[4]	2296	1			T491	54		T403	7		T548	12
values[5]	1442	1			T491	17		T403	8		T430	2
values[6]	955	1			T491	2		T403	3		T430	1
values[7]	691	1			T491	3		T430	1		T748	1
values[8]	562	1			T491	1		T430	3		T748	1
values[9]	487	1			T430	5		T748	1		T442	7
values[10]	428	1			T430	3		T748	1		T442	6
values[11]	370	1			T430	2		T748	1		T442	7
values[12]	300	1			T430	3		T748	1		T442	9
values[13]	299	1			T430	3		T748	1		T442	3
values[14]	223	1			T430	2		T748	1		T442	3
values[15]	240	1			T430	2		T748	1		T442	10
values[16]	307	1			T430	1		T748	1		T442	15
values[17]	291	1			T430	3		T748	1		T442	3
values[18]	295	1			T430	1		T748	1		T442	5
values[19]	287	1			T430	3		T748	1		T442	24
values[20]	247	1			T430	1		T748	1		T442	4
values[21]	276	1			T430	2		T748	1		T442	6
values[22]	260	1			T430	2		T748	1		T442	3
values[23]	286	1			T430	4		T748	1		T442	8
values[24]	283	1			T430	2		T748	1		T442	16
values[25]	298	1			T430	1		T748	1		T442	8
values[26]	259	1			T430	2		T748	1		T442	4
values[27]	270	1			T430	2		T748	1		T442	4
values[28]	247	1			T430	2		T748	1		T442	7
values[29]	260	1			T430	4		T748	2		T442	3
values[30]	306	1			T430	5		T748	1		T442	9
values[31]	270	1			T430	2		T748	1		T442	17
values[32]	269	1			T430	1		T748	1		T442	13
values[33]	271	1			T430	3		T748	1		T442	6
values[34]	275	1			T430	3		T748	1		T442	3
values[35]	254	1			T430	1		T748	1		T442	2
values[36]	226	1			T430	5		T748	1		T442	7
values[37]	259	1			T430	5		T748	1		T442	5
values[38]	240	1			T430	1		T748	1		T442	6
values[39]	245	1			T430	2		T748	1		T442	8
values[40]	233	1			T430	6		T748	1		T442	13
values[41]	222	1			T430	4		T748	1		T442	5
values[42]	267	1			T430	6		T748	1		T442	5
values[43]	272	1			T430	1		T748	1		T442	11
values[44]	263	1			T430	6		T748	1		T442	5
values[45]	227	1			T430	1		T748	1		T442	6
values[46]	242	1			T430	3		T748	1		T773	1
values[47]	246	1			T430	2		T748	1		T773	1
values[48]	205	1			T430	2		T748	1		T773	1
values[49]	202	1			T430	3		T748	1		T773	1
values[50]	211	1			T430	9		T748	1		T773	1
values[51]	199	1			T430	1		T748	1		T773	1
values[52]	229	1			T430	2		T748	1		T773	1
values[53]	241	1			T430	1		T748	2		T773	1
values[54]	196	1			T430	1		T748	1		T773	1
values[55]	210	1			T430	2		T748	1		T773	1
values[56]	217	1			T430	3		T748	1		T773	1
values[57]	247	1			T430	3		T748	1		T773	1
values[58]	164	1			T430	6		T748	1		T773	1
values[59]	195	1			T430	4		T748	1		T773	1
values[60]	159	1			T430	6		T748	1		T773	1
values[61]	205	1			T430	3		T748	1		T773	1
values[62]	155	1			T430	1		T748	1		T773	1
values[63]	143	1			T430	2		T748	1		T773	1
values[64]	128	1			T430	2		T748	1		T773	1
values[65]	143	1			T430	1		T748	1		T773	1
values[66]	153	1			T430	5		T748	1		T773	1
values[67]	138	1			T430	2		T748	1		T773	1
values[68]	128	1			T430	2		T748	2		T773	1
values[69]	140	1			T430	7		T748	1		T773	1
values[70]	126	1			T430	5		T748	1		T773	1
values[71]	142	1			T430	7		T748	1		T773	1
values[72]	123	1			T430	1		T748	1		T773	1
values[73]	120	1			T430	1		T748	1		T773	1
values[74]	84	1			T430	2		T748	1		T773	1
values[75]	90	1			T430	6		T748	1		T773	1
values[76]	101	1			T430	3		T748	1		T773	1
values[77]	81	1			T430	2		T748	1		T773	1
values[78]	80	1			T430	3		T748	1		T773	1
values[79]	97	1			T430	5		T748	1		T773	1
values[80]	106	1			T430	5		T748	1		T773	1
values[81]	106	1			T430	3		T748	1		T773	1
values[82]	104	1			T430	4		T748	1		T773	1
values[83]	90	1			T430	3		T748	1		T773	2
values[84]	103	1			T430	3		T748	1		T773	1
values[85]	90	1			T430	1		T748	1		T773	3
values[86]	88	1			T430	4		T748	1		T773	3
values[87]	96	1			T430	1		T748	1		T773	3
values[88]	95	1			T430	2		T748	1		T773	6
values[89]	76	1			T430	7		T748	1		T773	1
values[90]	94	1			T430	4		T748	1		T773	4
values[91]	72	1			T430	5		T748	1		T773	2
values[92]	77	1			T430	7		T748	1		T773	3
values[93]	94	1			T430	6		T748	1		T773	1
values[94]	98	1			T430	5		T748	1		T773	1
values[95]	97	1			T430	3		T748	1		T773	1
values[96]	80	1			T430	4		T748	1		T773	2
values[97]	84	1			T430	1		T748	1		T773	2
values[98]	88	1			T748	1		T773	4		T778	1
values[99]	74	1			T748	1		T773	1		T778	1
values[100]	61	1			T748	1		T773	2		T778	1
values[101]	103	1			T748	1		T773	4		T778	1
values[102]	76	1			T748	1		T773	2		T778	1
values[103]	103	1			T748	1		T773	3		T778	1
values[104]	75	1			T748	1		T773	2		T778	1
values[105]	73	1			T748	2		T773	1		T778	1
values[106]	80	1			T748	1		T773	1		T778	1
values[107]	93	1			T748	1		T773	1		T778	1
values[108]	75	1			T748	1		T773	1		T778	1
values[109]	80	1			T748	1		T773	2		T778	1
values[110]	95	1			T748	1		T773	3		T778	1
values[111]	81	1			T748	1		T773	4		T778	1
values[112]	58	1			T748	1		T773	1		T778	2
values[113]	81	1			T748	1		T773	2		T778	4
values[114]	81	1			T748	1		T773	5		T778	2
values[115]	71	1			T748	1		T773	2		T778	2
values[116]	69	1			T748	1		T773	1		T778	5
values[117]	76	1			T748	1		T773	1		T778	2
values[118]	62	1			T748	1		T773	1		T778	4
values[119]	69	1			T748	1		T773	1		T778	1
values[120]	58	1			T748	1		T773	2		T778	2
values[121]	49	1			T748	2		T773	1		T778	1
values[122]	61	1			T748	4		T773	1		T778	2
values[123]	76	1			T748	2		T773	3		T778	2
values[124]	68	1			T748	2		T773	1		T778	1
values[125]	93	1			T748	2		T773	3		T778	3
values[126]	157	1			T748	1		T773	1		T778	3
values[127]	678	1			T748	21		T773	17		T778	39
values[128]	4786	1			T748	246		T773	248		T778	321