Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	139615	1			T77	268		T81	25		T82	372
values[2]	10106	1			T82	32		T230	66		T231	1
values[3]	4275	1			T82	14		T230	43		T403	8
values[4]	2547	1			T82	9		T230	15		T403	6
values[5]	1673	1			T82	16		T230	7		T403	12
values[6]	1039	1			T82	7		T403	8		T591	12
values[7]	736	1			T82	7		T403	8		T591	29
values[8]	509	1			T82	5		T403	4		T591	13
values[9]	403	1			T82	12		T403	11		T591	10
values[10]	397	1			T82	10		T403	10		T591	6
values[11]	362	1			T82	9		T403	4		T591	6
values[12]	320	1			T82	3		T403	7		T402	21
values[13]	279	1			T82	7		T403	7		T402	14
values[14]	333	1			T82	6		T403	4		T402	24
values[15]	340	1			T82	5		T403	6		T402	7
values[16]	318	1			T82	5		T403	9		T402	12
values[17]	294	1			T82	3		T403	7		T402	14
values[18]	306	1			T82	1		T403	4		T402	16
values[19]	294	1			T82	6		T403	15		T402	10
values[20]	371	1			T82	6		T403	15		T402	19
values[21]	299	1			T82	2		T403	5		T402	8
values[22]	326	1			T82	2		T403	5		T402	23
values[23]	326	1			T82	5		T403	8		T402	12
values[24]	274	1			T82	4		T403	3		T402	11
values[25]	268	1			T82	1		T403	5		T402	16
values[26]	287	1			T82	11		T403	8		T402	12
values[27]	314	1			T82	15		T403	19		T402	22
values[28]	322	1			T82	11		T403	10		T402	12
values[29]	302	1			T82	8		T403	4		T402	15
values[30]	299	1			T82	1		T403	4		T402	16
values[31]	332	1			T82	2		T403	5		T402	13
values[32]	267	1			T82	5		T403	4		T402	15
values[33]	284	1			T82	3		T403	3		T402	8
values[34]	291	1			T82	2		T403	3		T402	8
values[35]	291	1			T403	10		T402	15		T578	11
values[36]	289	1			T403	10		T402	20		T578	16
values[37]	313	1			T403	7		T402	17		T578	14
values[38]	247	1			T403	18		T402	7		T578	12
values[39]	260	1			T403	23		T402	24		T578	9
values[40]	277	1			T403	11		T402	13		T578	13
values[41]	244	1			T403	5		T402	14		T578	16
values[42]	273	1			T403	9		T402	19		T578	41
values[43]	272	1			T403	7		T402	12		T578	11
values[44]	270	1			T403	5		T402	15		T578	14
values[45]	301	1			T403	3		T402	9		T578	12
values[46]	266	1			T403	8		T402	18		T578	12
values[47]	306	1			T403	5		T402	11		T578	9
values[48]	243	1			T403	2		T402	9		T578	8
values[49]	264	1			T403	15		T402	7		T578	11
values[50]	238	1			T403	10		T402	5		T578	11
values[51]	241	1			T403	3		T402	8		T578	14
values[52]	234	1			T403	10		T402	22		T578	16
values[53]	228	1			T403	6		T402	6		T578	21
values[54]	220	1			T403	4		T402	5		T578	14
values[55]	229	1			T403	6		T402	5		T578	11
values[56]	201	1			T403	8		T402	3		T578	16
values[57]	238	1			T403	9		T402	11		T578	9
values[58]	213	1			T403	5		T402	7		T578	6
values[59]	203	1			T403	4		T402	6		T578	6
values[60]	234	1			T403	6		T402	4		T578	5
values[61]	160	1			T403	7		T402	4		T578	4
values[62]	169	1			T403	6		T402	7		T578	6
values[63]	146	1			T403	8		T402	16		T578	7
values[64]	171	1			T403	3		T402	19		T578	4
values[65]	160	1			T403	3		T402	10		T578	5
values[66]	167	1			T403	8		T402	10		T578	10
values[67]	119	1			T403	1		T402	12		T578	6
values[68]	115	1			T402	4		T578	7		T768	7
values[69]	98	1			T402	5		T578	7		T768	5
values[70]	98	1			T402	7		T578	11		T768	1
values[71]	107	1			T402	9		T578	10		T768	2
values[72]	112	1			T578	15		T768	1		T463	1
values[73]	72	1			T578	4		T768	2		T463	1
values[74]	71	1			T578	7		T768	2		T463	1
values[75]	72	1			T578	5		T768	6		T463	1
values[76]	88	1			T578	6		T768	7		T463	1
values[77]	104	1			T578	6		T768	10		T463	1
values[78]	85	1			T578	5		T768	6		T463	1
values[79]	94	1			T578	2		T768	3		T463	1
values[80]	87	1			T768	5		T463	1		T477	8
values[81]	66	1			T768	2		T463	1		T477	4
values[82]	54	1			T768	2		T463	1		T477	5
values[83]	59	1			T768	2		T463	1		T477	2
values[84]	85	1			T768	3		T463	1		T477	4
values[85]	83	1			T768	4		T463	1		T477	9
values[86]	90	1			T768	1		T463	1		T477	8
values[87]	99	1			T768	2		T463	1		T477	5
values[88]	93	1			T768	1		T463	1		T477	5
values[89]	101	1			T768	9		T463	1		T477	8
values[90]	75	1			T768	5		T463	1		T477	7
values[91]	58	1			T768	2		T463	1		T477	7
values[92]	67	1			T768	1		T463	1		T477	5
values[93]	82	1			T768	3		T463	1		T477	6
values[94]	63	1			T768	2		T463	1		T477	8
values[95]	61	1			T768	5		T463	1		T477	4
values[96]	59	1			T768	2		T463	1		T477	2
values[97]	61	1			T768	2		T463	1		T477	9
values[98]	67	1			T768	2		T463	1		T477	8
values[99]	75	1			T768	4		T463	1		T477	13
values[100]	80	1			T768	3		T463	1		T477	9
values[101]	72	1			T768	1		T463	1		T477	7
values[102]	87	1			T768	6		T463	1		T477	10
values[103]	86	1			T768	5		T463	1		T477	3
values[104]	80	1			T768	3		T463	1		T784	4
values[105]	86	1			T768	2		T463	1		T784	8
values[106]	67	1			T768	2		T463	1		T784	6
values[107]	80	1			T768	1		T463	1		T784	9
values[108]	68	1			T768	1		T463	1		T784	8
values[109]	61	1			T768	1		T463	1		T784	11
values[110]	81	1			T768	4		T463	1		T784	14
values[111]	72	1			T768	2		T463	2		T784	10
values[112]	61	1			T768	6		T463	1		T784	3
values[113]	53	1			T768	4		T463	1		T784	2
values[114]	63	1			T768	3		T463	1		T784	2
values[115]	73	1			T768	3		T463	1		T784	3
values[116]	73	1			T768	3		T463	1		T784	4
values[117]	69	1			T768	4		T463	1		T784	1
values[118]	60	1			T768	2		T463	3		T784	2
values[119]	41	1			T768	2		T463	1		T784	2
values[120]	55	1			T768	2		T463	1		T784	1
values[121]	47	1			T768	3		T463	1		T784	1
values[122]	45	1			T768	1		T463	2		T784	4
values[123]	59	1			T768	1		T463	3		T784	1
values[124]	64	1			T768	5		T463	1		T784	4
values[125]	66	1			T768	6		T463	3		T784	3
values[126]	152	1			T768	10		T463	3		T784	7
values[127]	713	1			T768	18		T463	39		T784	27
values[128]	4193	1			T768	9		T463	388		T784	6