Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	150123	1			T77	233		T81	27		T82	140
values[2]	10656	1			T663	1		T512	1		T566	1
values[3]	5022	1			T403	7		T401	12		T405	1
values[4]	3123	1			T403	5		T405	1		T746	153
values[5]	2082	1			T403	8		T405	1		T746	87
values[6]	1556	1			T403	12		T405	1		T746	53
values[7]	1078	1			T403	12		T405	1		T746	29
values[8]	952	1			T403	4		T405	1		T746	12
values[9]	736	1			T403	15		T405	1		T746	1
values[10]	709	1			T403	6		T405	1		T458	1
values[11]	721	1			T403	10		T405	1		T458	1
values[12]	707	1			T403	17		T405	1		T458	5
values[13]	605	1			T403	7		T405	1		T458	7
values[14]	658	1			T403	4		T405	1		T458	4
values[15]	543	1			T403	6		T405	1		T458	1
values[16]	588	1			T403	23		T405	1		T402	10
values[17]	655	1			T403	13		T405	2		T402	12
values[18]	466	1			T403	5		T405	1		T402	4
values[19]	460	1			T403	6		T405	1		T402	5
values[20]	496	1			T403	21		T405	1		T402	20
values[21]	541	1			T403	5		T405	1		T402	9
values[22]	561	1			T403	32		T405	1		T402	7
values[23]	456	1			T403	7		T405	1		T402	13
values[24]	450	1			T405	1		T402	14		T442	27
values[25]	474	1			T405	1		T402	10		T442	28
values[26]	434	1			T405	1		T402	3		T442	8
values[27]	446	1			T405	1		T402	9		T442	11
values[28]	487	1			T405	1		T402	6		T442	21
values[29]	457	1			T405	1		T402	4		T442	17
values[30]	522	1			T405	1		T402	24		T442	20
values[31]	461	1			T405	1		T402	6		T442	27
values[32]	455	1			T405	1		T402	11		T442	21
values[33]	430	1			T405	1		T402	8		T442	17
values[34]	395	1			T405	1		T402	11		T442	19
values[35]	402	1			T405	1		T402	6		T442	16
values[36]	445	1			T405	1		T402	7		T442	26
values[37]	444	1			T405	1		T402	10		T442	25
values[38]	455	1			T405	1		T402	11		T442	19
values[39]	429	1			T405	1		T402	25		T442	30
values[40]	386	1			T405	1		T402	14		T442	29
values[41]	352	1			T405	1		T402	8		T442	26
values[42]	288	1			T405	1		T402	7		T442	15
values[43]	304	1			T405	1		T402	13		T442	12
values[44]	279	1			T405	1		T402	9		T442	12
values[45]	260	1			T405	1		T442	3		T578	1
values[46]	252	1			T405	1		T442	8		T447	6
values[47]	244	1			T405	1		T442	5		T447	7
values[48]	241	1			T405	1		T442	14		T447	6
values[49]	220	1			T405	1		T447	6		T763	5
values[50]	173	1			T405	1		T447	15		T763	11
values[51]	155	1			T405	1		T447	11		T763	8
values[52]	165	1			T405	1		T447	11		T763	10
values[53]	138	1			T405	1		T447	9		T763	2
values[54]	121	1			T405	1		T447	7		T763	2
values[55]	102	1			T405	1		T447	13		T763	2
values[56]	97	1			T405	1		T447	8		T763	3
values[57]	113	1			T405	1		T447	6		T763	1
values[58]	128	1			T405	1		T447	11		T763	2
values[59]	107	1			T405	1		T447	8		T763	3
values[60]	92	1			T405	1		T447	7		T763	3
values[61]	100	1			T405	1		T447	13		T763	3
values[62]	111	1			T405	1		T447	31		T763	1
values[63]	96	1			T405	1		T447	23		T763	10
values[64]	93	1			T405	1		T447	23		T763	8
values[65]	102	1			T405	1		T447	11		T763	2
values[66]	85	1			T405	1		T447	9		T763	1
values[67]	84	1			T405	1		T447	6		T763	4
values[68]	90	1			T405	1		T447	7		T763	2
values[69]	111	1			T405	1		T447	3		T763	2
values[70]	84	1			T405	1		T447	3		T763	1
values[71]	102	1			T405	1		T447	2		T763	1
values[72]	97	1			T405	1		T447	4		T763	2
values[73]	96	1			T405	1		T447	3		T763	3
values[74]	100	1			T405	1		T447	2		T763	9
values[75]	96	1			T405	1		T447	6		T763	5
values[76]	109	1			T405	1		T447	2		T763	11
values[77]	98	1			T405	1		T447	2		T763	15
values[78]	134	1			T405	1		T447	2		T763	19
values[79]	114	1			T405	1		T447	1		T763	20
values[80]	94	1			T405	1		T447	2		T763	5
values[81]	94	1			T405	1		T447	2		T763	7
values[82]	94	1			T405	1		T447	1		T763	10
values[83]	99	1			T405	1		T447	4		T763	6
values[84]	75	1			T405	1		T447	3		T763	8
values[85]	76	1			T405	1		T447	2		T763	3
values[86]	81	1			T405	1		T447	10		T763	7
values[87]	87	1			T405	1		T447	8		T763	4
values[88]	111	1			T405	1		T447	6		T763	25
values[89]	98	1			T405	1		T447	1		T763	14
values[90]	74	1			T405	1		T447	2		T763	4
values[91]	84	1			T405	1		T447	3		T763	13
values[92]	94	1			T405	1		T447	3		T763	6
values[93]	109	1			T405	2		T447	1		T763	14
values[94]	85	1			T405	1		T447	3		T763	13
values[95]	69	1			T405	1		T447	4		T763	6
values[96]	74	1			T405	1		T447	2		T780	1
values[97]	66	1			T405	1		T447	3		T780	1
values[98]	81	1			T405	1		T447	5		T780	1
values[99]	75	1			T405	4		T447	5		T780	1
values[100]	77	1			T405	2		T447	5		T780	2
values[101]	53	1			T405	1		T447	3		T780	1
values[102]	68	1			T405	2		T447	4		T780	1
values[103]	63	1			T405	1		T447	2		T780	2
values[104]	64	1			T405	3		T447	1		T780	3
values[105]	83	1			T405	4		T447	7		T780	2
values[106]	77	1			T405	2		T447	4		T780	3
values[107]	67	1			T405	1		T447	1		T780	5
values[108]	71	1			T405	1		T447	1		T780	9
values[109]	56	1			T405	1		T447	5		T780	2
values[110]	57	1			T405	4		T447	5		T780	5
values[111]	54	1			T405	3		T447	6		T780	2
values[112]	53	1			T405	2		T447	7		T780	3
values[113]	60	1			T405	1		T447	10		T780	6
values[114]	51	1			T405	3		T447	5		T780	4
values[115]	43	1			T405	2		T447	2		T780	1
values[116]	55	1			T405	2		T447	15		T780	1
values[117]	40	1			T405	1		T447	2		T780	3
values[118]	37	1			T405	3		T447	8		T780	1
values[119]	38	1			T405	2		T447	5		T780	2
values[120]	40	1			T405	5		T447	4		T780	4
values[121]	35	1			T405	1		T447	3		T780	1
values[122]	45	1			T405	1		T447	8		T780	4
values[123]	52	1			T405	2		T447	4		T780	1
values[124]	54	1			T405	1		T447	7		T780	2
values[125]	51	1			T405	2		T447	10		T780	4
values[126]	92	1			T405	7		T447	7		T780	3
values[127]	1291	1			T405	58		T447	7		T780	52
values[128]	6163	1			T405	348		T447	4		T780	305