Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	165210	1			T77	706		T81	21		T82	134
values[2]	5377	1			T82	3		T512	2		T496	1
values[3]	2447	1			T496	1		T405	1		T750	51
values[4]	1699	1			T405	1		T750	57		T400	1
values[5]	1258	1			T405	1		T750	74		T400	1
values[6]	1183	1			T405	1		T750	86		T400	1
values[7]	1064	1			T405	1		T750	62		T400	1
values[8]	1006	1			T405	1		T750	41		T400	1
values[9]	981	1			T405	1		T750	31		T400	1
values[10]	812	1			T405	1		T750	14		T400	1
values[11]	819	1			T405	1		T750	11		T400	1
values[12]	707	1			T405	1		T750	10		T400	1
values[13]	550	1			T405	1		T750	5		T400	1
values[14]	434	1			T405	1		T750	2		T400	1
values[15]	365	1			T405	1		T400	1		T753	10
values[16]	411	1			T405	1		T400	1		T753	10
values[17]	494	1			T405	1		T400	1		T753	9
values[18]	468	1			T405	1		T400	1		T753	9
values[19]	424	1			T405	1		T400	1		T753	7
values[20]	309	1			T405	1		T400	1		T753	5
values[21]	271	1			T405	1		T400	1		T753	13
values[22]	287	1			T405	1		T400	1		T753	15
values[23]	337	1			T405	1		T400	1		T753	13
values[24]	298	1			T405	1		T400	1		T753	24
values[25]	269	1			T405	1		T400	1		T753	36
values[26]	237	1			T405	1		T400	1		T753	20
values[27]	257	1			T405	1		T400	1		T753	32
values[28]	254	1			T405	1		T400	1		T753	6
values[29]	234	1			T405	1		T400	1		T753	7
values[30]	243	1			T405	1		T400	1		T753	4
values[31]	207	1			T405	1		T400	1		T753	5
values[32]	156	1			T405	1		T400	1		T753	5
values[33]	135	1			T405	1		T400	1		T753	1
values[34]	155	1			T405	1		T400	1		T748	1
values[35]	139	1			T405	1		T400	1		T748	1
values[36]	100	1			T405	1		T400	1		T748	1
values[37]	120	1			T405	1		T400	1		T748	2
values[38]	84	1			T405	1		T400	1		T748	1
values[39]	72	1			T405	1		T400	1		T748	1
values[40]	75	1			T405	1		T400	1		T748	1
values[41]	80	1			T405	1		T400	1		T748	1
values[42]	68	1			T405	1		T400	1		T748	1
values[43]	77	1			T405	1		T400	1		T748	1
values[44]	76	1			T405	1		T400	1		T748	1
values[45]	73	1			T405	1		T400	1		T748	1
values[46]	91	1			T405	1		T400	1		T748	1
values[47]	85	1			T405	1		T400	1		T748	1
values[48]	66	1			T405	1		T400	1		T748	1
values[49]	74	1			T405	1		T400	1		T748	1
values[50]	81	1			T405	1		T400	1		T748	1
values[51]	88	1			T405	1		T400	1		T748	1
values[52]	96	1			T405	1		T400	1		T748	1
values[53]	84	1			T405	1		T400	1		T748	1
values[54]	72	1			T405	1		T400	1		T748	1
values[55]	73	1			T405	1		T400	1		T748	1
values[56]	79	1			T405	1		T400	1		T748	1
values[57]	75	1			T405	1		T400	1		T748	1
values[58]	66	1			T405	1		T400	1		T748	1
values[59]	76	1			T405	1		T400	1		T748	1
values[60]	67	1			T405	1		T400	1		T748	1
values[61]	63	1			T405	1		T400	1		T748	1
values[62]	74	1			T405	1		T400	1		T748	1
values[63]	71	1			T405	1		T400	1		T748	1
values[64]	65	1			T405	1		T400	1		T748	1
values[65]	68	1			T405	1		T400	1		T748	1
values[66]	73	1			T405	1		T400	1		T748	1
values[67]	67	1			T405	1		T400	1		T748	1
values[68]	70	1			T405	1		T400	1		T748	1
values[69]	73	1			T405	1		T400	1		T748	1
values[70]	56	1			T405	1		T400	1		T748	1
values[71]	70	1			T405	1		T400	1		T748	1
values[72]	64	1			T405	1		T400	1		T748	1
values[73]	70	1			T405	1		T400	1		T748	1
values[74]	74	1			T405	1		T400	1		T748	1
values[75]	70	1			T405	1		T400	1		T748	1
values[76]	85	1			T405	1		T400	1		T748	1
values[77]	81	1			T405	1		T400	1		T748	1
values[78]	101	1			T405	1		T400	1		T748	1
values[79]	92	1			T405	1		T400	1		T748	1
values[80]	86	1			T405	1		T400	1		T748	2
values[81]	104	1			T405	1		T400	1		T748	3
values[82]	102	1			T405	1		T400	1		T748	6
values[83]	109	1			T405	1		T400	1		T748	4
values[84]	118	1			T405	1		T400	1		T748	3
values[85]	95	1			T405	1		T400	1		T748	6
values[86]	96	1			T405	1		T400	1		T748	1
values[87]	97	1			T405	1		T400	1		T748	1
values[88]	103	1			T405	1		T400	1		T748	1
values[89]	86	1			T405	1		T400	1		T748	1
values[90]	88	1			T405	1		T400	1		T748	1
values[91]	98	1			T405	1		T400	1		T748	3
values[92]	88	1			T405	1		T400	1		T748	3
values[93]	117	1			T405	1		T400	1		T748	2
values[94]	105	1			T405	1		T400	1		T748	3
values[95]	121	1			T405	1		T400	1		T748	1
values[96]	98	1			T405	1		T400	1		T748	3
values[97]	118	1			T405	1		T400	1		T748	1
values[98]	101	1			T405	1		T400	1		T748	3
values[99]	100	1			T405	1		T400	1		T748	5
values[100]	92	1			T405	1		T400	1		T748	1
values[101]	91	1			T405	1		T400	1		T748	3
values[102]	87	1			T405	1		T400	2		T748	2
values[103]	106	1			T405	1		T400	1		T748	1
values[104]	113	1			T405	1		T400	1		T748	3
values[105]	125	1			T405	1		T400	1		T748	1
values[106]	99	1			T405	1		T400	1		T748	1
values[107]	134	1			T405	1		T400	1		T748	8
values[108]	114	1			T405	1		T400	1		T748	2
values[109]	119	1			T405	1		T400	1		T748	1
values[110]	131	1			T405	1		T400	1		T748	2
values[111]	127	1			T405	2		T400	1		T748	1
values[112]	125	1			T405	1		T400	1		T748	3
values[113]	131	1			T405	1		T400	1		T748	1
values[114]	112	1			T405	1		T400	1		T748	3
values[115]	98	1			T405	1		T400	1		T748	5
values[116]	98	1			T405	1		T400	1		T748	4
values[117]	117	1			T405	1		T400	1		T748	1
values[118]	129	1			T405	1		T400	1		T748	2
values[119]	127	1			T405	1		T400	1		T748	1
values[120]	121	1			T405	2		T400	1		T748	2
values[121]	104	1			T405	3		T400	1		T748	1
values[122]	133	1			T405	3		T400	1		T748	1
values[123]	125	1			T405	1		T400	2		T748	1
values[124]	244	1			T405	1		T400	2		T748	3
values[125]	416	1			T405	5		T400	2		T748	3
values[126]	918	1			T405	17		T400	7		T748	23
values[127]	3051	1			T405	100		T400	89		T748	133
values[128]	5056	1			T405	177		T400	199		T748	177