Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 50 0 50 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 50 0 50 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 50 0 50 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 508 1 T82 3 T399 1 T425 2
all_values[1] 488 1 T82 2 T399 1 T565 1
all_values[2] 505 1 T77 1 T82 4 T786 1
all_values[3] 538 1 T82 2 T424 1 T425 3
all_values[4] 517 1 T82 2 T399 1 T425 3
all_values[5] 509 1 T82 3 T399 2 T425 4
all_values[6] 520 1 T82 1 T399 1 T425 1
all_values[7] 507 1 T77 1 T399 2 T425 1
all_values[8] 499 1 T77 1 T399 2 T565 1
all_values[9] 488 1 T82 2 T399 3 T403 3
all_values[10] 516 1 T82 5 T399 1 T403 1
all_values[11] 507 1 T491 2 T399 2 T425 1
all_values[12] 491 1 T82 4 T662 1 T399 2
all_values[13] 486 1 T82 2 T491 1 T565 1
all_values[14] 517 1 T77 2 T399 3 T403 2
all_values[15] 515 1 T77 1 T82 4 T230 1
all_values[16] 496 1 T82 3 T662 1 T399 1
all_values[17] 539 1 T82 4 T491 1 T399 1
all_values[18] 534 1 T82 2 T399 2 T425 1
all_values[19] 515 1 T77 1 T82 2 T664 1
all_values[20] 508 1 T77 1 T82 1 T399 2
all_values[21] 510 1 T82 6 T491 1 T548 2
all_values[22] 485 1 T77 1 T82 4 T399 2
all_values[23] 502 1 T82 2 T230 1 T399 2
all_values[24] 541 1 T82 1 T425 2 T403 2
all_values[25] 493 1 T82 1 T491 1 T425 2
all_values[26] 488 1 T82 5 T399 2 T425 2
all_values[27] 485 1 T77 1 T82 3 T491 1
all_values[28] 541 1 T491 1 T399 1 T565 1
all_values[29] 525 1 T424 1 T399 1 T604 1
all_values[30] 510 1 T82 2 T399 1 T425 1
all_values[31] 497 1 T77 1 T82 1 T399 1
all_values[32] 485 1 T82 1 T399 2 T425 1
all_values[33] 503 1 T77 1 T82 1 T399 1
all_values[34] 493 1 T77 1 T82 2 T399 1
all_values[35] 509 1 T82 1 T491 1 T399 2
all_values[36] 522 1 T82 4 T399 3 T548 1
all_values[37] 525 1 T82 1 T664 1 T425 2
all_values[38] 507 1 T77 1 T424 1 T399 1
all_values[39] 451 1 T424 1 T399 2 T425 1
all_values[40] 463 1 T399 1 T403 1 T548 4
all_values[41] 498 1 T82 2 T399 1 T565 1
all_values[42] 488 1 T77 1 T82 3 T491 1
all_values[43] 508 1 T82 2 T399 1 T664 1
all_values[44] 498 1 T491 1 T399 1 T403 1
all_values[45] 478 1 T77 2 T82 1 T399 1
all_values[46] 500 1 T82 3 T399 1 T403 1
all_values[47] 459 1 T82 2 T399 1 T403 2
all_values[48] 513 1 T82 1 T491 1 T399 1
all_values[49] 495 1 T82 2 T399 4 T664 1

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