Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3624	1			T77	3		T82	7		T424	5
all_values[1]	3712	1			T77	4		T82	13		T424	2
all_values[2]	3765	1			T77	4		T82	13		T424	5
all_values[3]	3765	1			T77	2		T82	10		T424	6
all_values[4]	3644	1			T77	2		T82	11		T424	2
all_values[5]	3678	1			T77	2		T82	6		T424	3
all_values[6]	3883	1			T77	3		T82	10		T424	3
all_values[7]	3768	1			T77	3		T82	13		T424	10
all_values[8]	3713	1			T77	2		T82	6		T424	10
all_values[9]	3744	1			T77	6		T82	6		T424	4
all_values[10]	3684	1			T77	4		T82	7		T424	7
all_values[11]	3774	1			T77	3		T82	6		T424	3
all_values[12]	3736	1			T77	2		T82	7		T424	7
all_values[13]	3711	1			T77	4		T82	14		T424	2
all_values[14]	3774	1			T82	8		T424	8		T399	6
all_values[15]	3686	1			T77	3		T82	8		T424	5
all_values[16]	3785	1			T77	2		T82	6		T424	5
all_values[17]	3734	1			T77	1		T82	8		T424	5
all_values[18]	3653	1			T77	4		T82	10		T424	6
all_values[19]	3706	1			T77	4		T82	9		T424	6
all_values[20]	3689	1			T77	3		T82	6		T424	5
all_values[21]	3696	1			T77	3		T82	14		T424	6
all_values[22]	3684	1			T77	2		T82	9		T424	5
all_values[23]	3781	1			T77	3		T82	8		T424	8
all_values[24]	3709	1			T77	1		T82	6		T424	5
all_values[25]	3648	1			T82	8		T424	7		T399	7
all_values[26]	3774	1			T77	1		T82	10		T424	6
all_values[27]	3770	1			T77	7		T82	8		T424	5
all_values[28]	3736	1			T77	2		T82	7		T424	4
all_values[29]	3742	1			T77	2		T82	8		T424	3
all_values[30]	3659	1			T82	8		T424	2		T399	5
all_values[31]	3760	1			T77	4		T82	7		T424	9
all_values[32]	3841	1			T77	2		T82	15		T424	3
all_values[33]	3780	1			T77	1		T82	7		T424	1
all_values[34]	3677	1			T77	7		T82	3		T424	4
all_values[35]	3761	1			T77	5		T82	9		T424	4
all_values[36]	3682	1			T77	2		T82	8		T424	2
all_values[37]	3693	1			T77	2		T82	4		T424	7
all_values[38]	3637	1			T77	4		T82	12		T424	2
all_values[39]	3795	1			T82	8		T424	6		T399	10
all_values[40]	3677	1			T77	1		T82	7		T424	5
all_values[41]	3773	1			T77	3		T82	7		T424	7
all_values[42]	3716	1			T77	5		T82	12		T424	5
all_values[43]	3848	1			T77	4		T82	9		T424	2
all_values[44]	3690	1			T77	2		T82	3		T424	6
all_values[45]	3675	1			T77	5		T82	11		T424	7
all_values[46]	3859	1			T77	3		T82	7		T424	5
all_values[47]	3701	1			T77	6		T82	8		T424	6
all_values[48]	3704	1			T77	3		T82	4		T424	4
all_values[49]	3641	1			T77	2		T82	5		T424	4
all_values[50]	3733	1			T77	3		T82	10		T424	7
all_values[51]	3720	1			T77	4		T82	3		T424	10
all_values[52]	3779	1			T77	3		T82	7		T424	5
all_values[53]	3639	1			T77	3		T82	8		T424	5
all_values[54]	3761	1			T77	2		T82	11		T424	8
all_values[55]	3755	1			T77	1		T82	8		T424	7
all_values[56]	3633	1			T77	3		T82	2		T424	2
all_values[57]	3730	1			T77	1		T82	10		T424	2
all_values[58]	3813	1			T77	3		T82	9		T424	11
all_values[59]	3663	1			T77	2		T82	7		T424	9
all_values[60]	3706	1			T77	2		T82	9		T424	7
all_values[61]	3711	1			T77	7		T82	5		T424	8
all_values[62]	3792	1			T77	3		T82	14		T424	4
all_values[63]	3784	1			T82	11		T424	6		T399	6