Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	146792	1			T75	88		T79	8		T107	5
values[2]	10711	1			T75	2		T107	1		T157	1
values[3]	3698	1			T107	1		T433	1		T520	4
values[4]	2056	1			T520	6		T776	1		T777	1
values[5]	1429	1			T520	3		T776	1		T777	1
values[6]	1068	1			T520	12		T776	1		T777	1
values[7]	703	1			T520	6		T776	1		T777	1
values[8]	505	1			T520	5		T776	1		T777	1
values[9]	393	1			T520	3		T776	1		T777	1
values[10]	414	1			T520	5		T776	1		T777	1
values[11]	412	1			T520	13		T776	1		T777	1
values[12]	374	1			T520	5		T776	1		T777	1
values[13]	376	1			T520	3		T776	1		T777	1
values[14]	346	1			T520	9		T776	1		T777	1
values[15]	368	1			T520	12		T776	1		T777	1
values[16]	373	1			T520	3		T776	1		T777	1
values[17]	324	1			T520	4		T776	1		T777	1
values[18]	301	1			T520	4		T776	1		T777	1
values[19]	305	1			T520	5		T776	1		T777	1
values[20]	323	1			T520	4		T776	1		T777	1
values[21]	378	1			T520	7		T776	1		T777	1
values[22]	271	1			T520	13		T776	1		T777	1
values[23]	274	1			T520	7		T776	1		T777	1
values[24]	255	1			T520	5		T776	1		T777	1
values[25]	323	1			T520	10		T776	1		T777	1
values[26]	285	1			T520	5		T776	1		T777	1
values[27]	277	1			T520	8		T776	1		T777	1
values[28]	296	1			T520	9		T776	1		T777	1
values[29]	271	1			T520	3		T776	1		T777	1
values[30]	265	1			T520	4		T776	1		T777	1
values[31]	283	1			T520	8		T776	1		T777	1
values[32]	303	1			T520	12		T776	1		T777	1
values[33]	263	1			T520	4		T776	1		T777	1
values[34]	308	1			T520	17		T776	1		T777	1
values[35]	267	1			T520	10		T776	1		T777	1
values[36]	282	1			T520	14		T776	1		T777	1
values[37]	281	1			T520	5		T776	1		T777	1
values[38]	330	1			T520	6		T776	1		T777	1
values[39]	283	1			T520	3		T776	1		T777	1
values[40]	284	1			T520	6		T776	1		T777	1
values[41]	276	1			T520	4		T776	1		T777	1
values[42]	273	1			T520	7		T776	1		T777	1
values[43]	296	1			T520	7		T776	1		T777	1
values[44]	258	1			T520	4		T776	1		T777	1
values[45]	292	1			T520	5		T776	1		T777	1
values[46]	263	1			T520	4		T776	1		T777	1
values[47]	279	1			T520	5		T776	1		T777	1
values[48]	269	1			T520	11		T776	1		T777	1
values[49]	237	1			T520	3		T776	1		T777	1
values[50]	268	1			T520	11		T776	1		T777	1
values[51]	288	1			T520	6		T776	1		T777	1
values[52]	242	1			T520	5		T776	1		T777	1
values[53]	231	1			T776	1		T777	1		T636	5
values[54]	242	1			T776	1		T777	1		T636	7
values[55]	262	1			T776	1		T777	1		T636	4
values[56]	255	1			T776	1		T777	1		T636	4
values[57]	275	1			T776	1		T777	1		T636	5
values[58]	221	1			T776	1		T777	1		T636	9
values[59]	203	1			T776	1		T777	1		T636	9
values[60]	246	1			T776	1		T777	1		T636	6
values[61]	248	1			T776	1		T777	1		T636	4
values[62]	184	1			T776	1		T777	1		T636	8
values[63]	179	1			T776	1		T777	1		T636	11
values[64]	166	1			T776	1		T777	1		T636	2
values[65]	157	1			T776	1		T777	1		T636	6
values[66]	174	1			T776	1		T777	1		T636	7
values[67]	164	1			T776	1		T777	1		T636	11
values[68]	125	1			T776	1		T777	1		T636	9
values[69]	140	1			T776	1		T777	1		T636	7
values[70]	107	1			T776	1		T777	1		T636	4
values[71]	115	1			T776	1		T777	1		T636	5
values[72]	99	1			T776	1		T777	1		T636	8
values[73]	97	1			T776	1		T777	1		T636	2
values[74]	85	1			T776	1		T777	1		T480	1
values[75]	102	1			T776	1		T777	1		T480	1
values[76]	97	1			T776	1		T777	1		T480	1
values[77]	108	1			T776	1		T777	1		T480	1
values[78]	89	1			T776	1		T777	1		T480	1
values[79]	92	1			T776	1		T777	1		T480	1
values[80]	89	1			T776	1		T777	1		T480	1
values[81]	82	1			T776	1		T777	1		T480	1
values[82]	90	1			T776	1		T777	2		T480	1
values[83]	92	1			T776	1		T777	1		T480	2
values[84]	85	1			T776	1		T777	1		T480	1
values[85]	112	1			T776	1		T777	1		T480	1
values[86]	107	1			T776	1		T777	1		T480	1
values[87]	93	1			T776	1		T777	1		T480	1
values[88]	84	1			T776	1		T777	1		T480	1
values[89]	99	1			T776	2		T777	1		T480	1
values[90]	58	1			T776	1		T777	1		T480	1
values[91]	94	1			T776	1		T777	1		T480	1
values[92]	88	1			T776	1		T777	1		T480	1
values[93]	115	1			T776	1		T777	1		T480	1
values[94]	117	1			T776	1		T777	1		T480	1
values[95]	99	1			T776	1		T777	1		T480	1
values[96]	91	1			T776	1		T777	1		T480	1
values[97]	89	1			T776	1		T777	1		T480	1
values[98]	106	1			T776	1		T777	1		T480	1
values[99]	74	1			T776	1		T777	1		T480	1
values[100]	76	1			T776	1		T777	4		T480	1
values[101]	95	1			T776	1		T777	1		T480	1
values[102]	106	1			T776	1		T777	1		T480	1
values[103]	84	1			T776	1		T777	2		T480	1
values[104]	93	1			T776	1		T777	1		T480	1
values[105]	97	1			T776	1		T777	3		T480	1
values[106]	83	1			T776	1		T777	1		T480	2
values[107]	97	1			T776	1		T777	1		T480	3
values[108]	102	1			T776	1		T777	1		T480	1
values[109]	105	1			T776	1		T777	4		T480	6
values[110]	93	1			T776	1		T777	1		T480	3
values[111]	89	1			T776	1		T777	1		T480	2
values[112]	90	1			T776	1		T777	2		T480	1
values[113]	84	1			T776	1		T777	2		T480	1
values[114]	102	1			T776	1		T777	1		T480	5
values[115]	79	1			T776	1		T777	3		T480	1
values[116]	66	1			T776	1		T777	1		T480	5
values[117]	85	1			T776	1		T777	1		T480	1
values[118]	75	1			T776	1		T777	2		T480	1
values[119]	75	1			T776	2		T777	1		T480	1
values[120]	91	1			T776	1		T777	2		T480	1
values[121]	65	1			T776	3		T777	1		T480	1
values[122]	67	1			T776	2		T777	1		T480	3
values[123]	94	1			T776	6		T777	9		T480	4
values[124]	82	1			T776	2		T777	1		T480	1
values[125]	94	1			T776	1		T777	1		T480	3
values[126]	193	1			T776	3		T777	2		T480	1
values[127]	877	1			T776	30		T777	34		T480	24
values[128]	6642	1			T776	353		T777	313		T480	280

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	156209	1			T75	70		T79	5		T107	3
values[2]	5015	1			T428	2		T522	1		T433	6
values[3]	2681	1			T521	1		T441	2		T432	1
values[4]	1957	1			T521	1		T441	2		T459	1
values[5]	1565	1			T521	1		T441	3		T459	1
values[6]	1202	1			T521	1		T441	2		T459	1
values[7]	945	1			T521	1		T441	1		T459	1
values[8]	740	1			T521	1		T441	2		T459	1
values[9]	610	1			T521	1		T441	6		T459	1
values[10]	608	1			T521	1		T441	5		T459	1
values[11]	657	1			T521	1		T441	4		T459	1
values[12]	667	1			T521	1		T441	3		T459	1
values[13]	619	1			T521	1		T441	2		T459	1
values[14]	595	1			T521	1		T441	3		T459	1
values[15]	636	1			T521	1		T441	5		T459	1
values[16]	593	1			T521	1		T441	7		T459	1
values[17]	549	1			T521	1		T441	5		T459	1
values[18]	445	1			T521	1		T441	2		T459	1
values[19]	400	1			T521	1		T441	1		T459	1
values[20]	320	1			T521	1		T441	1		T459	2
values[21]	259	1			T521	1		T441	2		T459	1
values[22]	223	1			T521	1		T441	3		T459	1
values[23]	146	1			T521	1		T441	2		T459	1
values[24]	136	1			T521	1		T441	2		T459	1
values[25]	157	1			T521	1		T441	2		T459	1
values[26]	173	1			T521	1		T441	3		T459	1
values[27]	142	1			T521	1		T441	1		T459	1
values[28]	108	1			T521	1		T441	1		T459	1
values[29]	96	1			T521	1		T441	2		T459	1
values[30]	109	1			T521	1		T441	2		T459	1
values[31]	52	1			T521	1		T441	2		T459	1
values[32]	43	1			T521	1		T441	1		T459	1
values[33]	50	1			T521	1		T441	1		T459	1
values[34]	50	1			T521	1		T441	3		T459	1
values[35]	42	1			T521	1		T441	3		T459	1
values[36]	42	1			T521	1		T441	1		T459	1
values[37]	41	1			T521	1		T441	1		T459	1
values[38]	52	1			T521	1		T441	9		T459	1
values[39]	40	1			T521	1		T441	4		T459	1
values[40]	38	1			T521	1		T441	1		T459	1
values[41]	39	1			T521	1		T441	1		T459	1
values[42]	50	1			T521	1		T441	3		T459	1
values[43]	38	1			T521	1		T441	5		T459	1
values[44]	38	1			T521	1		T441	6		T459	1
values[45]	36	1			T521	1		T441	1		T459	1
values[46]	36	1			T521	1		T441	1		T459	1
values[47]	34	1			T521	1		T441	3		T459	1
values[48]	25	1			T521	1		T441	1		T459	1
values[49]	42	1			T521	1		T441	1		T459	1
values[50]	37	1			T521	1		T441	2		T459	1
values[51]	37	1			T521	1		T441	2		T459	1
values[52]	42	1			T521	1		T441	4		T459	1
values[53]	34	1			T521	1		T441	2		T459	1
values[54]	31	1			T521	1		T441	1		T459	1
values[55]	26	1			T521	1		T441	3		T459	1
values[56]	34	1			T521	1		T441	1		T459	1
values[57]	33	1			T521	1		T441	3		T459	1
values[58]	38	1			T521	2		T441	8		T459	1
values[59]	33	1			T521	1		T441	6		T459	1
values[60]	33	1			T521	1		T441	2		T459	1
values[61]	26	1			T521	1		T441	3		T459	1
values[62]	25	1			T521	1		T441	2		T459	1
values[63]	34	1			T521	1		T441	2		T459	1
values[64]	32	1			T521	1		T441	1		T459	1
values[65]	41	1			T521	1		T441	2		T459	1
values[66]	32	1			T521	1		T441	3		T459	1
values[67]	33	1			T521	1		T441	3		T459	1
values[68]	30	1			T521	1		T441	2		T459	1
values[69]	30	1			T521	1		T441	1		T459	1
values[70]	32	1			T521	1		T441	5		T459	1
values[71]	36	1			T521	1		T441	5		T459	1
values[72]	42	1			T521	1		T441	4		T459	1
values[73]	42	1			T521	1		T441	1		T459	1
values[74]	34	1			T521	1		T441	2		T459	1
values[75]	29	1			T521	1		T441	4		T459	1
values[76]	45	1			T521	1		T441	5		T459	1
values[77]	51	1			T521	1		T441	4		T459	1
values[78]	45	1			T521	1		T441	3		T459	1
values[79]	40	1			T521	1		T441	1		T459	1
values[80]	36	1			T521	1		T441	2		T459	1
values[81]	45	1			T521	1		T441	5		T459	1
values[82]	34	1			T521	1		T441	5		T459	2
values[83]	37	1			T521	1		T441	4		T459	1
values[84]	32	1			T521	1		T441	1		T459	1
values[85]	34	1			T521	1		T441	2		T459	1
values[86]	41	1			T521	1		T441	2		T459	1
values[87]	35	1			T521	1		T441	5		T459	1
values[88]	41	1			T521	1		T441	3		T459	1
values[89]	35	1			T521	1		T441	1		T459	1
values[90]	31	1			T521	1		T441	1		T459	1
values[91]	46	1			T521	3		T441	1		T459	1
values[92]	49	1			T521	2		T441	2		T459	1
values[93]	52	1			T521	1		T441	2		T459	1
values[94]	51	1			T521	5		T441	3		T459	1
values[95]	66	1			T521	1		T441	1		T459	1
values[96]	43	1			T521	1		T441	3		T459	1
values[97]	60	1			T521	3		T441	3		T459	1
values[98]	51	1			T521	1		T441	4		T459	1
values[99]	50	1			T521	1		T441	2		T459	1
values[100]	50	1			T521	4		T441	3		T459	1
values[101]	48	1			T521	5		T441	3		T459	1
values[102]	68	1			T521	2		T441	5		T459	1
values[103]	46	1			T521	2		T441	2		T459	1
values[104]	50	1			T521	2		T441	3		T459	1
values[105]	70	1			T521	1		T441	3		T459	1
values[106]	67	1			T521	5		T441	3		T459	1
values[107]	54	1			T521	2		T441	7		T459	1
values[108]	57	1			T521	2		T441	6		T459	1
values[109]	53	1			T521	2		T441	7		T459	1
values[110]	53	1			T521	1		T441	7		T459	1
values[111]	67	1			T521	2		T441	9		T459	1
values[112]	44	1			T521	3		T441	2		T459	1
values[113]	43	1			T521	2		T441	3		T459	1
values[114]	34	1			T521	1		T441	3		T459	1
values[115]	40	1			T521	3		T441	2		T459	1
values[116]	48	1			T521	2		T441	2		T459	1
values[117]	43	1			T521	2		T441	1		T459	1
values[118]	50	1			T521	2		T441	1		T459	1
values[119]	56	1			T521	1		T441	4		T459	1
values[120]	60	1			T521	3		T441	6		T459	2
values[121]	68	1			T521	3		T441	3		T459	1
values[122]	70	1			T521	3		T441	4		T459	1
values[123]	58	1			T521	3		T441	9		T459	2
values[124]	110	1			T521	1		T441	24		T459	4
values[125]	222	1			T521	1		T441	62		T459	3
values[126]	447	1			T521	9		T441	89		T459	11
values[127]	1403	1			T521	114		T441	30		T459	151
values[128]	2572	1			T521	240		T441	1		T459	260

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	145500	1			T75	60		T79	2		T107	2
values[2]	11756	1			T75	1		T80	1		T157	6
values[3]	4614	1			T427	55		T433	1		T520	19
values[4]	2599	1			T427	6		T520	16		T527	32
values[5]	1607	1			T427	3		T520	18		T527	14
values[6]	1044	1			T427	2		T520	15		T527	22
values[7]	793	1			T520	22		T527	13		T480	1
values[8]	560	1			T520	20		T527	17		T480	1
values[9]	541	1			T520	6		T527	22		T480	1
values[10]	503	1			T520	16		T527	9		T480	1
values[11]	386	1			T520	18		T527	7		T480	1
values[12]	461	1			T520	8		T527	15		T480	1
values[13]	353	1			T520	17		T527	11		T480	1
values[14]	335	1			T520	14		T527	14		T480	1
values[15]	416	1			T520	15		T527	8		T480	1
values[16]	354	1			T520	20		T527	9		T480	1
values[17]	402	1			T520	21		T527	26		T480	1
values[18]	403	1			T520	18		T527	19		T480	1
values[19]	337	1			T520	12		T527	9		T480	1
values[20]	304	1			T520	11		T527	17		T480	1
values[21]	328	1			T520	25		T527	12		T480	1
values[22]	309	1			T520	20		T527	7		T480	1
values[23]	321	1			T520	13		T527	9		T480	1
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