Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.22 95.37 94.53 95.15 95.35 97.38 99.53


Total tests in report: 2844
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
40.61 40.61 45.56 45.56 43.14 43.14 33.34 33.34 58.23 58.23 63.03 63.03 0.38 0.38 /workspace/coverage/default/54.chip_sw_all_escalation_resets.1823173782
50.36 9.75 53.95 8.39 52.09 8.96 37.80 4.46 66.51 8.28 90.76 27.73 1.03 0.66 /workspace/coverage/default/0.chip_jtag_csr_rw.2083314954
55.68 5.32 54.15 0.19 55.54 3.45 38.07 0.28 67.04 0.53 90.76 0.00 28.50 27.46 /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.3968155922
60.96 5.28 65.66 11.52 62.88 7.33 40.90 2.82 77.07 10.03 90.76 0.00 28.50 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_20.1816256112
65.29 4.33 73.67 8.00 71.06 8.18 44.71 3.81 82.35 5.28 90.76 0.00 29.18 0.68 /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.433156082
69.09 3.80 73.67 0.00 71.08 0.03 44.71 0.00 82.35 0.00 90.76 0.00 51.97 22.80 /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.2547330000
72.29 3.20 75.80 2.13 73.77 2.69 56.54 11.83 84.36 2.02 91.31 0.55 51.97 0.00 /workspace/coverage/default/1.rom_raw_unlock.375408544
75.01 2.71 75.80 0.00 73.77 0.00 72.78 16.24 84.36 0.00 91.31 0.00 52.02 0.05 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2858382149
77.35 2.34 79.49 3.69 73.95 0.18 75.44 2.66 84.41 0.04 91.31 0.00 59.51 7.49 /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.3580636765
79.68 2.33 84.68 5.19 77.77 3.82 78.88 3.44 85.93 1.53 91.31 0.00 59.51 0.00 /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2503077551
81.38 1.70 84.68 0.00 79.05 1.27 78.88 0.00 86.16 0.23 91.31 0.00 68.21 8.71 /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.549011176
82.71 1.33 84.68 0.00 79.05 0.00 78.88 0.00 86.16 0.00 91.31 0.00 76.17 7.96 /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.569730714
83.97 1.26 86.66 1.98 81.08 2.03 80.06 1.18 88.56 2.39 91.31 0.00 76.17 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_0.1288761913
84.90 0.93 88.86 2.20 82.38 1.30 81.18 1.12 89.51 0.95 91.31 0.00 76.17 0.00 /workspace/coverage/default/2.chip_sw_gpio.1927738968
85.67 0.77 88.86 0.00 82.42 0.05 81.18 0.00 89.51 0.00 91.31 0.00 80.74 4.57 /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.1538783274
86.43 0.75 89.06 0.19 82.55 0.13 81.20 0.02 89.63 0.12 95.38 4.07 80.74 0.00 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2389607763
87.12 0.70 89.93 0.87 84.14 1.59 81.27 0.08 91.27 1.64 95.38 0.00 80.74 0.00 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3502218667
87.77 0.65 90.55 0.63 84.72 0.58 83.19 1.91 91.87 0.61 95.56 0.18 80.74 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_10.3836353040
88.40 0.62 90.55 0.00 84.81 0.08 83.19 0.00 91.87 0.00 95.56 0.00 84.39 3.65 /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.3180638888
88.90 0.51 90.55 0.00 84.81 0.00 83.19 0.00 91.87 0.00 95.56 0.00 87.43 3.03 /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.536718501
89.40 0.50 91.43 0.88 85.69 0.88 83.72 0.53 92.51 0.63 95.56 0.00 87.49 0.06 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3587812124
89.87 0.47 92.16 0.73 85.83 0.14 83.93 0.22 92.54 0.03 95.56 0.00 89.20 1.72 /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.785857670
90.34 0.47 92.16 0.00 85.83 0.00 83.93 0.00 92.54 0.00 95.56 0.00 92.01 2.81 /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.1003394680
90.80 0.46 92.16 0.00 85.83 0.00 86.68 2.74 92.54 0.00 95.56 0.00 92.01 0.00 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.427316167
91.23 0.44 92.17 0.01 88.00 2.18 86.68 0.00 92.54 0.00 95.56 0.00 92.46 0.45 /workspace/coverage/cover_reg_top/11.chip_tl_errors.17806486
91.63 0.40 92.61 0.44 89.53 1.53 86.74 0.06 92.61 0.07 95.56 0.00 92.75 0.29 /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3136505809
92.01 0.37 93.28 0.68 90.15 0.62 86.83 0.10 93.39 0.78 95.56 0.00 92.82 0.07 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1419032750
92.35 0.35 93.28 0.00 90.15 0.00 87.92 1.09 93.39 0.00 95.56 0.00 93.81 0.99 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1983368309
92.69 0.34 93.28 0.00 90.15 0.00 87.92 0.00 93.39 0.00 95.56 0.00 95.83 2.02 /workspace/coverage/cover_reg_top/96.xbar_access_same_device.1463953799
92.97 0.28 93.28 0.00 90.15 0.00 89.56 1.64 93.39 0.00 95.56 0.00 95.88 0.05 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2193127119
93.21 0.24 93.30 0.01 90.15 0.01 90.92 1.36 93.39 0.00 95.56 0.00 95.92 0.05 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.829061340
93.42 0.21 93.55 0.26 90.41 0.26 90.93 0.01 93.57 0.18 96.12 0.55 95.92 0.00 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.1155580327
93.61 0.19 93.61 0.06 90.89 0.48 90.94 0.02 94.10 0.53 96.12 0.00 95.98 0.06 /workspace/coverage/default/1.chip_jtag_csr_rw.3767355365
93.79 0.18 93.65 0.04 91.01 0.12 91.53 0.58 94.19 0.09 96.30 0.18 96.03 0.05 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2203591948
93.94 0.15 93.65 0.00 91.03 0.02 91.53 0.00 94.19 0.00 96.30 0.00 96.91 0.88 /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.1170623561
94.08 0.15 93.65 0.00 91.05 0.01 91.53 0.00 94.19 0.00 96.30 0.00 97.77 0.86 /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.4249910906
94.20 0.12 93.79 0.14 91.11 0.07 92.03 0.51 94.21 0.02 96.30 0.00 97.78 0.01 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3327671863
94.33 0.12 94.02 0.23 91.37 0.26 92.27 0.24 94.21 0.00 96.30 0.00 97.78 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3905028824
94.44 0.11 94.25 0.22 91.52 0.15 92.41 0.14 94.36 0.15 96.30 0.00 97.78 0.00 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2065769313
94.54 0.10 94.32 0.07 91.60 0.07 92.71 0.30 94.42 0.07 96.30 0.00 97.88 0.11 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1701538707
94.63 0.10 94.32 0.00 92.15 0.56 92.71 0.00 94.42 0.00 96.30 0.00 97.90 0.01 /workspace/coverage/cover_reg_top/23.chip_tl_errors.2655247058
94.71 0.08 94.32 0.00 92.15 0.00 93.17 0.46 94.42 0.00 96.30 0.00 97.90 0.00 /workspace/coverage/default/0.chip_sw_edn_auto_mode.674242165
94.78 0.07 94.33 0.01 92.35 0.19 93.17 0.01 94.64 0.22 96.30 0.00 97.90 0.00 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.843034364
94.84 0.06 94.39 0.05 92.40 0.05 93.18 0.01 94.70 0.06 96.49 0.18 97.91 0.01 /workspace/coverage/default/72.chip_sw_all_escalation_resets.1633984929
94.90 0.06 94.46 0.08 92.57 0.17 93.21 0.03 94.77 0.07 96.49 0.00 97.91 0.00 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.804553676
94.96 0.06 94.46 0.00 92.57 0.00 93.54 0.34 94.77 0.00 96.49 0.00 97.91 0.00 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.600722504
95.01 0.05 94.48 0.01 92.71 0.14 93.55 0.01 94.92 0.15 96.49 0.00 97.91 0.00 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3543258139
95.05 0.04 94.54 0.06 92.76 0.05 93.59 0.04 95.01 0.09 96.49 0.00 97.91 0.00 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1717796010
95.09 0.04 94.55 0.01 92.78 0.01 93.59 0.00 95.04 0.02 96.67 0.18 97.92 0.01 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.136761288
95.13 0.04 94.55 0.00 92.78 0.00 93.84 0.24 95.04 0.00 96.67 0.00 97.92 0.00 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1547517210
95.17 0.04 94.56 0.01 92.79 0.02 93.84 0.01 95.05 0.01 96.86 0.18 97.93 0.01 /workspace/coverage/default/79.chip_sw_all_escalation_resets.533316856
95.21 0.04 94.56 0.01 92.81 0.01 93.84 0.00 95.05 0.01 97.04 0.18 97.94 0.01 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2573279090
95.25 0.04 94.57 0.01 92.82 0.01 93.85 0.01 95.06 0.01 97.23 0.18 97.96 0.01 /workspace/coverage/default/49.chip_sw_all_escalation_resets.974088735
95.28 0.04 94.57 0.01 92.83 0.01 93.86 0.01 95.07 0.01 97.41 0.18 97.96 0.00 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.1258960716
95.32 0.04 94.57 0.00 93.04 0.21 93.86 0.00 95.07 0.00 97.41 0.00 97.96 0.00 /workspace/coverage/cover_reg_top/25.chip_tl_errors.4042510211
95.35 0.03 94.60 0.03 93.10 0.06 93.94 0.08 95.10 0.03 97.41 0.00 97.96 0.00 /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.208657968
95.38 0.03 94.61 0.01 93.11 0.01 94.11 0.17 95.10 0.00 97.41 0.00 97.96 0.00 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1088397024
95.41 0.03 94.61 0.00 93.11 0.01 94.11 0.00 95.10 0.00 97.41 0.00 98.13 0.18 /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.4042625934
95.44 0.03 94.63 0.02 93.15 0.03 94.12 0.01 95.10 0.00 97.41 0.00 98.25 0.12 /workspace/coverage/default/0.chip_sw_alert_test.1394944814
95.47 0.03 94.63 0.00 93.22 0.07 94.12 0.00 95.14 0.03 97.41 0.00 98.31 0.06 /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.1805813837
95.50 0.03 94.69 0.05 93.27 0.05 94.14 0.03 95.16 0.02 97.41 0.00 98.31 0.00 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.2851612660
95.52 0.03 94.76 0.08 93.27 0.00 94.21 0.07 95.17 0.01 97.41 0.00 98.31 0.00 /workspace/coverage/default/3.chip_tap_straps_rma.4268935572
95.55 0.02 94.76 0.00 93.41 0.14 94.21 0.00 95.17 0.00 97.41 0.00 98.31 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_0.2880761077
95.57 0.02 94.77 0.01 93.43 0.01 94.31 0.10 95.18 0.01 97.41 0.00 98.32 0.01 /workspace/coverage/default/85.chip_sw_all_escalation_resets.2733147602
95.59 0.02 94.78 0.01 93.47 0.05 94.35 0.04 95.20 0.02 97.41 0.00 98.32 0.00 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2743334518
95.61 0.02 94.81 0.03 93.53 0.05 94.36 0.01 95.23 0.02 97.41 0.00 98.32 0.00 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1016452875
95.63 0.02 94.84 0.03 93.57 0.04 94.38 0.02 95.25 0.02 97.41 0.00 98.32 0.00 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.700826500
95.65 0.02 94.89 0.05 93.62 0.05 94.38 0.00 95.27 0.02 97.41 0.00 98.32 0.00 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.1579200211
95.67 0.02 94.93 0.03 93.62 0.00 94.47 0.08 95.27 0.00 97.41 0.00 98.32 0.00 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2471160227
95.69 0.02 94.93 0.00 93.71 0.09 94.47 0.00 95.27 0.00 97.41 0.00 98.33 0.01 /workspace/coverage/cover_reg_top/22.chip_tl_errors.406461463
95.70 0.02 94.93 0.00 93.71 0.00 94.57 0.10 95.27 0.00 97.41 0.00 98.33 0.00 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3618778699
95.72 0.02 94.93 0.00 93.72 0.01 94.57 0.00 95.27 0.00 97.41 0.00 98.43 0.09 /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.564289066
95.74 0.01 94.93 0.00 93.73 0.01 94.57 0.00 95.27 0.00 97.41 0.00 98.50 0.07 /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.3062381982
95.75 0.01 94.93 0.00 93.76 0.02 94.57 0.00 95.27 0.00 97.41 0.00 98.55 0.06 /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3012136838
95.76 0.01 94.93 0.00 93.84 0.08 94.57 0.00 95.27 0.00 97.41 0.00 98.55 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_0.2916567441
95.78 0.01 94.93 0.00 93.84 0.01 94.65 0.08 95.27 0.00 97.41 0.00 98.55 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1356308975
95.79 0.01 94.93 0.00 93.86 0.02 94.65 0.00 95.27 0.00 97.41 0.00 98.61 0.06 /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.778866754
95.80 0.01 94.93 0.00 93.86 0.00 94.72 0.08 95.27 0.00 97.41 0.00 98.61 0.00 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2532594497
95.81 0.01 94.93 0.00 93.92 0.06 94.72 0.00 95.29 0.02 97.41 0.00 98.61 0.00 /workspace/coverage/cover_reg_top/0.xbar_stress_all.3485263321
95.82 0.01 94.93 0.00 93.92 0.00 94.79 0.07 95.29 0.00 97.41 0.00 98.61 0.00 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3481541755
95.84 0.01 94.93 0.00 93.92 0.01 94.79 0.00 95.29 0.00 97.41 0.00 98.67 0.06 /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.1538951864
95.85 0.01 94.93 0.00 93.92 0.00 94.85 0.06 95.29 0.00 97.41 0.00 98.67 0.00 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2876572712
95.85 0.01 94.95 0.03 93.93 0.01 94.85 0.00 95.30 0.02 97.41 0.00 98.67 0.00 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.894491461
95.86 0.01 94.98 0.03 93.95 0.01 94.85 0.00 95.32 0.02 97.41 0.00 98.67 0.00 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2604335279
95.87 0.01 95.00 0.03 93.96 0.01 94.85 0.00 95.34 0.02 97.41 0.00 98.67 0.00 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1948605988
95.88 0.01 95.01 0.01 94.00 0.03 94.87 0.02 95.34 0.00 97.41 0.00 98.67 0.00 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.81568994
95.89 0.01 95.01 0.00 94.00 0.01 94.87 0.00 95.34 0.00 97.41 0.00 98.72 0.05 /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.3900661834
95.90 0.01 95.01 0.00 94.05 0.05 94.87 0.00 95.34 0.00 97.41 0.00 98.72 0.00 /workspace/coverage/cover_reg_top/5.chip_tl_errors.4034168902
95.91 0.01 95.02 0.01 94.05 0.00 94.91 0.03 95.34 0.00 97.41 0.00 98.72 0.00 /workspace/coverage/default/0.chip_sw_power_idle_load.2330747082
95.92 0.01 95.02 0.00 94.10 0.05 94.91 0.00 95.34 0.00 97.41 0.00 98.72 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_20.3657906232
95.92 0.01 95.02 0.00 94.14 0.04 94.91 0.00 95.34 0.00 97.41 0.00 98.72 0.00 /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.1386774633
95.93 0.01 95.02 0.00 94.18 0.04 94.91 0.00 95.34 0.00 97.41 0.00 98.72 0.00 /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.3629820573
95.94 0.01 95.02 0.00 94.22 0.04 94.91 0.00 95.34 0.00 97.41 0.00 98.72 0.00 /workspace/coverage/cover_reg_top/35.xbar_access_same_device.136160882
95.94 0.01 95.02 0.00 94.22 0.00 94.93 0.02 95.34 0.00 97.41 0.00 98.73 0.01 /workspace/coverage/default/99.chip_sw_all_escalation_resets.1369781380
95.95 0.01 95.02 0.01 94.25 0.03 94.93 0.00 95.34 0.00 97.41 0.00 98.73 0.00 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.517735323
95.95 0.01 95.02 0.00 94.25 0.00 94.96 0.03 95.34 0.00 97.41 0.00 98.73 0.00 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2409507522
95.96 0.01 95.02 0.00 94.26 0.01 94.96 0.00 95.34 0.00 97.41 0.00 98.75 0.02 /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.358437442
95.96 0.01 95.02 0.00 94.29 0.03 94.96 0.00 95.34 0.00 97.41 0.00 98.75 0.00 /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.2133812615
95.97 0.01 95.02 0.00 94.32 0.03 94.96 0.00 95.34 0.00 97.41 0.00 98.75 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_10.1056422208
95.97 0.01 95.02 0.00 94.34 0.03 94.96 0.00 95.34 0.00 97.41 0.00 98.75 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_20.2702182375
95.98 0.01 95.03 0.01 94.34 0.00 94.99 0.02 95.34 0.00 97.41 0.00 98.75 0.00 /workspace/coverage/default/0.chip_sw_usbdev_config_host.2256210587
95.98 0.01 95.03 0.00 94.34 0.00 94.99 0.00 95.34 0.00 97.41 0.00 98.78 0.02 /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.292873988
95.98 0.01 95.03 0.00 94.34 0.00 95.01 0.02 95.34 0.00 97.41 0.00 98.78 0.00 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.2652552222
95.99 0.01 95.03 0.00 94.34 0.00 95.02 0.01 95.34 0.00 97.41 0.00 98.79 0.01 /workspace/coverage/default/9.chip_sw_all_escalation_resets.690471657
95.99 0.01 95.03 0.00 94.35 0.01 95.03 0.01 95.34 0.00 97.41 0.00 98.79 0.00 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.2369500747
95.99 0.01 95.03 0.00 94.36 0.01 95.03 0.00 95.34 0.00 97.41 0.00 98.80 0.01 /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.2058619589
96.00 0.01 95.03 0.00 94.36 0.00 95.04 0.02 95.34 0.00 97.41 0.00 98.80 0.00 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3525038286
96.00 0.01 95.03 0.00 94.38 0.02 95.04 0.00 95.34 0.00 97.41 0.00 98.80 0.00 /workspace/coverage/cover_reg_top/16.chip_tl_errors.412161626
96.00 0.01 95.03 0.00 94.40 0.02 95.04 0.00 95.34 0.00 97.41 0.00 98.80 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_10.3911132299
96.01 0.01 95.03 0.01 94.40 0.00 95.06 0.01 95.34 0.00 97.41 0.00 98.80 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1813142544
96.01 0.01 95.05 0.01 94.40 0.00 95.06 0.01 95.34 0.00 97.41 0.00 98.80 0.00 /workspace/coverage/default/0.chip_sw_plic_sw_irq.2522305193
96.01 0.01 95.06 0.01 94.40 0.00 95.06 0.01 95.34 0.00 97.41 0.00 98.80 0.00 /workspace/coverage/default/1.chip_sw_pattgen_ios.1902904267
96.01 0.01 95.06 0.00 94.40 0.01 95.06 0.00 95.34 0.00 97.41 0.00 98.81 0.01 /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.2905609736
96.02 0.01 95.06 0.00 94.41 0.01 95.06 0.00 95.34 0.00 97.41 0.00 98.81 0.00 /workspace/coverage/cover_reg_top/81.xbar_stress_all.1594847705
96.02 0.01 95.06 0.00 94.43 0.01 95.06 0.00 95.34 0.00 97.41 0.00 98.81 0.00 /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.2339006918
96.02 0.01 95.06 0.00 94.44 0.01 95.06 0.00 95.34 0.00 97.41 0.00 98.81 0.00 /workspace/coverage/default/0.chip_sw_gpio.730981513
96.02 0.01 95.06 0.00 94.44 0.00 95.08 0.01 95.34 0.00 97.41 0.00 98.81 0.00 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.997286215
96.03 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 98.82 0.01 /workspace/coverage/cover_reg_top/15.chip_tl_errors.208335677
96.03 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 98.84 0.01 /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.3793727087
96.03 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 98.85 0.01 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1856591733
96.03 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 98.86 0.01 /workspace/coverage/default/0.chip_sw_all_escalation_resets.2229660284
96.03 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 98.87 0.01 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2124605833
96.04 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 98.88 0.01 /workspace/coverage/default/1.chip_sw_all_escalation_resets.2449504003
96.04 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 98.90 0.01 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3461288869
96.04 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 98.91 0.01 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.205009710
96.04 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 98.92 0.01 /workspace/coverage/default/11.chip_sw_all_escalation_resets.3074053022
96.04 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 98.93 0.01 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1073871667
96.05 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 98.94 0.01 /workspace/coverage/default/12.chip_sw_all_escalation_resets.3300954415
96.05 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 98.95 0.01 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3443754793
96.05 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 98.97 0.01 /workspace/coverage/default/14.chip_sw_all_escalation_resets.2305997539
96.05 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 98.98 0.01 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1865131926
96.05 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 98.99 0.01 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1891149374
96.05 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.00 0.01 /workspace/coverage/default/16.chip_sw_all_escalation_resets.2024884606
96.06 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.01 0.01 /workspace/coverage/default/18.chip_sw_all_escalation_resets.3770072673
96.06 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.02 0.01 /workspace/coverage/default/19.chip_sw_all_escalation_resets.2657494106
96.06 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.04 0.01 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2052915192
96.06 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.05 0.01 /workspace/coverage/default/2.chip_sw_all_escalation_resets.3777838434
96.06 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.06 0.01 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1202023981
96.07 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.07 0.01 /workspace/coverage/default/20.chip_sw_all_escalation_resets.2681884676
96.07 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.08 0.01 /workspace/coverage/default/21.chip_sw_all_escalation_resets.182508589
96.07 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.10 0.01 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3633987551
96.07 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.11 0.01 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1476145862
96.07 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.12 0.01 /workspace/coverage/default/23.chip_sw_all_escalation_resets.2801060334
96.08 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.13 0.01 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.363840989
96.08 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.14 0.01 /workspace/coverage/default/24.chip_sw_all_escalation_resets.3410784456
96.08 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.15 0.01 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.4073120307
96.08 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.17 0.01 /workspace/coverage/default/25.chip_sw_all_escalation_resets.1363446661
96.08 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.18 0.01 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.878609583
96.09 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.19 0.01 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.244482166
96.09 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.20 0.01 /workspace/coverage/default/3.chip_sw_all_escalation_resets.1381140788
96.09 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.21 0.01 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2747995497
96.09 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.22 0.01 /workspace/coverage/default/30.chip_sw_all_escalation_resets.706263329
96.09 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.24 0.01 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1302309697
96.10 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.25 0.01 /workspace/coverage/default/34.chip_sw_all_escalation_resets.1250269826
96.10 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.26 0.01 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2692473906
96.10 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.27 0.01 /workspace/coverage/default/35.chip_sw_all_escalation_resets.3856579802
96.10 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.28 0.01 /workspace/coverage/default/39.chip_sw_all_escalation_resets.2644083175
96.10 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.29 0.01 /workspace/coverage/default/4.chip_sw_all_escalation_resets.2408534510
96.11 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.31 0.01 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1642784876
96.11 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.32 0.01 /workspace/coverage/default/40.chip_sw_all_escalation_resets.127052178
96.11 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.33 0.01 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3870581550
96.11 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.34 0.01 /workspace/coverage/default/45.chip_sw_all_escalation_resets.4122532884
96.11 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.35 0.01 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3739710021
96.12 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.37 0.01 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2921128912
96.12 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.38 0.01 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2483911459
96.12 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.39 0.01 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.1347666263
96.12 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.40 0.01 /workspace/coverage/default/61.chip_sw_all_escalation_resets.797114073
96.12 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.41 0.01 /workspace/coverage/default/69.chip_sw_all_escalation_resets.4168029861
96.13 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.42 0.01 /workspace/coverage/default/7.chip_sw_all_escalation_resets.1202847756
96.13 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.44 0.01 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1773069891
96.13 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.45 0.01 /workspace/coverage/default/77.chip_sw_all_escalation_resets.479651771
96.13 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.46 0.01 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2288903266
96.13 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.47 0.01 /workspace/coverage/default/82.chip_sw_all_escalation_resets.1084579764
96.14 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.48 0.01 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3238850314
96.14 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.49 0.01 /workspace/coverage/default/87.chip_sw_all_escalation_resets.2506396418
96.14 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.51 0.01 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1426612164
96.14 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.52 0.01 /workspace/coverage/default/89.chip_sw_all_escalation_resets.3185023840
96.14 0.01 95.06 0.00 94.44 0.00 95.08 0.00 95.34 0.00 97.41 0.00 99.53 0.01 /workspace/coverage/default/94.chip_sw_all_escalation_resets.3914287759
96.14 0.01 95.06 0.00 94.45 0.01 95.08 0.00 95.34 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/cover_reg_top/28.chip_tl_errors.2496044337
96.15 0.01 95.06 0.00 94.46 0.01 95.08 0.00 95.34 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4251011563
96.15 0.01 95.06 0.01 94.46 0.00 95.08 0.01 95.34 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/default/74.chip_sw_all_escalation_resets.1846586308
96.15 0.01 95.06 0.00 94.46 0.00 95.09 0.01 95.34 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/default/0.chip_sw_flash_init.4246539257
96.15 0.01 95.06 0.00 94.46 0.00 95.10 0.01 95.34 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2496984540
96.15 0.01 95.06 0.00 94.46 0.00 95.11 0.01 95.34 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.389501529
96.15 0.01 95.06 0.00 94.46 0.00 95.12 0.01 95.34 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.3078271361
96.16 0.01 95.06 0.00 94.46 0.00 95.12 0.00 95.34 0.01 97.41 0.00 99.53 0.00 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3396672400
96.16 0.01 95.06 0.00 94.46 0.00 95.12 0.00 95.35 0.01 97.41 0.00 99.53 0.00 /workspace/coverage/default/0.chip_tap_straps_dev.2517293095
96.16 0.01 95.06 0.00 94.47 0.01 95.12 0.00 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.2733451948
96.16 0.01 95.06 0.00 94.48 0.01 95.12 0.00 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/default/1.chip_sival_flash_info_access.3584707732
96.16 0.01 95.06 0.00 94.49 0.01 95.12 0.00 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/default/1.chip_sw_gpio.1702041744
96.16 0.01 95.07 0.01 94.49 0.01 95.12 0.00 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/cover_reg_top/12.chip_csr_rw.908082150
96.16 0.01 95.07 0.01 94.49 0.01 95.12 0.00 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1679028834
96.16 0.01 95.08 0.01 94.50 0.01 95.12 0.00 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1026127147
96.17 0.01 95.08 0.00 94.50 0.00 95.13 0.01 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/default/0.chip_sw_edn_boot_mode.944426841
96.17 0.01 95.08 0.00 94.50 0.00 95.13 0.01 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.353927325
96.17 0.01 95.08 0.00 94.50 0.00 95.14 0.01 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.57220504
96.17 0.01 95.08 0.00 94.50 0.00 95.14 0.01 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1940018639
96.17 0.01 95.08 0.00 94.50 0.01 95.14 0.00 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.356235251
96.17 0.01 95.08 0.00 94.50 0.01 95.14 0.00 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/cover_reg_top/14.chip_tl_errors.2985512012
96.17 0.01 95.08 0.00 94.51 0.01 95.14 0.00 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.1856905382
96.17 0.01 95.08 0.00 94.51 0.01 95.14 0.00 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.2089884330
96.17 0.01 95.08 0.00 94.52 0.01 95.14 0.00 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.3349424478
96.17 0.01 95.08 0.00 94.52 0.01 95.14 0.00 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.2048642736
96.17 0.01 95.08 0.00 94.52 0.01 95.14 0.00 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3781169318
96.17 0.01 95.08 0.00 94.53 0.01 95.14 0.00 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2239854364
96.17 0.01 95.08 0.00 94.53 0.01 95.14 0.00 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1458021150
96.17 0.01 95.08 0.01 94.53 0.00 95.14 0.00 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1487389316
96.18 0.01 95.08 0.01 94.53 0.00 95.14 0.00 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2448000000
96.18 0.01 95.08 0.00 94.53 0.00 95.15 0.01 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.460247163
96.18 0.01 95.08 0.00 94.53 0.00 95.15 0.01 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3334104723
96.18 0.01 95.08 0.00 94.53 0.00 95.15 0.01 95.35 0.00 97.41 0.00 99.53 0.00 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3261919638


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.2322730932
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3106346156
/workspace/coverage/cover_reg_top/0.chip_csr_rw.2229483646
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.111847660
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3482080631
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.467053124
/workspace/coverage/cover_reg_top/0.chip_tl_errors.604213329
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2358601094
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2466375628
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.75280781
/workspace/coverage/cover_reg_top/0.xbar_error_random.316614228
/workspace/coverage/cover_reg_top/0.xbar_random.797051650
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.815959203
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/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1170271505
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2233535935
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1242510117
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1525136988
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2693952814




Total test records in report: 2844
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/0.chip_sw_example_flash.2644551268 Mar 07 03:37:07 PM PST 24 Mar 07 03:42:07 PM PST 24 2925865596 ps
T2 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2193127119 Mar 07 03:58:02 PM PST 24 Mar 07 04:32:00 PM PST 24 21850322855 ps
T3 /workspace/coverage/default/54.chip_sw_all_escalation_resets.1823173782 Mar 07 04:06:53 PM PST 24 Mar 07 04:15:52 PM PST 24 5042795020 ps
T39 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3099148098 Mar 07 03:42:34 PM PST 24 Mar 07 04:15:34 PM PST 24 8522699330 ps
T51 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.245087923 Mar 07 04:08:45 PM PST 24 Mar 07 04:14:20 PM PST 24 3194385976 ps
T52 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3587812124 Mar 07 04:05:26 PM PST 24 Mar 07 04:12:25 PM PST 24 3608137800 ps
T85 /workspace/coverage/default/2.chip_sw_aes_entropy.3392490290 Mar 07 03:55:14 PM PST 24 Mar 07 03:59:30 PM PST 24 2843818998 ps
T86 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.2652552222 Mar 07 03:46:39 PM PST 24 Mar 07 03:53:07 PM PST 24 3674085083 ps
T4 /workspace/coverage/default/1.rom_raw_unlock.375408544 Mar 07 03:51:37 PM PST 24 Mar 07 04:25:35 PM PST 24 14886042162 ps
T40 /workspace/coverage/default/1.chip_sw_uart_smoketest_signed.2621523406 Mar 07 03:54:46 PM PST 24 Mar 07 04:29:51 PM PST 24 9440400600 ps
T41 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2112644287 Mar 07 03:41:48 PM PST 24 Mar 07 04:17:21 PM PST 24 9077445336 ps
T29 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2401911575 Mar 07 03:37:42 PM PST 24 Mar 07 03:43:51 PM PST 24 4551525480 ps
T65 /workspace/coverage/default/67.chip_sw_all_escalation_resets.398045334 Mar 07 04:07:47 PM PST 24 Mar 07 04:16:47 PM PST 24 4649649902 ps
T166 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1021646757 Mar 07 03:45:31 PM PST 24 Mar 07 03:50:20 PM PST 24 3105035567 ps
T366 /workspace/coverage/default/2.chip_sw_aes_idle.2098559009 Mar 07 03:57:41 PM PST 24 Mar 07 04:02:01 PM PST 24 2565504670 ps
T66 /workspace/coverage/default/85.chip_sw_all_escalation_resets.2733147602 Mar 07 04:09:51 PM PST 24 Mar 07 04:21:27 PM PST 24 5220598616 ps
T131 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2203591948 Mar 07 03:38:18 PM PST 24 Mar 07 03:45:41 PM PST 24 3930852708 ps
T109 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.829061340 Mar 07 03:45:57 PM PST 24 Mar 07 04:04:53 PM PST 24 5138619456 ps
T144 /workspace/coverage/default/74.chip_sw_all_escalation_resets.1846586308 Mar 07 04:07:45 PM PST 24 Mar 07 04:20:07 PM PST 24 6271716480 ps
T5 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2881279965 Mar 07 03:56:39 PM PST 24 Mar 07 04:04:27 PM PST 24 9297235430 ps
T36 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1088397024 Mar 07 03:44:29 PM PST 24 Mar 07 04:12:21 PM PST 24 6990933554 ps
T177 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1356308975 Mar 07 03:41:18 PM PST 24 Mar 07 03:46:59 PM PST 24 3434843602 ps
T12 /workspace/coverage/default/2.chip_sw_gpio.1927738968 Mar 07 03:52:03 PM PST 24 Mar 07 03:59:37 PM PST 24 3828756366 ps
T191 /workspace/coverage/default/3.chip_sw_uart_tx_rx.4089661561 Mar 07 04:00:50 PM PST 24 Mar 07 04:16:59 PM PST 24 4872188072 ps
T134 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.50639325 Mar 07 03:42:52 PM PST 24 Mar 07 04:09:49 PM PST 24 9266353632 ps
T282 /workspace/coverage/default/99.chip_sw_all_escalation_resets.1369781380 Mar 07 04:11:26 PM PST 24 Mar 07 04:22:37 PM PST 24 5589803882 ps
T104 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.504699898 Mar 07 03:39:19 PM PST 24 Mar 07 04:42:34 PM PST 24 17235680164 ps
T333 /workspace/coverage/default/9.chip_sw_all_escalation_resets.690471657 Mar 07 04:02:47 PM PST 24 Mar 07 04:13:57 PM PST 24 5629752296 ps
T181 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2188215510 Mar 07 04:04:32 PM PST 24 Mar 07 04:11:14 PM PST 24 3183506616 ps
T123 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2356560561 Mar 07 03:47:42 PM PST 24 Mar 07 03:55:13 PM PST 24 4690808440 ps
T335 /workspace/coverage/default/23.chip_sw_all_escalation_resets.2801060334 Mar 07 04:04:33 PM PST 24 Mar 07 04:16:31 PM PST 24 5631042328 ps
T151 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.670331651 Mar 07 03:41:01 PM PST 24 Mar 07 04:12:54 PM PST 24 13869827211 ps
T855 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3142269619 Mar 07 03:39:20 PM PST 24 Mar 07 03:42:28 PM PST 24 2758162132 ps
T330 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3464689630 Mar 07 03:42:30 PM PST 24 Mar 07 03:51:13 PM PST 24 5749432600 ps
T351 /workspace/coverage/default/42.chip_sw_all_escalation_resets.2500750844 Mar 07 04:04:33 PM PST 24 Mar 07 04:12:26 PM PST 24 5719635844 ps
T178 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.700826500 Mar 07 04:00:37 PM PST 24 Mar 07 04:14:35 PM PST 24 5432465880 ps
T856 /workspace/coverage/default/1.chip_sw_aes_idle.2266262365 Mar 07 03:43:34 PM PST 24 Mar 07 03:47:26 PM PST 24 3009552848 ps
T115 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.4073120307 Mar 07 04:04:32 PM PST 24 Mar 07 04:11:44 PM PST 24 3785321770 ps
T245 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.2810584422 Mar 07 04:00:43 PM PST 24 Mar 07 04:04:41 PM PST 24 3403212556 ps
T677 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2851960603 Mar 07 04:05:56 PM PST 24 Mar 07 04:12:45 PM PST 24 4312350200 ps
T198 /workspace/coverage/default/65.chip_sw_all_escalation_resets.3915344882 Mar 07 04:07:49 PM PST 24 Mar 07 04:17:25 PM PST 24 5533102954 ps
T666 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1345604469 Mar 07 04:04:27 PM PST 24 Mar 07 04:11:12 PM PST 24 3523549418 ps
T703 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1656845615 Mar 07 03:37:29 PM PST 24 Mar 07 03:48:09 PM PST 24 4702209160 ps
T411 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.493575513 Mar 07 04:00:53 PM PST 24 Mar 07 04:05:17 PM PST 24 3461853954 ps
T154 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2743334518 Mar 07 03:56:43 PM PST 24 Mar 07 04:18:03 PM PST 24 5887439576 ps
T124 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1813142544 Mar 07 03:44:54 PM PST 24 Mar 07 04:23:07 PM PST 24 21385715583 ps
T336 /workspace/coverage/default/86.chip_sw_all_escalation_resets.2670500004 Mar 07 04:08:35 PM PST 24 Mar 07 04:18:03 PM PST 24 5252660908 ps
T334 /workspace/coverage/default/14.chip_sw_all_escalation_resets.2305997539 Mar 07 04:03:23 PM PST 24 Mar 07 04:14:31 PM PST 24 5157023080 ps
T64 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4138029997 Mar 07 03:40:02 PM PST 24 Mar 07 03:41:40 PM PST 24 2115784626 ps
T187 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.598243880 Mar 07 04:03:07 PM PST 24 Mar 07 04:38:30 PM PST 24 13427738316 ps
T30 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.804553676 Mar 07 03:39:33 PM PST 24 Mar 07 03:44:06 PM PST 24 3125509624 ps
T70 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1176203419 Mar 07 04:01:26 PM PST 24 Mar 07 04:10:15 PM PST 24 4141449300 ps
T139 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.293220030 Mar 07 03:45:33 PM PST 24 Mar 07 03:56:16 PM PST 24 4219989217 ps
T761 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2124605833 Mar 07 03:43:17 PM PST 24 Mar 07 03:48:34 PM PST 24 3560170908 ps
T419 /workspace/coverage/default/1.chip_sw_kmac_idle.1247485292 Mar 07 03:45:50 PM PST 24 Mar 07 03:48:55 PM PST 24 2614287530 ps
T155 /workspace/coverage/default/2.chip_sw_edn_boot_mode.1926848734 Mar 07 03:54:53 PM PST 24 Mar 07 04:04:39 PM PST 24 2941373352 ps
T184 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3346942555 Mar 07 03:42:22 PM PST 24 Mar 07 03:53:36 PM PST 24 4921153568 ps
T135 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2858382149 Mar 07 03:57:24 PM PST 24 Mar 07 05:13:27 PM PST 24 18112818868 ps
T232 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3267652006 Mar 07 03:41:30 PM PST 24 Mar 07 03:50:52 PM PST 24 3295209706 ps
T731 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1177518312 Mar 07 04:04:12 PM PST 24 Mar 07 04:11:49 PM PST 24 4343729400 ps
T188 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.81568994 Mar 07 03:38:52 PM PST 24 Mar 07 03:52:34 PM PST 24 4130728356 ps
T125 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1762723007 Mar 07 03:40:37 PM PST 24 Mar 07 03:48:33 PM PST 24 5935928952 ps
T418 /workspace/coverage/default/69.chip_sw_all_escalation_resets.4168029861 Mar 07 04:07:47 PM PST 24 Mar 07 04:18:15 PM PST 24 5229764360 ps
T299 /workspace/coverage/default/0.chip_plic_all_irqs_20.1816256112 Mar 07 03:37:23 PM PST 24 Mar 07 03:49:35 PM PST 24 5037940830 ps
T247 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.44766911 Mar 07 03:59:04 PM PST 24 Mar 07 04:04:22 PM PST 24 3103127006 ps
T248 /workspace/coverage/default/2.chip_sw_aon_timer_irq.2642195586 Mar 07 03:54:18 PM PST 24 Mar 07 04:01:04 PM PST 24 3570503976 ps
T67 /workspace/coverage/default/4.chip_tap_straps_rma.2052087133 Mar 07 04:01:16 PM PST 24 Mar 07 04:04:12 PM PST 24 2789076067 ps
T857 /workspace/coverage/default/1.chip_sw_aes_entropy.1171001858 Mar 07 03:41:38 PM PST 24 Mar 07 03:44:59 PM PST 24 2506339806 ps
T175 /workspace/coverage/default/0.chip_tap_straps_prod.2042409896 Mar 07 03:38:54 PM PST 24 Mar 07 03:41:42 PM PST 24 3187108506 ps
T669 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1513760998 Mar 07 04:05:25 PM PST 24 Mar 07 04:13:07 PM PST 24 3584322736 ps
T858 /workspace/coverage/default/1.chip_sw_example_concurrency.2021674149 Mar 07 03:38:22 PM PST 24 Mar 07 03:41:40 PM PST 24 2660282156 ps
T859 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2234063681 Mar 07 03:38:24 PM PST 24 Mar 07 03:47:42 PM PST 24 6234626932 ps
T19 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1256105049 Mar 07 03:40:53 PM PST 24 Mar 07 04:46:13 PM PST 24 20670139885 ps
T42 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.2851612660 Mar 07 03:39:02 PM PST 24 Mar 07 03:46:26 PM PST 24 5039500744 ps
T37 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.4151182996 Mar 07 03:45:01 PM PST 24 Mar 07 04:38:10 PM PST 24 11497679598 ps
T99 /workspace/coverage/default/3.chip_sw_all_escalation_resets.1381140788 Mar 07 04:00:04 PM PST 24 Mar 07 04:10:56 PM PST 24 4858366000 ps
T31 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.4092821714 Mar 07 03:51:44 PM PST 24 Mar 07 03:58:05 PM PST 24 3182289768 ps
T13 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1094974979 Mar 07 04:02:18 PM PST 24 Mar 07 04:15:13 PM PST 24 4633704874 ps
T100 /workspace/coverage/default/0.chip_sw_rv_timer_irq.1547680189 Mar 07 03:37:16 PM PST 24 Mar 07 03:42:28 PM PST 24 3400981508 ps
T101 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3238850314 Mar 07 04:08:17 PM PST 24 Mar 07 04:16:50 PM PST 24 3921877088 ps
T102 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3870581550 Mar 07 04:06:53 PM PST 24 Mar 07 04:13:33 PM PST 24 3622297062 ps
T103 /workspace/coverage/default/93.chip_sw_all_escalation_resets.2237031177 Mar 07 04:11:13 PM PST 24 Mar 07 04:19:41 PM PST 24 4914952038 ps
T62 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.600722504 Mar 07 03:42:04 PM PST 24 Mar 07 04:20:13 PM PST 24 33587527520 ps
T71 /workspace/coverage/default/0.chip_jtag_mem_access.1979391944 Mar 07 03:29:29 PM PST 24 Mar 07 03:54:14 PM PST 24 13377344760 ps
T250 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2675997619 Mar 07 03:54:29 PM PST 24 Mar 07 04:11:43 PM PST 24 5785955064 ps
T417 /workspace/coverage/default/1.chip_sw_flash_crash_alert.1107367757 Mar 07 03:51:05 PM PST 24 Mar 07 04:04:10 PM PST 24 5631124276 ps
T353 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2908980784 Mar 07 03:43:31 PM PST 24 Mar 07 04:30:42 PM PST 24 26820729768 ps
T220 /workspace/coverage/default/0.rom_keymgr_functest.274479520 Mar 07 03:38:42 PM PST 24 Mar 07 03:48:29 PM PST 24 3856757700 ps
T860 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.476955654 Mar 07 03:38:03 PM PST 24 Mar 07 03:41:01 PM PST 24 2941407584 ps
T132 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1547517210 Mar 07 03:37:27 PM PST 24 Mar 07 03:44:16 PM PST 24 5023064156 ps
T674 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3164078428 Mar 07 03:38:20 PM PST 24 Mar 07 03:49:10 PM PST 24 4509171488 ps
T201 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1175005219 Mar 07 03:41:08 PM PST 24 Mar 07 04:10:02 PM PST 24 6638078080 ps
T176 /workspace/coverage/default/4.chip_tap_straps_dev.2897120838 Mar 07 04:00:00 PM PST 24 Mar 07 04:05:30 PM PST 24 3858921720 ps
T63 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3481541755 Mar 07 03:40:24 PM PST 24 Mar 07 04:00:12 PM PST 24 13746576508 ps
T38 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1025442717 Mar 07 03:41:26 PM PST 24 Mar 07 04:13:55 PM PST 24 8814601836 ps
T861 /workspace/coverage/default/2.chip_sw_csrng_smoketest.3030139401 Mar 07 04:00:39 PM PST 24 Mar 07 04:05:36 PM PST 24 3508696496 ps
T260 /workspace/coverage/default/1.rom_volatile_raw_unlock.4012651567 Mar 07 03:51:03 PM PST 24 Mar 07 03:52:59 PM PST 24 1795294232 ps
T133 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.427316167 Mar 07 03:53:55 PM PST 24 Mar 07 05:25:04 PM PST 24 51337157112 ps
T862 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2893162769 Mar 07 04:03:49 PM PST 24 Mar 07 04:35:48 PM PST 24 8981765859 ps
T693 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.4225798359 Mar 07 03:43:10 PM PST 24 Mar 07 03:55:55 PM PST 24 5073630288 ps
T420 /workspace/coverage/default/2.chip_sw_kmac_entropy.3686708157 Mar 07 03:57:27 PM PST 24 Mar 07 04:02:43 PM PST 24 2794792968 ps
T300 /workspace/coverage/default/1.chip_plic_all_irqs_20.3657906232 Mar 07 03:46:01 PM PST 24 Mar 07 03:59:38 PM PST 24 5178647898 ps
T73 /workspace/coverage/default/0.chip_tap_straps_dev.2517293095 Mar 07 03:35:48 PM PST 24 Mar 07 04:08:18 PM PST 24 16067061555 ps
T863 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.798385147 Mar 07 03:47:03 PM PST 24 Mar 07 03:54:36 PM PST 24 3868435656 ps
T864 /workspace/coverage/default/0.rom_e2e_asm_init_prod.3011209644 Mar 07 03:44:12 PM PST 24 Mar 07 04:20:23 PM PST 24 8855316924 ps
T364 /workspace/coverage/default/45.chip_sw_all_escalation_resets.4122532884 Mar 07 04:07:01 PM PST 24 Mar 07 04:17:12 PM PST 24 5772028262 ps
T43 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.1579200211 Mar 07 03:51:49 PM PST 24 Mar 07 03:55:26 PM PST 24 2631607070 ps
T152 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1118231799 Mar 07 03:57:47 PM PST 24 Mar 07 04:09:49 PM PST 24 4305503656 ps
T403 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1106077825 Mar 07 04:07:45 PM PST 24 Mar 07 04:15:10 PM PST 24 3821346168 ps
T116 /workspace/coverage/default/46.chip_sw_all_escalation_resets.3210800951 Mar 07 04:05:46 PM PST 24 Mar 07 04:16:50 PM PST 24 4912736080 ps
T68 /workspace/coverage/default/1.chip_tap_straps_testunlock0.3443873544 Mar 07 03:47:34 PM PST 24 Mar 07 03:57:51 PM PST 24 6797539244 ps
T404 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2616778501 Mar 07 03:56:07 PM PST 24 Mar 07 04:03:54 PM PST 24 7519785336 ps
T208 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.203219524 Mar 07 03:46:24 PM PST 24 Mar 07 03:56:52 PM PST 24 4921102012 ps
T405 /workspace/coverage/default/0.chip_sw_example_rom.665538986 Mar 07 03:36:30 PM PST 24 Mar 07 03:38:17 PM PST 24 1955163064 ps
T406 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.601696454 Mar 07 04:03:01 PM PST 24 Mar 07 05:09:46 PM PST 24 23092136828 ps
T136 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.826125578 Mar 07 03:36:52 PM PST 24 Mar 07 03:39:08 PM PST 24 2663484048 ps
T205 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3441741580 Mar 07 04:06:29 PM PST 24 Mar 07 04:12:36 PM PST 24 2924227976 ps
T676 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2288903266 Mar 07 04:08:48 PM PST 24 Mar 07 04:15:12 PM PST 24 3374049540 ps
T865 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2239740631 Mar 07 03:38:04 PM PST 24 Mar 07 03:45:42 PM PST 24 4185019144 ps
T317 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3240395786 Mar 07 03:53:53 PM PST 24 Mar 07 04:03:19 PM PST 24 4430488820 ps
T866 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3883847767 Mar 07 03:37:07 PM PST 24 Mar 07 03:45:10 PM PST 24 4703729928 ps
T105 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.997286215 Mar 07 03:58:08 PM PST 24 Mar 07 04:56:35 PM PST 24 24945258508 ps
T867 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3371366837 Mar 07 04:01:12 PM PST 24 Mar 07 04:04:38 PM PST 24 2472535632 ps
T129 /workspace/coverage/default/43.chip_sw_all_escalation_resets.671248296 Mar 07 04:05:51 PM PST 24 Mar 07 04:15:12 PM PST 24 4937983000 ps
T762 /workspace/coverage/default/51.chip_sw_all_escalation_resets.1796010293 Mar 07 04:05:53 PM PST 24 Mar 07 04:16:57 PM PST 24 4590290780 ps
T153 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2409507522 Mar 07 03:40:50 PM PST 24 Mar 07 03:54:07 PM PST 24 4522805750 ps
T179 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1406191560 Mar 07 04:02:24 PM PST 24 Mar 07 04:16:11 PM PST 24 5112678676 ps
T341 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3152916803 Mar 07 03:44:45 PM PST 24 Mar 07 03:49:30 PM PST 24 2939156480 ps
T868 /workspace/coverage/default/1.chip_sw_aon_timer_irq.992294313 Mar 07 03:39:44 PM PST 24 Mar 07 03:45:32 PM PST 24 3489695828 ps
T72 /workspace/coverage/default/1.chip_tap_straps_rma.999820995 Mar 07 03:50:18 PM PST 24 Mar 07 03:54:39 PM PST 24 3079460116 ps
T869 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1310125156 Mar 07 03:40:23 PM PST 24 Mar 07 03:49:19 PM PST 24 2853093408 ps
T342 /workspace/coverage/default/1.chip_sw_hmac_enc.3090995774 Mar 07 03:45:06 PM PST 24 Mar 07 03:51:08 PM PST 24 2805472520 ps
T386 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2640048058 Mar 07 03:37:23 PM PST 24 Mar 07 03:58:56 PM PST 24 9796277612 ps
T203 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2282561008 Mar 07 03:54:02 PM PST 24 Mar 07 05:20:54 PM PST 24 51356318920 ps
T870 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3243404455 Mar 07 03:41:45 PM PST 24 Mar 07 03:48:25 PM PST 24 5887061127 ps
T158 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.218058210 Mar 07 03:56:56 PM PST 24 Mar 07 04:03:39 PM PST 24 4736121782 ps
T407 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1897804350 Mar 07 04:03:12 PM PST 24 Mar 07 04:06:30 PM PST 24 2232463592 ps
T190 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3707127705 Mar 07 03:52:01 PM PST 24 Mar 07 04:15:04 PM PST 24 8697051160 ps
T730 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2905541873 Mar 07 04:08:37 PM PST 24 Mar 07 04:13:06 PM PST 24 3478236552 ps
T231 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1694563911 Mar 07 03:52:21 PM PST 24 Mar 07 04:17:51 PM PST 24 9083485766 ps
T140 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.652961926 Mar 07 03:50:27 PM PST 24 Mar 07 04:00:43 PM PST 24 4009816064 ps
T380 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.432055618 Mar 07 03:37:32 PM PST 24 Mar 07 03:41:14 PM PST 24 2679337688 ps
T871 /workspace/coverage/default/1.chip_sw_aes_enc.1697389748 Mar 07 03:41:32 PM PST 24 Mar 07 03:46:13 PM PST 24 2850542228 ps
T145 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1889172384 Mar 07 03:41:46 PM PST 24 Mar 07 03:47:41 PM PST 24 19017755134 ps
T387 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1865131926 Mar 07 04:03:35 PM PST 24 Mar 07 04:12:00 PM PST 24 3773965742 ps
T872 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.784289049 Mar 07 04:00:35 PM PST 24 Mar 07 04:19:06 PM PST 24 5185533236 ps
T873 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.827711004 Mar 07 03:59:16 PM PST 24 Mar 07 04:02:34 PM PST 24 2904848356 ps
T729 /workspace/coverage/default/88.chip_sw_all_escalation_resets.3821243821 Mar 07 04:09:25 PM PST 24 Mar 07 04:21:23 PM PST 24 4786703100 ps
T318 /workspace/coverage/default/2.chip_sival_flash_info_access.2017232051 Mar 07 03:51:37 PM PST 24 Mar 07 03:58:21 PM PST 24 3621691976 ps
T874 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1023879728 Mar 07 03:54:24 PM PST 24 Mar 07 04:04:54 PM PST 24 3728671564 ps
T694 /workspace/coverage/default/2.chip_sw_hmac_smoketest.3926330729 Mar 07 04:00:25 PM PST 24 Mar 07 04:06:02 PM PST 24 2636940736 ps
T875 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1287360768 Mar 07 03:39:23 PM PST 24 Mar 07 03:47:18 PM PST 24 4127920178 ps
T106 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1191475432 Mar 07 03:42:11 PM PST 24 Mar 07 04:46:36 PM PST 24 19284918452 ps
T206 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1797131793 Mar 07 04:05:28 PM PST 24 Mar 07 04:12:58 PM PST 24 3217561320 ps
T876 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2677173189 Mar 07 03:47:23 PM PST 24 Mar 07 03:55:12 PM PST 24 3730324040 ps
T199 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.244482166 Mar 07 04:00:24 PM PST 24 Mar 07 04:06:02 PM PST 24 3658757312 ps
T877 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1831893804 Mar 07 04:02:45 PM PST 24 Mar 07 04:12:38 PM PST 24 5978971870 ps
T878 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3418084770 Mar 07 03:44:26 PM PST 24 Mar 07 04:21:08 PM PST 24 9256922950 ps
T15 /workspace/coverage/default/0.chip_sw_usbdev_vbus.3852567181 Mar 07 03:40:06 PM PST 24 Mar 07 03:45:11 PM PST 24 3019898260 ps
T879 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.4065348523 Mar 07 03:38:12 PM PST 24 Mar 07 03:45:52 PM PST 24 3604329410 ps
T664 /workspace/coverage/default/30.chip_sw_all_escalation_resets.706263329 Mar 07 04:05:15 PM PST 24 Mar 07 04:14:41 PM PST 24 4416495788 ps
T119 /workspace/coverage/default/10.chip_sw_all_escalation_resets.1547778959 Mar 07 04:02:58 PM PST 24 Mar 07 04:13:58 PM PST 24 5347187612 ps
T880 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.4009258144 Mar 07 03:46:41 PM PST 24 Mar 07 03:50:51 PM PST 24 3167823688 ps
T881 /workspace/coverage/default/0.chip_sw_aon_timer_irq.3386817177 Mar 07 03:36:33 PM PST 24 Mar 07 03:42:44 PM PST 24 3872915790 ps
T211 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.199540187 Mar 07 03:56:40 PM PST 24 Mar 07 04:05:35 PM PST 24 5013752240 ps
T194 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1969236861 Mar 07 03:45:25 PM PST 24 Mar 07 04:16:54 PM PST 24 22906955784 ps
T189 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3151337296 Mar 07 03:40:26 PM PST 24 Mar 07 03:55:44 PM PST 24 5641682920 ps
T319 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.4092010298 Mar 07 03:51:53 PM PST 24 Mar 07 04:03:09 PM PST 24 4570184120 ps
T150 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2241354660 Mar 07 03:37:40 PM PST 24 Mar 07 04:43:26 PM PST 24 18877822974 ps
T641 /workspace/coverage/default/0.chip_sw_edn_sw_mode.1795623327 Mar 07 03:40:12 PM PST 24 Mar 07 04:23:40 PM PST 24 9930535574 ps
T69 /workspace/coverage/default/3.chip_tap_straps_rma.4268935572 Mar 07 04:00:30 PM PST 24 Mar 07 04:25:48 PM PST 24 12388194355 ps
T882 /workspace/coverage/default/1.chip_sw_otbn_randomness.3484542661 Mar 07 03:41:19 PM PST 24 Mar 07 03:57:39 PM PST 24 5494486296 ps
T883 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.756138815 Mar 07 04:00:29 PM PST 24 Mar 07 04:04:52 PM PST 24 2936158576 ps
T77 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3327671863 Mar 07 03:40:57 PM PST 24 Mar 07 06:42:16 PM PST 24 58762936048 ps
T884 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3536966465 Mar 07 03:55:49 PM PST 24 Mar 07 04:07:42 PM PST 24 4140999782 ps
T347 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2471615995 Mar 07 04:02:55 PM PST 24 Mar 07 04:20:32 PM PST 24 5558056710 ps
T261 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3761772138 Mar 07 03:44:17 PM PST 24 Mar 07 04:20:05 PM PST 24 9205588158 ps
T426 /workspace/coverage/default/0.chip_sw_otbn_smoketest.3251286492 Mar 07 03:38:02 PM PST 24 Mar 07 04:18:45 PM PST 24 9533759512 ps
T117 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1773069891 Mar 07 04:08:52 PM PST 24 Mar 07 04:15:38 PM PST 24 3434986840 ps
T246 /workspace/coverage/default/2.chip_sw_rv_timer_irq.2545678050 Mar 07 03:54:25 PM PST 24 Mar 07 03:59:03 PM PST 24 3130573604 ps
T156 /workspace/coverage/default/2.chip_sw_edn_kat.2425990571 Mar 07 03:55:30 PM PST 24 Mar 07 04:07:25 PM PST 24 3302449256 ps
T265 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.715830325 Mar 07 04:02:16 PM PST 24 Mar 07 04:16:15 PM PST 24 6212111184 ps
T270 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2730189026 Mar 07 03:56:42 PM PST 24 Mar 07 04:03:21 PM PST 24 4715474236 ps
T130 /workspace/coverage/default/17.chip_sw_all_escalation_resets.4084199096 Mar 07 04:04:22 PM PST 24 Mar 07 04:14:41 PM PST 24 5936232772 ps
T271 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1928024552 Mar 07 03:54:55 PM PST 24 Mar 07 04:53:39 PM PST 24 18584744422 ps
T272 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2351855120 Mar 07 03:42:17 PM PST 24 Mar 07 04:00:58 PM PST 24 8603669390 ps
T273 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2020877625 Mar 07 03:39:34 PM PST 24 Mar 07 03:45:19 PM PST 24 3372586488 ps
T274 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.2507008572 Mar 07 03:49:22 PM PST 24 Mar 07 03:56:10 PM PST 24 4662108580 ps
T275 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1426612164 Mar 07 04:09:25 PM PST 24 Mar 07 04:15:12 PM PST 24 3796829328 ps
T276 /workspace/coverage/default/0.chip_sw_example_concurrency.81238801 Mar 07 03:37:49 PM PST 24 Mar 07 03:43:15 PM PST 24 3279990920 ps
T233 /workspace/coverage/default/72.chip_sw_all_escalation_resets.1633984929 Mar 07 04:07:23 PM PST 24 Mar 07 04:16:04 PM PST 24 5063965400 ps
T110 /workspace/coverage/default/2.chip_plic_all_irqs_10.3836353040 Mar 07 03:55:58 PM PST 24 Mar 07 04:03:39 PM PST 24 3052000936 ps
T234 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1942886194 Mar 07 03:53:42 PM PST 24 Mar 07 04:05:21 PM PST 24 4635042938 ps
T256 /workspace/coverage/default/0.rom_volatile_raw_unlock.3660947292 Mar 07 03:38:48 PM PST 24 Mar 07 03:40:36 PM PST 24 2659800534 ps
T257 /workspace/coverage/default/2.chip_sw_aes_enc.2975965013 Mar 07 03:55:50 PM PST 24 Mar 07 03:59:55 PM PST 24 2851135552 ps
T258 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2890384061 Mar 07 03:53:59 PM PST 24 Mar 07 03:57:05 PM PST 24 2156345406 ps
T259 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.224413353 Mar 07 04:06:19 PM PST 24 Mar 07 04:12:37 PM PST 24 2956553594 ps
T81 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2483911459 Mar 07 04:07:36 PM PST 24 Mar 07 04:12:56 PM PST 24 3757748140 ps
T90 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2828562880 Mar 07 03:44:53 PM PST 24 Mar 07 04:06:46 PM PST 24 8542943070 ps
T91 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.265748216 Mar 07 03:39:44 PM PST 24 Mar 07 03:48:23 PM PST 24 4737808703 ps
T92 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3500472470 Mar 07 04:07:42 PM PST 24 Mar 07 04:16:45 PM PST 24 4136940432 ps
T93 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.38980880 Mar 07 03:59:02 PM PST 24 Mar 07 04:09:10 PM PST 24 5339581627 ps
T94 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3681307512 Mar 07 03:40:50 PM PST 24 Mar 07 04:01:31 PM PST 24 6452354437 ps
T95 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2602384863 Mar 07 03:36:41 PM PST 24 Mar 07 03:44:32 PM PST 24 3735552908 ps
T96 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.4095358515 Mar 07 03:55:32 PM PST 24 Mar 07 03:59:40 PM PST 24 2655458384 ps
T97 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3914101875 Mar 07 04:07:45 PM PST 24 Mar 07 04:14:19 PM PST 24 4323392260 ps
T98 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.783724940 Mar 07 03:56:08 PM PST 24 Mar 07 04:03:57 PM PST 24 5701009128 ps
T885 /workspace/coverage/default/2.chip_sw_uart_smoketest.2313923625 Mar 07 04:00:38 PM PST 24 Mar 07 04:04:29 PM PST 24 2062370520 ps
T262 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.212042049 Mar 07 03:43:04 PM PST 24 Mar 07 04:17:57 PM PST 24 8727598676 ps
T236 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1701538707 Mar 07 03:53:30 PM PST 24 Mar 07 04:27:18 PM PST 24 13724553502 ps
T169 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.84143601 Mar 07 03:42:30 PM PST 24 Mar 07 07:21:12 PM PST 24 64457396095 ps
T141 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1801879839 Mar 07 03:49:03 PM PST 24 Mar 07 03:53:46 PM PST 24 3370459480 ps
T295 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1532675863 Mar 07 03:35:41 PM PST 24 Mar 07 03:38:55 PM PST 24 2911858225 ps
T185 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1487389316 Mar 07 03:37:04 PM PST 24 Mar 07 03:51:42 PM PST 24 5050000584 ps
T296 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3602711711 Mar 07 03:38:08 PM PST 24 Mar 07 03:46:46 PM PST 24 5131603472 ps
T242 /workspace/coverage/default/0.chip_sw_plic_sw_irq.2522305193 Mar 07 03:41:07 PM PST 24 Mar 07 03:46:15 PM PST 24 2510651096 ps
T266 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.1258960716 Mar 07 04:00:39 PM PST 24 Mar 07 04:15:42 PM PST 24 6293014306 ps
T297 /workspace/coverage/default/95.chip_sw_all_escalation_resets.4284258234 Mar 07 04:09:15 PM PST 24 Mar 07 04:21:59 PM PST 24 4970702424 ps
T149 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.460247163 Mar 07 03:40:01 PM PST 24 Mar 07 04:43:18 PM PST 24 19464095628 ps
T108 /workspace/coverage/default/2.rom_raw_unlock.4286381690 Mar 07 04:00:27 PM PST 24 Mar 07 04:32:49 PM PST 24 16321966640 ps
T298 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3161675529 Mar 07 04:01:05 PM PST 24 Mar 07 04:12:38 PM PST 24 7568714250 ps
T305 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1962995403 Mar 07 03:39:38 PM PST 24 Mar 07 03:51:33 PM PST 24 3914610972 ps
T306 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.115364488 Mar 07 03:40:02 PM PST 24 Mar 07 03:57:25 PM PST 24 6170802274 ps
T307 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2800543541 Mar 07 04:06:35 PM PST 24 Mar 07 04:13:22 PM PST 24 3550885040 ps
T308 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.4112076419 Mar 07 03:38:07 PM PST 24 Mar 07 03:52:03 PM PST 24 8228257062 ps
T277 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.279123502 Mar 07 03:56:31 PM PST 24 Mar 07 04:08:13 PM PST 24 5460771990 ps
T309 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.206156984 Mar 07 03:43:26 PM PST 24 Mar 07 04:31:56 PM PST 24 11562278888 ps
T20 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2065769313 Mar 07 03:42:07 PM PST 24 Mar 07 04:09:13 PM PST 24 23729562286 ps
T886 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1988792874 Mar 07 03:56:18 PM PST 24 Mar 07 04:04:00 PM PST 24 4174941500 ps
T192 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3229082045 Mar 07 04:01:32 PM PST 24 Mar 07 05:08:33 PM PST 24 23338809188 ps
T714 /workspace/coverage/default/96.chip_sw_all_escalation_resets.3270188410 Mar 07 04:10:18 PM PST 24 Mar 07 04:23:55 PM PST 24 5935369100 ps
T887 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.664655959 Mar 07 03:49:07 PM PST 24 Mar 07 03:52:01 PM PST 24 2702963758 ps
T137 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.615803321 Mar 07 03:36:41 PM PST 24 Mar 07 03:38:53 PM PST 24 3555118941 ps
T888 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1262302530 Mar 07 03:39:12 PM PST 24 Mar 07 04:03:32 PM PST 24 7787254540 ps
T170 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.410069171 Mar 07 03:52:21 PM PST 24 Mar 07 06:45:47 PM PST 24 58049110275 ps
T180 /workspace/coverage/default/0.chip_sw_power_idle_load.2330747082 Mar 07 03:37:40 PM PST 24 Mar 07 03:47:30 PM PST 24 4828207064 ps
T889 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3757760515 Mar 07 03:39:15 PM PST 24 Mar 07 03:42:16 PM PST 24 3166934752 ps
T890 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.1069654208 Mar 07 03:48:24 PM PST 24 Mar 07 03:52:39 PM PST 24 2721251743 ps
T410 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1202023981 Mar 07 04:03:10 PM PST 24 Mar 07 04:09:08 PM PST 24 3951649396 ps
T891 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.175060153 Mar 07 03:52:04 PM PST 24 Mar 07 04:02:57 PM PST 24 2860033064 ps
T758 /workspace/coverage/default/60.chip_sw_all_escalation_resets.3679344173 Mar 07 04:06:12 PM PST 24 Mar 07 04:18:18 PM PST 24 6019461640 ps
T249 /workspace/coverage/default/0.chip_sw_edn_auto_mode.674242165 Mar 07 03:38:07 PM PST 24 Mar 07 03:54:39 PM PST 24 3952970736 ps
T425 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1726000836 Mar 07 04:07:19 PM PST 24 Mar 07 04:14:11 PM PST 24 3623027452 ps
T892 /workspace/coverage/default/0.chip_sw_hmac_smoketest.1041246092 Mar 07 03:40:08 PM PST 24 Mar 07 03:44:51 PM PST 24 2828802760 ps
T893 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.328033943 Mar 07 03:38:37 PM PST 24 Mar 07 03:42:14 PM PST 24 2515710152 ps
T16 /workspace/coverage/default/0.chip_sw_usbdev_stream.106157171 Mar 07 03:41:01 PM PST 24 Mar 07 04:54:01 PM PST 24 18859200448 ps
T894 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.4157011718 Mar 07 03:57:22 PM PST 24 Mar 07 04:02:41 PM PST 24 2575835620 ps
T895 /workspace/coverage/default/1.chip_tap_straps_dev.2561665966 Mar 07 03:50:09 PM PST 24 Mar 07 03:52:23 PM PST 24 2768083566 ps
T896 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1041544572 Mar 07 03:41:54 PM PST 24 Mar 07 03:46:39 PM PST 24 2631024581 ps
T408 /workspace/coverage/default/2.chip_sw_kmac_app_rom.2541346308 Mar 07 03:56:29 PM PST 24 Mar 07 04:01:15 PM PST 24 3045961096 ps
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