Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	161279	1			T75	74		T79	6		T107	6
values[2]	4214	1			T107	1		T522	72		T430	1
values[3]	1784	1			T522	27		T430	1		T441	20
values[4]	1267	1			T522	10		T430	1		T441	14
values[5]	966	1			T522	20		T430	1		T441	17
values[6]	850	1			T522	23		T430	1		T441	11
values[7]	743	1			T522	26		T430	1		T441	14
values[8]	735	1			T522	49		T430	1		T441	8
values[9]	734	1			T522	68		T430	1		T441	9
values[10]	612	1			T522	39		T430	1		T441	9
values[11]	591	1			T522	17		T430	1		T441	6
values[12]	485	1			T522	33		T430	1		T441	2
values[13]	365	1			T522	24		T430	1		T441	3
values[14]	381	1			T522	14		T430	1		T441	2
values[15]	394	1			T522	5		T430	1		T441	1
values[16]	332	1			T522	4		T430	1		T441	4
values[17]	305	1			T522	1		T430	1		T441	13
values[18]	246	1			T430	1		T441	12		T480	2
values[19]	262	1			T430	1		T441	16		T480	2
values[20]	256	1			T430	1		T441	6		T480	2
values[21]	238	1			T430	1		T480	2		T790	1
values[22]	208	1			T430	1		T480	2		T790	1
values[23]	233	1			T430	1		T480	2		T790	1
values[24]	220	1			T430	1		T480	2		T790	1
values[25]	264	1			T430	1		T480	2		T790	1
values[26]	268	1			T430	1		T480	2		T790	1
values[27]	209	1			T430	1		T480	2		T790	1
values[28]	173	1			T430	1		T480	2		T790	1
values[29]	148	1			T430	1		T480	2		T790	1
values[30]	138	1			T430	1		T480	2		T790	1
values[31]	129	1			T430	1		T480	2		T790	1
values[32]	112	1			T430	1		T480	2		T790	1
values[33]	101	1			T430	1		T480	2		T790	1
values[34]	85	1			T430	1		T480	2		T790	1
values[35]	95	1			T430	1		T480	2		T790	1
values[36]	95	1			T430	1		T480	2		T790	1
values[37]	131	1			T430	1		T480	2		T790	1
values[38]	140	1			T430	1		T480	2		T790	1
values[39]	112	1			T430	1		T480	2		T790	1
values[40]	101	1			T430	1		T480	2		T790	1
values[41]	76	1			T430	1		T480	2		T790	1
values[42]	65	1			T430	1		T480	2		T790	1
values[43]	71	1			T430	1		T480	2		T790	1
values[44]	78	1			T430	1		T480	2		T790	1
values[45]	74	1			T430	1		T480	2		T790	1
values[46]	66	1			T430	1		T480	2		T790	1
values[47]	80	1			T430	1		T480	2		T790	1
values[48]	82	1			T430	1		T480	2		T790	1
values[49]	69	1			T430	1		T480	2		T790	1
values[50]	65	1			T430	1		T480	2		T790	1
values[51]	78	1			T430	1		T480	2		T790	1
values[52]	84	1			T430	1		T480	2		T790	1
values[53]	71	1			T430	1		T480	2		T790	1
values[54]	69	1			T430	1		T480	2		T790	1
values[55]	82	1			T430	1		T480	3		T790	1
values[56]	89	1			T430	1		T480	2		T790	1
values[57]	77	1			T430	1		T480	2		T790	1
values[58]	72	1			T430	1		T480	2		T790	1
values[59]	78	1			T430	1		T480	2		T790	1
values[60]	83	1			T430	1		T480	2		T790	1
values[61]	76	1			T430	1		T480	2		T790	1
values[62]	93	1			T430	1		T480	2		T790	1
values[63]	80	1			T430	1		T480	2		T790	1
values[64]	87	1			T430	1		T480	2		T790	1
values[65]	82	1			T430	1		T480	2		T790	1
values[66]	66	1			T430	1		T480	2		T790	1
values[67]	63	1			T430	1		T480	2		T790	1
values[68]	73	1			T430	1		T480	2		T790	1
values[69]	95	1			T430	1		T480	2		T790	1
values[70]	91	1			T430	1		T480	2		T790	1
values[71]	78	1			T430	1		T480	2		T790	1
values[72]	69	1			T430	1		T480	2		T790	1
values[73]	75	1			T430	1		T480	2		T790	1
values[74]	74	1			T430	1		T480	2		T790	1
values[75]	82	1			T430	1		T480	2		T790	1
values[76]	86	1			T430	1		T480	2		T790	1
values[77]	86	1			T430	1		T480	2		T790	1
values[78]	108	1			T430	1		T480	2		T790	1
values[79]	124	1			T430	1		T480	2		T790	1
values[80]	92	1			T430	1		T480	2		T790	1
values[81]	90	1			T430	1		T480	2		T790	1
values[82]	104	1			T430	1		T480	2		T790	1
values[83]	95	1			T430	1		T480	2		T790	1
values[84]	107	1			T430	1		T480	2		T790	1
values[85]	99	1			T430	1		T480	2		T790	1
values[86]	100	1			T430	1		T480	2		T790	1
values[87]	95	1			T430	1		T480	2		T790	1
values[88]	102	1			T430	1		T480	3		T790	1
values[89]	87	1			T430	1		T480	3		T790	1
values[90]	112	1			T430	1		T480	6		T790	2
values[91]	99	1			T430	1		T480	5		T790	1
values[92]	91	1			T430	1		T480	3		T790	2
values[93]	100	1			T430	1		T480	5		T790	2
values[94]	103	1			T430	1		T480	3		T790	2
values[95]	107	1			T430	1		T480	3		T790	1
values[96]	100	1			T430	1		T480	2		T790	2
values[97]	99	1			T430	1		T480	2		T790	6
values[98]	99	1			T430	1		T480	5		T790	9
values[99]	97	1			T430	1		T480	4		T790	2
values[100]	104	1			T430	1		T480	4		T790	3
values[101]	104	1			T430	1		T480	4		T790	1
values[102]	114	1			T430	1		T480	4		T790	2
values[103]	108	1			T430	1		T480	8		T790	1
values[104]	119	1			T430	1		T480	5		T790	4
values[105]	124	1			T430	1		T480	5		T790	3
values[106]	96	1			T430	1		T480	5		T790	1
values[107]	133	1			T430	1		T480	7		T790	2
values[108]	122	1			T430	1		T480	7		T790	1
values[109]	122	1			T430	1		T480	2		T790	2
values[110]	130	1			T430	1		T480	4		T790	2
values[111]	132	1			T430	1		T480	4		T790	4
values[112]	136	1			T430	1		T480	4		T790	5
values[113]	140	1			T430	1		T480	4		T790	2
values[114]	132	1			T430	1		T480	4		T790	2
values[115]	129	1			T430	3		T480	5		T790	2
values[116]	144	1			T430	2		T480	4		T790	3
values[117]	160	1			T430	4		T480	3		T790	1
values[118]	144	1			T430	3		T480	6		T790	1
values[119]	145	1			T430	1		T480	4		T790	2
values[120]	148	1			T430	1		T480	8		T790	2
values[121]	148	1			T430	2		T480	4		T790	2
values[122]	151	1			T430	2		T480	4		T790	2
values[123]	179	1			T430	1		T480	6		T790	1
values[124]	316	1			T430	1		T480	2		T790	1
values[125]	566	1			T430	3		T480	4		T790	2
values[126]	963	1			T430	29		T480	20		T790	12
values[127]	2971	1			T430	119		T480	220		T790	116
values[128]	5076	1			T430	177		T480	467		T790	216