Unified Coverage Report :: Group Instance : rv

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T107	1	T428	1	T430	1
small_delay	654	1		T76	1	T157	1	T427	1
zero	646	1		T75	1	T79	1	T80	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T523	1	T854	1	T525	1
small_delay	954	1		T76	1	T107	1	T157	1
zero	646	1		T75	1	T79	1	T80	1