Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	443	1			T157	1		T521	1		T534	1
all_values[1]	428	1			T76	1		T157	2		T534	3
all_values[2]	444	1			T157	1		T532	2		T430	1
all_values[3]	444	1			T157	3		T520	1		T534	3
all_values[4]	489	1			T157	2		T532	1		T534	2
all_values[5]	495	1			T522	1		T520	1		T534	2
all_values[6]	488	1			T157	2		T532	1		T534	4
all_values[7]	485	1			T157	3		T430	1		T519	1
all_values[8]	473	1			T157	3		T534	5		T777	1
all_values[9]	476	1			T76	1		T157	1		T520	1
all_values[10]	479	1			T157	1		T534	1		T777	1
all_values[11]	481	1			T157	1		T522	1		T519	2
all_values[12]	447	1			T521	1		T534	3		T527	3
all_values[13]	499	1			T157	2		T534	2		T527	5
all_values[14]	490	1			T522	1		T430	1		T520	1
all_values[15]	472	1			T522	1		T430	1		T520	1
all_values[16]	474	1			T532	2		T522	1		T534	1
all_values[17]	456	1			T532	1		T521	2		T534	6
all_values[18]	453	1			T157	1		T522	1		T430	1
all_values[19]	422	1			T76	1		T532	1		T519	1
all_values[20]	481	1			T157	2		T534	2		T527	1
all_values[21]	481	1			T76	1		T430	1		T521	1
all_values[22]	480	1			T157	1		T532	1		T519	1
all_values[23]	457	1			T157	1		T532	2		T522	1
all_values[24]	484	1			T76	1		T157	1		T532	1
all_values[25]	458	1			T76	1		T430	1		T534	2
all_values[26]	441	1			T532	1		T534	1		T527	2
all_values[27]	465	1			T76	1		T157	2		T520	1
all_values[28]	475	1			T157	2		T430	1		T534	3
all_values[29]	407	1			T76	1		T157	2		T532	1
all_values[30]	449	1			T157	1		T522	1		T534	1
all_values[31]	469	1			T76	1		T157	1		T532	1
all_values[32]	456	1			T532	2		T430	1		T534	1
all_values[33]	437	1			T157	2		T521	1		T519	1
all_values[34]	459	1			T157	2		T430	1		T534	3
all_values[35]	475	1			T157	1		T532	1		T522	1
all_values[36]	448	1			T534	1		T527	3		T441	2
all_values[37]	474	1			T157	1		T532	1		T430	1
all_values[38]	491	1			T522	1		T430	1		T534	4
all_values[39]	493	1			T157	2		T532	2		T527	3
all_values[40]	455	1			T157	1		T532	2		T534	3
all_values[41]	442	1			T520	1		T534	1		T776	1
all_values[42]	471	1			T532	1		T534	3		T527	1
all_values[43]	500	1			T157	1		T427	1		T520	2
all_values[44]	481	1			T157	2		T532	2		T819	1
all_values[45]	466	1			T532	1		T430	1		T520	1
all_values[46]	476	1			T157	1		T520	2		T534	3
all_values[47]	455	1			T157	1		T522	1		T534	2
all_values[48]	492	1			T157	1		T532	3		T520	1
all_values[49]	477	1			T157	1		T427	1		T430	1