Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3280	1			T157	12		T532	2		T522	4
all_values[1]	3327	1			T157	19		T532	5		T522	4
all_values[2]	3318	1			T157	18		T532	2		T522	4
all_values[3]	3315	1			T157	19		T532	1		T522	6
all_values[4]	3428	1			T157	14		T532	2		T522	3
all_values[5]	3341	1			T157	12		T532	7		T522	4
all_values[6]	3382	1			T157	18		T532	5		T522	5
all_values[7]	3315	1			T157	17		T532	2		T522	6
all_values[8]	3392	1			T157	20		T532	2		T522	3
all_values[9]	3373	1			T157	12		T532	1		T522	5
all_values[10]	3363	1			T157	11		T532	9		T522	4
all_values[11]	3356	1			T157	22		T532	7		T522	3
all_values[12]	3384	1			T157	20		T532	3		T522	8
all_values[13]	3360	1			T157	22		T532	3		T522	2
all_values[14]	3436	1			T157	12		T532	6		T522	2
all_values[15]	3411	1			T157	13		T532	6		T522	5
all_values[16]	3407	1			T157	22		T532	5		T522	5
all_values[17]	3335	1			T157	13		T532	4		T522	4
all_values[18]	3298	1			T157	19		T532	3		T522	9
all_values[19]	3320	1			T157	16		T532	4		T522	1
all_values[20]	3408	1			T157	19		T532	5		T522	2
all_values[21]	3422	1			T157	18		T532	1		T522	5
all_values[22]	3376	1			T157	32		T532	7		T522	2
all_values[23]	3266	1			T157	21		T532	2		T522	3
all_values[24]	3387	1			T157	19		T532	2		T522	4
all_values[25]	3391	1			T157	11		T532	2		T522	3
all_values[26]	3472	1			T157	19		T532	4		T522	6
all_values[27]	3380	1			T157	18		T532	5		T522	3
all_values[28]	3467	1			T157	14		T532	6		T522	3
all_values[29]	3362	1			T157	18		T532	4		T522	3
all_values[30]	3342	1			T157	15		T532	5		T522	2
all_values[31]	3378	1			T157	15		T532	2		T522	3
all_values[32]	3345	1			T157	14		T532	3		T522	9
all_values[33]	3300	1			T157	22		T532	3		T522	8
all_values[34]	3305	1			T157	15		T532	5		T522	8
all_values[35]	3244	1			T157	17		T532	5		T522	3
all_values[36]	3307	1			T157	14		T532	3		T522	4
all_values[37]	3335	1			T157	20		T532	6		T522	5
all_values[38]	3403	1			T157	16		T532	4		T522	6
all_values[39]	3341	1			T157	17		T532	4		T522	2
all_values[40]	3506	1			T157	19		T532	3		T522	2
all_values[41]	3403	1			T157	20		T532	4		T522	4
all_values[42]	3357	1			T157	18		T532	2		T522	5
all_values[43]	3304	1			T157	17		T532	2		T522	3
all_values[44]	3448	1			T157	25		T532	4		T522	3
all_values[45]	3456	1			T157	16		T532	5		T522	5
all_values[46]	3392	1			T157	23		T532	1		T522	3
all_values[47]	3336	1			T157	12		T532	3		T522	3
all_values[48]	3401	1			T157	15		T532	9		T522	6
all_values[49]	3325	1			T157	16		T532	2		T522	5
all_values[50]	3423	1			T157	19		T532	1		T522	4
all_values[51]	3377	1			T157	17		T532	4		T522	2
all_values[52]	3432	1			T157	20		T532	4		T522	4
all_values[53]	3413	1			T157	20		T532	3		T522	2
all_values[54]	3442	1			T157	13		T532	4		T522	2
all_values[55]	3302	1			T157	19		T532	3		T522	7
all_values[56]	3355	1			T157	17		T532	1		T522	5
all_values[57]	3331	1			T157	16		T532	2		T522	2
all_values[58]	3325	1			T157	15		T532	3		T522	3
all_values[59]	3464	1			T157	16		T532	4		T522	1
all_values[60]	3369	1			T157	19		T532	7		T522	3
all_values[61]	3435	1			T157	14		T532	2		T522	2
all_values[62]	3328	1			T157	12		T532	3		T522	4
all_values[63]	3445	1			T157	20		T532	6		T522	4