Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.aon_timer_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	149546	1			T69	7		T70	69		T73	45
values[2]	9904	1			T70	6		T74	1		T222	1
values[3]	3663	1			T403	1		T507	27		T398	20
values[4]	2177	1			T403	2		T507	16		T398	2
values[5]	1433	1			T403	3		T507	4		T582	1
values[6]	1037	1			T403	2		T507	6		T582	2
values[7]	706	1			T403	2		T507	5		T582	2
values[8]	591	1			T403	3		T507	3		T582	2
values[9]	467	1			T403	2		T507	4		T582	3
values[10]	412	1			T403	9		T507	2		T582	11
values[11]	380	1			T403	3		T582	3		T792	4
values[12]	305	1			T403	2		T582	1		T792	1
values[13]	253	1			T403	3		T582	2		T793	4
values[14]	319	1			T403	2		T582	1		T793	6
values[15]	362	1			T403	2		T582	7		T793	14
values[16]	260	1			T403	4		T582	6		T793	2
values[17]	252	1			T403	3		T582	4		T793	3
values[18]	254	1			T403	2		T582	2		T793	4
values[19]	261	1			T403	2		T582	6		T793	3
values[20]	284	1			T403	2		T582	1		T793	9
values[21]	282	1			T403	2		T582	2		T793	13
values[22]	275	1			T403	4		T582	2		T793	19
values[23]	244	1			T403	1		T582	2		T793	5
values[24]	192	1			T403	2		T582	2		T793	7
values[25]	241	1			T403	5		T582	5		T793	6
values[26]	219	1			T403	7		T582	3		T793	2
values[27]	238	1			T403	4		T582	1		T793	3
values[28]	261	1			T403	5		T582	4		T793	7
values[29]	266	1			T403	8		T582	4		T793	4
values[30]	219	1			T403	4		T582	3		T793	6
values[31]	206	1			T403	3		T582	1		T793	10
values[32]	255	1			T403	3		T582	2		T793	20
values[33]	270	1			T403	2		T582	2		T793	3
values[34]	226	1			T403	1		T582	1		T793	5
values[35]	224	1			T403	4		T582	3		T793	7
values[36]	186	1			T403	1		T582	1		T793	5
values[37]	259	1			T403	3		T582	1		T793	5
values[38]	273	1			T403	7		T582	2		T793	8
values[39]	248	1			T403	6		T582	2		T793	4
values[40]	223	1			T403	1		T582	3		T793	3
values[41]	208	1			T403	6		T582	1		T793	10
values[42]	194	1			T403	3		T582	1		T793	8
values[43]	198	1			T403	2		T582	4		T793	7
values[44]	221	1			T403	2		T582	5		T793	4
values[45]	238	1			T403	4		T582	5		T793	4
values[46]	189	1			T403	1		T582	4		T793	4
values[47]	199	1			T403	1		T582	3		T793	13
values[48]	191	1			T403	4		T582	1		T793	7
values[49]	205	1			T403	4		T582	2		T793	4
values[50]	179	1			T403	2		T582	4		T793	8
values[51]	210	1			T403	3		T582	10		T793	12
values[52]	196	1			T403	4		T582	7		T793	8
values[53]	194	1			T403	2		T582	7		T793	5
values[54]	197	1			T403	4		T582	12		T793	5
values[55]	157	1			T403	3		T582	4		T793	8
values[56]	181	1			T403	2		T582	3		T793	9
values[57]	211	1			T403	1		T582	2		T793	4
values[58]	193	1			T403	2		T582	3		T793	5
values[59]	150	1			T403	2		T582	4		T793	3
values[60]	217	1			T403	3		T582	1		T793	6
values[61]	198	1			T403	1		T582	1		T793	15
values[62]	165	1			T403	8		T582	10		T793	3
values[63]	152	1			T403	8		T582	6		T793	14
values[64]	149	1			T403	8		T582	3		T793	10
values[65]	137	1			T403	6		T582	1		T440	4
values[66]	105	1			T403	2		T582	3		T440	2
values[67]	99	1			T403	1		T582	3		T440	3
values[68]	115	1			T403	4		T582	12		T440	1
values[69]	97	1			T403	2		T582	5		T440	4
values[70]	94	1			T403	2		T582	1		T440	9
values[71]	65	1			T403	2		T582	1		T440	3
values[72]	78	1			T403	1		T582	5		T440	2
values[73]	75	1			T403	3		T582	8		T440	5
values[74]	60	1			T403	2		T582	2		T440	3
values[75]	85	1			T403	1		T582	3		T440	6
values[76]	110	1			T403	2		T582	7		T440	4
values[77]	102	1			T403	1		T582	3		T440	2
values[78]	74	1			T403	1		T582	7		T440	1
values[79]	70	1			T403	1		T582	2		T440	2
values[80]	71	1			T403	1		T582	4		T440	6
values[81]	66	1			T403	5		T582	2		T440	8
values[82]	67	1			T403	1		T582	1		T440	6
values[83]	95	1			T403	2		T582	2		T440	2
values[84]	63	1			T403	2		T582	1		T440	1
values[85]	56	1			T403	1		T582	2		T440	3
values[86]	82	1			T403	3		T582	11		T440	4
values[87]	55	1			T403	1		T582	2		T440	3
values[88]	52	1			T403	1		T582	2		T440	6
values[89]	58	1			T403	3		T582	2		T440	6
values[90]	61	1			T403	3		T582	2		T440	8
values[91]	67	1			T403	4		T582	3		T440	9
values[92]	47	1			T403	2		T582	4		T440	3
values[93]	60	1			T403	3		T582	3		T440	4
values[94]	51	1			T403	2		T582	1		T440	3
values[95]	53	1			T403	2		T582	5		T440	3
values[96]	66	1			T403	5		T582	2		T440	1
values[97]	51	1			T403	6		T582	1		T440	3
values[98]	56	1			T403	2		T582	2		T440	7
values[99]	63	1			T403	8		T582	2		T440	6
values[100]	79	1			T403	10		T582	1		T440	4
values[101]	53	1			T403	4		T582	4		T440	3
values[102]	78	1			T403	2		T582	10		T440	2
values[103]	55	1			T403	2		T582	4		T440	4
values[104]	54	1			T403	6		T582	1		T440	5
values[105]	65	1			T403	10		T582	3		T440	5
values[106]	73	1			T403	13		T582	1		T440	3
values[107]	67	1			T403	19		T582	2		T440	3
values[108]	45	1			T403	6		T582	1		T440	4
values[109]	66	1			T403	9		T582	1		T440	4
values[110]	67	1			T403	4		T582	4		T440	2
values[111]	59	1			T403	10		T582	9		T440	2
values[112]	65	1			T403	3		T582	2		T440	5
values[113]	66	1			T403	3		T582	2		T440	9
values[114]	44	1			T403	4		T582	2		T440	4
values[115]	44	1			T403	12		T582	2		T440	1
values[116]	55	1			T403	5		T582	1		T440	8
values[117]	70	1			T403	8		T582	3		T440	7
values[118]	63	1			T403	7		T582	4		T440	11
values[119]	63	1			T403	2		T582	3		T440	4
values[120]	51	1			T403	2		T582	1		T440	4
values[121]	56	1			T403	1		T582	3		T440	7
values[122]	70	1			T403	4		T582	8		T440	7
values[123]	64	1			T403	7		T582	5		T440	3
values[124]	70	1			T403	6		T582	7		T440	4
values[125]	57	1			T582	5		T440	7		T452	7
values[126]	97	1			T582	13		T440	3		T452	19
values[127]	682	1			T582	56		T440	2		T452	46
values[128]	5267	1			T582	24		T440	1		T452	24