Name |
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1626964143 |
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.4227812796 |
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.285691700 |
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.698026733 |
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.4210269558 |
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.3128844826 |
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1100333010 |
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.206659034 |
/workspace/coverage/cover_reg_top/0.xbar_error_random.2926413456 |
/workspace/coverage/cover_reg_top/0.xbar_random.3571179226 |
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.8173884 |
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.274606869 |
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2131060135 |
/workspace/coverage/cover_reg_top/0.xbar_same_source.1813745627 |
/workspace/coverage/cover_reg_top/0.xbar_smoke.3163446365 |
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2650607381 |
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2053407947 |
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2273899973 |
/workspace/coverage/cover_reg_top/0.xbar_stress_all.3355335976 |
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.1579715280 |
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2592525070 |
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1191721124 |
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3018749587 |
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1728051690 |
/workspace/coverage/cover_reg_top/1.chip_csr_rw.3036400016 |
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.813776700 |
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3823017966 |
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3556976738 |
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.28505905 |
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2886571641 |
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.245090236 |
/workspace/coverage/cover_reg_top/1.xbar_error_random.3570235112 |
/workspace/coverage/cover_reg_top/1.xbar_random.3129666718 |
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.305355520 |
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1534224011 |
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.4091544016 |
/workspace/coverage/cover_reg_top/1.xbar_same_source.2132682921 |
/workspace/coverage/cover_reg_top/1.xbar_smoke.4290870222 |
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1125452507 |
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.408115936 |
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2642915769 |
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2524535810 |
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.2961391814 |
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1614355750 |
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2373058498 |
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2502667004 |
/workspace/coverage/cover_reg_top/10.chip_csr_rw.969800168 |
/workspace/coverage/cover_reg_top/10.chip_tl_errors.723312751 |
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1145323172 |
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3401206438 |
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.792948057 |
/workspace/coverage/cover_reg_top/10.xbar_error_random.2003234837 |
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.4046600926 |
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3744863197 |
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.4202379265 |
/workspace/coverage/cover_reg_top/10.xbar_same_source.253491057 |
/workspace/coverage/cover_reg_top/10.xbar_smoke.679742839 |
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.77145413 |
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.620205924 |
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.683026484 |
/workspace/coverage/cover_reg_top/10.xbar_stress_all.4142239530 |
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1919096067 |
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2923431049 |
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2810794222 |
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3202535382 |
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2583217968 |
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2066576329 |
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.720014336 |
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.671594278 |
/workspace/coverage/cover_reg_top/11.xbar_error_random.2058852745 |
/workspace/coverage/cover_reg_top/11.xbar_random.4161729729 |
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3372052338 |
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3426704613 |
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3903726912 |
/workspace/coverage/cover_reg_top/11.xbar_same_source.625980841 |
/workspace/coverage/cover_reg_top/11.xbar_smoke.3021758278 |
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2573922378 |
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.583233288 |
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2772337573 |
/workspace/coverage/cover_reg_top/11.xbar_stress_all.865750116 |
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2844440359 |
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2479545650 |
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2578980815 |
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3824320700 |
/workspace/coverage/cover_reg_top/12.chip_csr_rw.3631730049 |
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3352417120 |
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.106578158 |
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1170294659 |
/workspace/coverage/cover_reg_top/12.xbar_error_random.354877840 |
/workspace/coverage/cover_reg_top/12.xbar_random.138234280 |
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3498106224 |
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2763032037 |
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3504020928 |
/workspace/coverage/cover_reg_top/12.xbar_same_source.3483893159 |
/workspace/coverage/cover_reg_top/12.xbar_smoke.3277139579 |
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3704969545 |
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.4167721942 |
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3365618250 |
/workspace/coverage/cover_reg_top/12.xbar_stress_all.1706422983 |
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2870028588 |
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.885981128 |
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2443261872 |
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1975728223 |
/workspace/coverage/cover_reg_top/13.chip_csr_rw.1360447776 |
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2362237810 |
/workspace/coverage/cover_reg_top/13.chip_tl_errors.831354198 |
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.3346320589 |
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2885811822 |
/workspace/coverage/cover_reg_top/13.xbar_error_random.521386549 |
/workspace/coverage/cover_reg_top/13.xbar_random.2188745579 |
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.463815965 |
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3864513142 |
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.4231163125 |
/workspace/coverage/cover_reg_top/13.xbar_same_source.2392714301 |
/workspace/coverage/cover_reg_top/13.xbar_smoke.2308653846 |
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3644547128 |
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.2077172329 |
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3944712618 |
/workspace/coverage/cover_reg_top/13.xbar_stress_all.2632753236 |
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.939446040 |
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3757765810 |
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.927647552 |
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2185728027 |
/workspace/coverage/cover_reg_top/14.chip_csr_rw.1440793838 |
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.4081270020 |
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.115240858 |
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3991427474 |
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3852871122 |
/workspace/coverage/cover_reg_top/14.xbar_error_random.2548815092 |
/workspace/coverage/cover_reg_top/14.xbar_random.1338223943 |
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.1491512042 |
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.333450554 |
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.3705469225 |
/workspace/coverage/cover_reg_top/14.xbar_same_source.328288826 |
/workspace/coverage/cover_reg_top/14.xbar_smoke.4178987116 |
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.4022255533 |
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2507132617 |
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3303262731 |
/workspace/coverage/cover_reg_top/14.xbar_stress_all.3035766512 |
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.701047125 |
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.1380023209 |
/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.3607081785 |
/workspace/coverage/cover_reg_top/15.chip_csr_rw.1371503465 |
/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.555293162 |
/workspace/coverage/cover_reg_top/15.xbar_access_same_device.3487654151 |
/workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.2099083257 |
/workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.1853915499 |
/workspace/coverage/cover_reg_top/15.xbar_error_random.502775495 |
/workspace/coverage/cover_reg_top/15.xbar_random.1633714534 |
/workspace/coverage/cover_reg_top/15.xbar_random_large_delays.2157800006 |
/workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.2897597696 |
/workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.1246093944 |
/workspace/coverage/cover_reg_top/15.xbar_same_source.3053839538 |
/workspace/coverage/cover_reg_top/15.xbar_smoke.3234324498 |
/workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.3274239804 |
/workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.2947250408 |
/workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.4062390181 |
/workspace/coverage/cover_reg_top/15.xbar_stress_all.152543414 |
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.937612644 |
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.51229528 |
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1402189006 |
/workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.3501533742 |
/workspace/coverage/cover_reg_top/16.chip_csr_rw.1035342975 |
/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.4221953027 |
/workspace/coverage/cover_reg_top/16.chip_tl_errors.1467586873 |
/workspace/coverage/cover_reg_top/16.xbar_access_same_device.1336995521 |
/workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1419439687 |
/workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.760023280 |
/workspace/coverage/cover_reg_top/16.xbar_error_random.3347116638 |
/workspace/coverage/cover_reg_top/16.xbar_random.855392044 |
/workspace/coverage/cover_reg_top/16.xbar_random_large_delays.3562703779 |
/workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.2959649363 |
/workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.888471166 |
/workspace/coverage/cover_reg_top/16.xbar_same_source.2384142935 |
/workspace/coverage/cover_reg_top/16.xbar_smoke.3329447769 |
/workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.3918637332 |
/workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.3864402369 |
/workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.467402526 |
/workspace/coverage/cover_reg_top/16.xbar_stress_all.3423941831 |
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.2330625419 |
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.2081115604 |
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.74949245 |
/workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.2536706511 |
/workspace/coverage/cover_reg_top/17.chip_csr_rw.4189670413 |
/workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.1813376413 |
/workspace/coverage/cover_reg_top/17.chip_tl_errors.536981461 |
/workspace/coverage/cover_reg_top/17.xbar_access_same_device.507226007 |
/workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1170965208 |
/workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.2993287940 |
/workspace/coverage/cover_reg_top/17.xbar_error_random.454899140 |
/workspace/coverage/cover_reg_top/17.xbar_random.3138549553 |
/workspace/coverage/cover_reg_top/17.xbar_random_large_delays.1597123816 |
/workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.1264476122 |
/workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.560432154 |
/workspace/coverage/cover_reg_top/17.xbar_same_source.3271542205 |
/workspace/coverage/cover_reg_top/17.xbar_smoke.3915471695 |
/workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.486039352 |
/workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.3428046349 |
/workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.1263973129 |
/workspace/coverage/cover_reg_top/17.xbar_stress_all.3155605203 |
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.2477338775 |
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.3328800875 |
/workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.1662249899 |
/workspace/coverage/cover_reg_top/18.chip_csr_rw.3382169674 |
/workspace/coverage/cover_reg_top/18.chip_tl_errors.3343608451 |
/workspace/coverage/cover_reg_top/18.xbar_access_same_device.3925972879 |
/workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.2447193286 |
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/workspace/coverage/cover_reg_top/19.chip_csr_rw.3111647150 |
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/workspace/coverage/cover_reg_top/19.xbar_same_source.319889324 |
/workspace/coverage/cover_reg_top/19.xbar_smoke.714665652 |
/workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.1960221092 |
/workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.1122305306 |
/workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.2750815167 |
/workspace/coverage/cover_reg_top/19.xbar_stress_all.619630890 |
/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.1169566377 |
/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.1490466046 |
/workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.3503162323 |
/workspace/coverage/cover_reg_top/2.chip_csr_aliasing.4293036653 |
/workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.113720098 |
/workspace/coverage/cover_reg_top/2.chip_csr_rw.2326205675 |
/workspace/coverage/cover_reg_top/2.chip_prim_tl_access.454401764 |
/workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.2477706360 |
/workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.3874904266 |
/workspace/coverage/cover_reg_top/2.chip_tl_errors.1601675645 |
/workspace/coverage/cover_reg_top/2.xbar_access_same_device.4021831758 |
/workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2813187053 |
/workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.3478279056 |
/workspace/coverage/cover_reg_top/2.xbar_error_random.2592751988 |
/workspace/coverage/cover_reg_top/2.xbar_random.1138605208 |
/workspace/coverage/cover_reg_top/2.xbar_random_large_delays.2766425746 |
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/workspace/coverage/default/50.chip_sw_all_escalation_resets.3768785204 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.272271523 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.1601732052 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2779636694 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.2486547752 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1515169427 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.142654855 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1086782345 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.991879487 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1855282539 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1212446703 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.2013055798 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2525987110 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3999951552 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.4250427365 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.2049566344 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3130348254 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.1775679953 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1953597006 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3474789530 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.3303216739 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2234008008 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1145421986 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3431281265 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1105548899 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3234080327 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1718536714 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.1110738205 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1168390150 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.231203963 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.4064972092 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.2725745797 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1791582917 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.120934136 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2687174415 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.4107949908 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.327201320 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.3820746704 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.107474803 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3424042917 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3844675652 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2277819118 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1490544650 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3963917687 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.792780552 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.3512548442 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.3868033246 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1200974034 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3758506729 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.502330921 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.2623333897 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.924177286 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2207818370 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1765766053 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2667877310 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.4252460372 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.369157995 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3668936803 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.3358030845 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3721002293 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2565833268 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.740412068 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.18623306 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.629437511 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.517581003 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2370207495 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.1049437846 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1829648740 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2433561501 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3016452160 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1533046983 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3122018660 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.1461585406 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.974207920 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3772733302 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1569999401 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2449845696 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3615797369 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.393404335 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1616703144 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2801254980 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.4167285389 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.1834334972 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1014977112 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1050229859 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1403276851 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.452200002 |
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.4206956256 |
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.4008877737 |
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1291422753 |
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1829958690 |
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3731721834 |
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2669261825 |
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.477659302 |
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3754923811 |
TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
T1 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3364076153 |
|
|
Mar 12 04:04:30 PM PDT 24 |
Mar 12 04:14:31 PM PDT 24 |
3886334726 ps |
T2 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.502330921 |
|
|
Mar 12 04:13:26 PM PDT 24 |
Mar 12 04:19:03 PM PDT 24 |
3710592616 ps |
T3 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3313621730 |
|
|
Mar 12 04:14:42 PM PDT 24 |
Mar 12 04:19:44 PM PDT 24 |
3771095944 ps |
T79 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2842345292 |
|
|
Mar 12 03:45:27 PM PDT 24 |
Mar 12 03:51:23 PM PDT 24 |
3522857536 ps |
T80 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1527751453 |
|
|
Mar 12 03:50:43 PM PDT 24 |
Mar 12 03:53:42 PM PDT 24 |
2758828944 ps |
T49 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.214470953 |
|
|
Mar 12 03:46:42 PM PDT 24 |
Mar 12 04:56:47 PM PDT 24 |
24612855961 ps |
T4 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3331249454 |
|
|
Mar 12 03:50:39 PM PDT 24 |
Mar 12 04:23:47 PM PDT 24 |
8348455475 ps |
T53 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.66232637 |
|
|
Mar 12 03:50:12 PM PDT 24 |
Mar 12 03:51:57 PM PDT 24 |
2346577736 ps |
T32 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3816569698 |
|
|
Mar 12 03:46:23 PM PDT 24 |
Mar 12 03:54:46 PM PDT 24 |
3529000348 ps |
T5 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3040459584 |
|
|
Mar 12 04:07:26 PM PDT 24 |
Mar 12 04:14:09 PM PDT 24 |
5083558675 ps |
T6 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3048577996 |
|
|
Mar 12 03:46:33 PM PDT 24 |
Mar 12 04:02:09 PM PDT 24 |
8637918881 ps |
T126 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1410674383 |
|
|
Mar 12 03:45:40 PM PDT 24 |
Mar 12 03:53:45 PM PDT 24 |
4440254772 ps |
T129 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.4149263264 |
|
|
Mar 12 03:46:21 PM PDT 24 |
Mar 12 03:58:02 PM PDT 24 |
5690818232 ps |
T121 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3834385193 |
|
|
Mar 12 03:50:08 PM PDT 24 |
Mar 12 03:54:34 PM PDT 24 |
3270267228 ps |
T140 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.475520933 |
|
|
Mar 12 04:04:35 PM PDT 24 |
Mar 12 04:24:00 PM PDT 24 |
7328734688 ps |
T141 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.149832361 |
|
|
Mar 12 03:58:33 PM PDT 24 |
Mar 12 04:16:34 PM PDT 24 |
6009636647 ps |
T116 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2439384671 |
|
|
Mar 12 03:59:25 PM PDT 24 |
Mar 12 04:07:09 PM PDT 24 |
5527909360 ps |
T13 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.2902114368 |
|
|
Mar 12 03:48:17 PM PDT 24 |
Mar 12 03:53:38 PM PDT 24 |
2915436531 ps |
T52 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.622518622 |
|
|
Mar 12 03:44:46 PM PDT 24 |
Mar 12 05:08:36 PM PDT 24 |
49109787275 ps |
T405 |
/workspace/coverage/default/2.chip_sw_example_rom.225556686 |
|
|
Mar 12 03:55:11 PM PDT 24 |
Mar 12 03:57:06 PM PDT 24 |
2866027180 ps |
T57 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.101026553 |
|
|
Mar 12 03:43:19 PM PDT 24 |
Mar 12 03:46:27 PM PDT 24 |
2738836694 ps |
T225 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.4053836900 |
|
|
Mar 12 03:55:34 PM PDT 24 |
Mar 12 04:00:11 PM PDT 24 |
2396290624 ps |
T412 |
/workspace/coverage/default/1.chip_sw_kmac_idle.826386467 |
|
|
Mar 12 03:50:46 PM PDT 24 |
Mar 12 03:53:37 PM PDT 24 |
2271548312 ps |
T269 |
/workspace/coverage/default/2.chip_sw_hmac_enc.9094429 |
|
|
Mar 12 04:03:51 PM PDT 24 |
Mar 12 04:09:14 PM PDT 24 |
3140826732 ps |
T54 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.452200002 |
|
|
Mar 12 04:16:34 PM PDT 24 |
Mar 12 04:26:42 PM PDT 24 |
5707819880 ps |
T144 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3945049435 |
|
|
Mar 12 04:02:45 PM PDT 24 |
Mar 12 04:13:31 PM PDT 24 |
4370365288 ps |
T128 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2284632157 |
|
|
Mar 12 03:47:35 PM PDT 24 |
Mar 12 03:56:30 PM PDT 24 |
4963294528 ps |
T55 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.245853077 |
|
|
Mar 12 03:45:26 PM PDT 24 |
Mar 12 04:16:43 PM PDT 24 |
14828475164 ps |
T130 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1743214552 |
|
|
Mar 12 04:02:30 PM PDT 24 |
Mar 12 04:18:09 PM PDT 24 |
11321215416 ps |
T677 |
/workspace/coverage/default/1.chip_sw_aes_entropy.381492295 |
|
|
Mar 12 03:51:44 PM PDT 24 |
Mar 12 03:56:40 PM PDT 24 |
3003765464 ps |
T10 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.2260932933 |
|
|
Mar 12 03:57:13 PM PDT 24 |
Mar 12 04:09:39 PM PDT 24 |
6799810315 ps |
T145 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1210333689 |
|
|
Mar 12 04:05:41 PM PDT 24 |
Mar 12 04:44:18 PM PDT 24 |
14527573041 ps |
T173 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.254803429 |
|
|
Mar 12 04:06:36 PM PDT 24 |
Mar 12 04:23:52 PM PDT 24 |
6085082914 ps |
T122 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.448664840 |
|
|
Mar 12 03:59:51 PM PDT 24 |
Mar 12 05:30:52 PM PDT 24 |
46726577096 ps |
T63 |
/workspace/coverage/default/3.chip_tap_straps_rma.2504796846 |
|
|
Mar 12 04:05:30 PM PDT 24 |
Mar 12 04:07:54 PM PDT 24 |
2540685342 ps |
T171 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3866885369 |
|
|
Mar 12 03:58:26 PM PDT 24 |
Mar 12 04:13:15 PM PDT 24 |
5072133816 ps |
T117 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.994235348 |
|
|
Mar 12 04:04:41 PM PDT 24 |
Mar 12 04:11:19 PM PDT 24 |
9471610584 ps |
T131 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3625415756 |
|
|
Mar 12 03:57:23 PM PDT 24 |
Mar 12 04:01:37 PM PDT 24 |
3364834480 ps |
T38 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1951492654 |
|
|
Mar 12 03:52:31 PM PDT 24 |
Mar 12 04:43:39 PM PDT 24 |
11100900236 ps |
T56 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.3110995122 |
|
|
Mar 12 04:11:08 PM PDT 24 |
Mar 12 04:19:20 PM PDT 24 |
4733738096 ps |
T118 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2736197360 |
|
|
Mar 12 04:08:19 PM PDT 24 |
Mar 12 04:16:15 PM PDT 24 |
6643456500 ps |
T39 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.791915770 |
|
|
Mar 12 03:53:01 PM PDT 24 |
Mar 12 04:21:55 PM PDT 24 |
8488035165 ps |
T66 |
/workspace/coverage/default/2.chip_tap_straps_prod.2889288255 |
|
|
Mar 12 04:02:16 PM PDT 24 |
Mar 12 04:18:24 PM PDT 24 |
9276635243 ps |
T137 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.544515200 |
|
|
Mar 12 03:57:28 PM PDT 24 |
Mar 12 04:03:20 PM PDT 24 |
4264753220 ps |
T147 |
/workspace/coverage/default/0.chip_sw_edn_kat.3605752890 |
|
|
Mar 12 03:45:32 PM PDT 24 |
Mar 12 03:57:00 PM PDT 24 |
3674311276 ps |
T193 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.1399803127 |
|
|
Mar 12 04:12:32 PM PDT 24 |
Mar 12 04:24:07 PM PDT 24 |
5039629248 ps |
T14 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3896866199 |
|
|
Mar 12 03:56:38 PM PDT 24 |
Mar 12 04:12:24 PM PDT 24 |
5876590232 ps |
T174 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.525981608 |
|
|
Mar 12 04:07:45 PM PDT 24 |
Mar 12 04:25:27 PM PDT 24 |
6017134752 ps |
T307 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.879732740 |
|
|
Mar 12 03:44:28 PM PDT 24 |
Mar 12 03:53:22 PM PDT 24 |
4847277108 ps |
T315 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.282972395 |
|
|
Mar 12 03:46:04 PM PDT 24 |
Mar 12 03:59:16 PM PDT 24 |
5938644440 ps |
T190 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.804268558 |
|
|
Mar 12 04:14:22 PM PDT 24 |
Mar 12 04:24:07 PM PDT 24 |
5207886600 ps |
T236 |
/workspace/coverage/default/1.chip_sw_hmac_enc.3763199441 |
|
|
Mar 12 03:50:36 PM PDT 24 |
Mar 12 03:54:44 PM PDT 24 |
2457000984 ps |
T11 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1055754664 |
|
|
Mar 12 03:46:11 PM PDT 24 |
Mar 12 03:55:59 PM PDT 24 |
3651301350 ps |
T148 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.1765642109 |
|
|
Mar 12 03:46:09 PM PDT 24 |
Mar 12 04:07:53 PM PDT 24 |
4839787500 ps |
T20 |
/workspace/coverage/default/2.chip_jtag_csr_rw.2357827763 |
|
|
Mar 12 03:55:27 PM PDT 24 |
Mar 12 04:27:43 PM PDT 24 |
19961397600 ps |
T237 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.427542707 |
|
|
Mar 12 04:03:05 PM PDT 24 |
Mar 12 04:14:17 PM PDT 24 |
7270943242 ps |
T238 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.616457717 |
|
|
Mar 12 04:10:28 PM PDT 24 |
Mar 12 04:18:50 PM PDT 24 |
5032738520 ps |
T149 |
/workspace/coverage/default/1.chip_sw_edn_kat.2464690158 |
|
|
Mar 12 03:52:36 PM PDT 24 |
Mar 12 04:03:00 PM PDT 24 |
2891035510 ps |
T61 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.180280055 |
|
|
Mar 12 03:48:39 PM PDT 24 |
Mar 12 06:51:16 PM PDT 24 |
59777380532 ps |
T62 |
/workspace/coverage/default/1.chip_jtag_csr_rw.2955268008 |
|
|
Mar 12 03:44:34 PM PDT 24 |
Mar 12 04:22:16 PM PDT 24 |
17903629358 ps |
T328 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1177118125 |
|
|
Mar 12 03:47:31 PM PDT 24 |
Mar 12 03:52:23 PM PDT 24 |
2730901446 ps |
T12 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.918522744 |
|
|
Mar 12 03:52:28 PM PDT 24 |
Mar 12 03:55:53 PM PDT 24 |
3318930074 ps |
T228 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.3541459015 |
|
|
Mar 12 03:53:22 PM PDT 24 |
Mar 12 04:14:46 PM PDT 24 |
4801625412 ps |
T329 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1372382901 |
|
|
Mar 12 04:01:18 PM PDT 24 |
Mar 12 04:09:01 PM PDT 24 |
4258042920 ps |
T181 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.291590792 |
|
|
Mar 12 03:45:18 PM PDT 24 |
Mar 12 04:21:46 PM PDT 24 |
24369264508 ps |
T133 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2913093840 |
|
|
Mar 12 03:47:25 PM PDT 24 |
Mar 12 04:00:36 PM PDT 24 |
8445798458 ps |
T109 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.1603779720 |
|
|
Mar 12 04:02:33 PM PDT 24 |
Mar 12 04:10:29 PM PDT 24 |
4161713244 ps |
T175 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3439172277 |
|
|
Mar 12 03:58:26 PM PDT 24 |
Mar 12 04:14:26 PM PDT 24 |
5741953840 ps |
T138 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3228408544 |
|
|
Mar 12 03:55:33 PM PDT 24 |
Mar 12 04:46:47 PM PDT 24 |
15709291788 ps |
T853 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1953597006 |
|
|
Mar 12 04:06:26 PM PDT 24 |
Mar 12 04:17:36 PM PDT 24 |
10344795942 ps |
T214 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.4244383325 |
|
|
Mar 12 04:01:56 PM PDT 24 |
Mar 12 04:11:46 PM PDT 24 |
3268259464 ps |
T16 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3059326769 |
|
|
Mar 12 03:45:53 PM PDT 24 |
Mar 12 04:21:40 PM PDT 24 |
19109269400 ps |
T97 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.2486547752 |
|
|
Mar 12 04:10:22 PM PDT 24 |
Mar 12 04:22:40 PM PDT 24 |
5262400982 ps |
T98 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3369689532 |
|
|
Mar 12 03:50:11 PM PDT 24 |
Mar 12 04:19:28 PM PDT 24 |
24704947030 ps |
T99 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.811635164 |
|
|
Mar 12 04:02:17 PM PDT 24 |
Mar 12 04:06:50 PM PDT 24 |
3018646693 ps |
T100 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2838081752 |
|
|
Mar 12 03:47:48 PM PDT 24 |
Mar 12 04:23:45 PM PDT 24 |
13254142935 ps |
T101 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1659759537 |
|
|
Mar 12 03:52:40 PM PDT 24 |
Mar 12 04:03:05 PM PDT 24 |
4806458750 ps |
T21 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1990053734 |
|
|
Mar 12 03:50:29 PM PDT 24 |
Mar 12 04:49:43 PM PDT 24 |
20148395556 ps |
T102 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1592801294 |
|
|
Mar 12 04:09:21 PM PDT 24 |
Mar 12 04:34:01 PM PDT 24 |
8558751331 ps |
T103 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3507102596 |
|
|
Mar 12 03:53:03 PM PDT 24 |
Mar 12 04:22:45 PM PDT 24 |
8523617764 ps |
T104 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1023870985 |
|
|
Mar 12 04:03:04 PM PDT 24 |
Mar 12 04:10:40 PM PDT 24 |
4109701394 ps |
T194 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.819084905 |
|
|
Mar 12 04:03:59 PM PDT 24 |
Mar 12 05:09:48 PM PDT 24 |
12983683812 ps |
T854 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.498701891 |
|
|
Mar 12 03:57:35 PM PDT 24 |
Mar 12 04:14:22 PM PDT 24 |
5943179889 ps |
T127 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1878203285 |
|
|
Mar 12 03:45:02 PM PDT 24 |
Mar 12 03:56:32 PM PDT 24 |
4679547850 ps |
T142 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1914344594 |
|
|
Mar 12 03:49:14 PM PDT 24 |
Mar 12 03:57:11 PM PDT 24 |
4754548317 ps |
T146 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4251462669 |
|
|
Mar 12 03:49:02 PM PDT 24 |
Mar 12 04:00:09 PM PDT 24 |
4274371570 ps |
T657 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2948407093 |
|
|
Mar 12 04:09:16 PM PDT 24 |
Mar 12 04:15:04 PM PDT 24 |
3402366902 ps |
T107 |
/workspace/coverage/default/1.rom_raw_unlock.3430452754 |
|
|
Mar 12 03:55:53 PM PDT 24 |
Mar 12 04:29:12 PM PDT 24 |
16720308263 ps |
T186 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1200974034 |
|
|
Mar 12 04:13:00 PM PDT 24 |
Mar 12 04:18:23 PM PDT 24 |
3456655680 ps |
T658 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1105548899 |
|
|
Mar 12 04:14:26 PM PDT 24 |
Mar 12 04:19:02 PM PDT 24 |
3461179200 ps |
T660 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2889604510 |
|
|
Mar 12 04:03:24 PM PDT 24 |
Mar 12 04:09:30 PM PDT 24 |
3474284658 ps |
T855 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3255940893 |
|
|
Mar 12 03:56:26 PM PDT 24 |
Mar 12 03:59:33 PM PDT 24 |
2293207368 ps |
T663 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.989826749 |
|
|
Mar 12 04:07:32 PM PDT 24 |
Mar 12 04:15:14 PM PDT 24 |
3767841602 ps |
T198 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3740857077 |
|
|
Mar 12 04:01:29 PM PDT 24 |
Mar 12 04:10:21 PM PDT 24 |
5060352296 ps |
T631 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.98951306 |
|
|
Mar 12 04:08:01 PM PDT 24 |
Mar 12 04:33:04 PM PDT 24 |
9299396789 ps |
T35 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.3777015833 |
|
|
Mar 12 03:45:38 PM PDT 24 |
Mar 12 03:52:38 PM PDT 24 |
3646095001 ps |
T856 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.1275128957 |
|
|
Mar 12 03:55:25 PM PDT 24 |
Mar 12 03:59:38 PM PDT 24 |
2463589730 ps |
T857 |
/workspace/coverage/default/0.chip_sw_coremark.2231528451 |
|
|
Mar 12 03:46:09 PM PDT 24 |
Mar 12 06:32:20 PM PDT 24 |
49615070288 ps |
T290 |
/workspace/coverage/default/0.chip_sival_flash_info_access.1555044053 |
|
|
Mar 12 03:43:08 PM PDT 24 |
Mar 12 03:49:42 PM PDT 24 |
3332821162 ps |
T184 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3016452160 |
|
|
Mar 12 04:14:55 PM PDT 24 |
Mar 12 04:20:16 PM PDT 24 |
3617575584 ps |
T858 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4209766332 |
|
|
Mar 12 03:59:13 PM PDT 24 |
Mar 12 04:11:22 PM PDT 24 |
4341073366 ps |
T239 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1659981902 |
|
|
Mar 12 03:53:43 PM PDT 24 |
Mar 12 04:27:25 PM PDT 24 |
8748807542 ps |
T717 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.954980888 |
|
|
Mar 12 03:45:59 PM PDT 24 |
Mar 12 03:52:16 PM PDT 24 |
3826995912 ps |
T859 |
/workspace/coverage/default/0.chip_sw_example_flash.2558556355 |
|
|
Mar 12 03:44:03 PM PDT 24 |
Mar 12 03:47:44 PM PDT 24 |
3038244292 ps |
T179 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3119181686 |
|
|
Mar 12 04:08:47 PM PDT 24 |
Mar 12 04:20:52 PM PDT 24 |
4311413040 ps |
T860 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1525272576 |
|
|
Mar 12 04:07:45 PM PDT 24 |
Mar 12 04:26:00 PM PDT 24 |
11106776070 ps |
T413 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.4182817973 |
|
|
Mar 12 04:01:58 PM PDT 24 |
Mar 12 04:07:37 PM PDT 24 |
3328971276 ps |
T861 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3336894448 |
|
|
Mar 12 03:51:25 PM PDT 24 |
Mar 12 04:04:16 PM PDT 24 |
4010161096 ps |
T132 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.652695550 |
|
|
Mar 12 03:46:01 PM PDT 24 |
Mar 12 03:48:37 PM PDT 24 |
3292272144 ps |
T187 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.2618843353 |
|
|
Mar 12 04:07:06 PM PDT 24 |
Mar 12 04:17:40 PM PDT 24 |
5455622544 ps |
T219 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3844675652 |
|
|
Mar 12 04:14:59 PM PDT 24 |
Mar 12 04:21:20 PM PDT 24 |
3519804036 ps |
T258 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.1325926901 |
|
|
Mar 12 04:04:02 PM PDT 24 |
Mar 12 04:18:46 PM PDT 24 |
5659558774 ps |
T168 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2972831845 |
|
|
Mar 12 03:56:49 PM PDT 24 |
Mar 12 04:39:08 PM PDT 24 |
23765850157 ps |
T259 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1966049865 |
|
|
Mar 12 03:58:44 PM PDT 24 |
Mar 12 04:05:34 PM PDT 24 |
4286458448 ps |
T260 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2979205696 |
|
|
Mar 12 03:45:36 PM PDT 24 |
Mar 12 04:45:09 PM PDT 24 |
38494437763 ps |
T191 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.278046546 |
|
|
Mar 12 04:05:50 PM PDT 24 |
Mar 12 04:16:42 PM PDT 24 |
4142487720 ps |
T185 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.663732165 |
|
|
Mar 12 03:50:42 PM PDT 24 |
Mar 12 05:19:15 PM PDT 24 |
51717637735 ps |
T242 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2773367779 |
|
|
Mar 12 04:14:49 PM PDT 24 |
Mar 12 04:21:56 PM PDT 24 |
3742262922 ps |
T243 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2491540279 |
|
|
Mar 12 03:48:45 PM PDT 24 |
Mar 12 04:00:22 PM PDT 24 |
5068342750 ps |
T72 |
/workspace/coverage/default/2.chip_jtag_mem_access.3851660460 |
|
|
Mar 12 03:55:35 PM PDT 24 |
Mar 12 04:18:10 PM PDT 24 |
13397028754 ps |
T244 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.4209396314 |
|
|
Mar 12 04:00:30 PM PDT 24 |
Mar 12 04:39:25 PM PDT 24 |
35842023620 ps |
T245 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3010085116 |
|
|
Mar 12 04:01:05 PM PDT 24 |
Mar 12 04:06:40 PM PDT 24 |
2677720450 ps |
T246 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3157072371 |
|
|
Mar 12 04:08:48 PM PDT 24 |
Mar 12 04:15:07 PM PDT 24 |
3433345110 ps |
T247 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3091997138 |
|
|
Mar 12 03:48:35 PM PDT 24 |
Mar 12 03:52:41 PM PDT 24 |
2555081632 ps |
T248 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3825809666 |
|
|
Mar 12 03:49:56 PM PDT 24 |
Mar 12 04:06:09 PM PDT 24 |
5545363200 ps |
T862 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1823570864 |
|
|
Mar 12 03:56:51 PM PDT 24 |
Mar 12 04:23:25 PM PDT 24 |
8350289964 ps |
T188 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.3358030845 |
|
|
Mar 12 04:13:06 PM PDT 24 |
Mar 12 04:22:35 PM PDT 24 |
4836560400 ps |
T863 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3970004207 |
|
|
Mar 12 03:52:54 PM PDT 24 |
Mar 12 04:11:43 PM PDT 24 |
6001868284 ps |
T75 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1751716547 |
|
|
Mar 12 03:46:53 PM PDT 24 |
Mar 12 06:57:26 PM PDT 24 |
254506330892 ps |
T303 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.1721693334 |
|
|
Mar 12 03:49:15 PM PDT 24 |
Mar 12 04:05:21 PM PDT 24 |
6163587036 ps |
T641 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1515169427 |
|
|
Mar 12 04:11:36 PM PDT 24 |
Mar 12 04:18:38 PM PDT 24 |
3714961208 ps |
T864 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.4027013668 |
|
|
Mar 12 03:51:24 PM PDT 24 |
Mar 12 03:59:53 PM PDT 24 |
5013026672 ps |
T647 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1518085940 |
|
|
Mar 12 03:57:26 PM PDT 24 |
Mar 12 03:59:12 PM PDT 24 |
2315402843 ps |
T865 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2146828056 |
|
|
Mar 12 03:59:33 PM PDT 24 |
Mar 12 05:04:51 PM PDT 24 |
47865380603 ps |
T192 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.957226489 |
|
|
Mar 12 04:07:23 PM PDT 24 |
Mar 12 04:17:03 PM PDT 24 |
4649546504 ps |
T866 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3158082581 |
|
|
Mar 12 03:52:01 PM PDT 24 |
Mar 12 04:19:23 PM PDT 24 |
6751018196 ps |
T180 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.3369480371 |
|
|
Mar 12 04:06:52 PM PDT 24 |
Mar 12 04:19:34 PM PDT 24 |
5236922860 ps |
T240 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.721254987 |
|
|
Mar 12 03:52:11 PM PDT 24 |
Mar 12 03:58:29 PM PDT 24 |
3460872029 ps |
T114 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.629437511 |
|
|
Mar 12 04:13:32 PM PDT 24 |
Mar 12 04:19:19 PM PDT 24 |
3448960280 ps |
T115 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.3120942438 |
|
|
Mar 12 04:15:06 PM PDT 24 |
Mar 12 04:24:01 PM PDT 24 |
5897964440 ps |
T867 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3088403695 |
|
|
Mar 12 03:49:55 PM PDT 24 |
Mar 12 04:04:20 PM PDT 24 |
8295800749 ps |
T868 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.3477176513 |
|
|
Mar 12 04:04:01 PM PDT 24 |
Mar 12 04:07:27 PM PDT 24 |
3286928211 ps |
T869 |
/workspace/coverage/default/2.chip_sw_edn_kat.2285019555 |
|
|
Mar 12 04:01:46 PM PDT 24 |
Mar 12 04:14:24 PM PDT 24 |
3392012800 ps |
T64 |
/workspace/coverage/default/4.chip_tap_straps_rma.1838112480 |
|
|
Mar 12 04:07:22 PM PDT 24 |
Mar 12 04:09:29 PM PDT 24 |
2207045807 ps |
T870 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.2347602673 |
|
|
Mar 12 03:51:58 PM PDT 24 |
Mar 12 04:26:11 PM PDT 24 |
9264962649 ps |
T288 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3731365106 |
|
|
Mar 12 04:01:12 PM PDT 24 |
Mar 12 04:12:24 PM PDT 24 |
3811417840 ps |
T871 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3793794613 |
|
|
Mar 12 03:52:27 PM PDT 24 |
Mar 12 04:26:31 PM PDT 24 |
8857264920 ps |
T872 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2559236177 |
|
|
Mar 12 04:01:43 PM PDT 24 |
Mar 12 04:07:30 PM PDT 24 |
2965235064 ps |
T17 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1983850081 |
|
|
Mar 12 03:50:52 PM PDT 24 |
Mar 12 03:56:19 PM PDT 24 |
5128905736 ps |
T659 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.4167285389 |
|
|
Mar 12 04:15:29 PM PDT 24 |
Mar 12 04:23:57 PM PDT 24 |
5558641524 ps |
T873 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.954037195 |
|
|
Mar 12 03:49:47 PM PDT 24 |
Mar 12 03:56:51 PM PDT 24 |
3968235560 ps |
T177 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2143004409 |
|
|
Mar 12 03:52:49 PM PDT 24 |
Mar 12 07:27:29 PM PDT 24 |
79677315630 ps |
T664 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3593130543 |
|
|
Mar 12 04:07:45 PM PDT 24 |
Mar 12 04:14:07 PM PDT 24 |
3826901224 ps |
T15 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.1188038346 |
|
|
Mar 12 04:05:21 PM PDT 24 |
Mar 12 04:11:07 PM PDT 24 |
2573655313 ps |
T76 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.476639435 |
|
|
Mar 12 04:01:48 PM PDT 24 |
Mar 12 04:21:24 PM PDT 24 |
10151042976 ps |
T169 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.648562914 |
|
|
Mar 12 03:57:24 PM PDT 24 |
Mar 12 04:07:23 PM PDT 24 |
4616106288 ps |
T178 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2567605787 |
|
|
Mar 12 03:46:25 PM PDT 24 |
Mar 12 07:24:18 PM PDT 24 |
78528027880 ps |
T356 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1808013165 |
|
|
Mar 12 03:50:36 PM PDT 24 |
Mar 12 04:15:58 PM PDT 24 |
10218355708 ps |
T874 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.493679732 |
|
|
Mar 12 03:52:37 PM PDT 24 |
Mar 12 03:57:20 PM PDT 24 |
2397944129 ps |
T313 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1050229859 |
|
|
Mar 12 04:13:48 PM PDT 24 |
Mar 12 04:23:23 PM PDT 24 |
4968595956 ps |
T77 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.2415505741 |
|
|
Mar 12 04:00:50 PM PDT 24 |
Mar 12 04:04:59 PM PDT 24 |
2903944462 ps |
T875 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.193713978 |
|
|
Mar 12 03:51:33 PM PDT 24 |
Mar 12 04:21:42 PM PDT 24 |
8061492770 ps |
T217 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.3119650860 |
|
|
Mar 12 03:47:16 PM PDT 24 |
Mar 12 03:55:31 PM PDT 24 |
5431940234 ps |
T33 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2725283580 |
|
|
Mar 12 03:44:14 PM PDT 24 |
Mar 12 03:48:25 PM PDT 24 |
2617235584 ps |
T40 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3959131233 |
|
|
Mar 12 04:00:32 PM PDT 24 |
Mar 12 04:04:53 PM PDT 24 |
3354729738 ps |
T202 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.699499438 |
|
|
Mar 12 04:00:37 PM PDT 24 |
Mar 12 05:22:42 PM PDT 24 |
45488275229 ps |
T383 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.696875347 |
|
|
Mar 12 04:10:01 PM PDT 24 |
Mar 12 04:20:27 PM PDT 24 |
4830423528 ps |
T170 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1071114872 |
|
|
Mar 12 03:51:18 PM PDT 24 |
Mar 12 04:02:03 PM PDT 24 |
4832949528 ps |
T336 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1565972102 |
|
|
Mar 12 03:54:27 PM PDT 24 |
Mar 12 03:56:47 PM PDT 24 |
2753592170 ps |
T384 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3877590818 |
|
|
Mar 12 03:48:35 PM PDT 24 |
Mar 12 03:58:48 PM PDT 24 |
4278995950 ps |
T172 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3381306437 |
|
|
Mar 12 03:49:50 PM PDT 24 |
Mar 12 03:54:28 PM PDT 24 |
2809092079 ps |
T385 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3849854263 |
|
|
Mar 12 04:04:00 PM PDT 24 |
Mar 12 04:22:06 PM PDT 24 |
5895471194 ps |
T386 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.1049437846 |
|
|
Mar 12 04:12:57 PM PDT 24 |
Mar 12 04:20:46 PM PDT 24 |
4331851768 ps |
T387 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3474789530 |
|
|
Mar 12 04:08:01 PM PDT 24 |
Mar 12 05:07:16 PM PDT 24 |
23309935094 ps |
T707 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2072326254 |
|
|
Mar 12 04:13:07 PM PDT 24 |
Mar 12 04:19:54 PM PDT 24 |
3883690476 ps |
T876 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1175906729 |
|
|
Mar 12 03:51:59 PM PDT 24 |
Mar 12 04:18:30 PM PDT 24 |
6275145115 ps |
T298 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1860003618 |
|
|
Mar 12 03:46:05 PM PDT 24 |
Mar 12 04:00:00 PM PDT 24 |
4954879160 ps |
T296 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3331303760 |
|
|
Mar 12 03:49:14 PM PDT 24 |
Mar 12 04:06:13 PM PDT 24 |
5511403009 ps |
T877 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.1627354007 |
|
|
Mar 12 03:46:13 PM PDT 24 |
Mar 12 03:55:06 PM PDT 24 |
3339923800 ps |
T291 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2511258158 |
|
|
Mar 12 03:44:50 PM PDT 24 |
Mar 12 04:01:43 PM PDT 24 |
5960720100 ps |
T878 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2390886422 |
|
|
Mar 12 03:49:53 PM PDT 24 |
Mar 12 03:53:18 PM PDT 24 |
2394472760 ps |
T719 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.745922730 |
|
|
Mar 12 04:12:52 PM PDT 24 |
Mar 12 04:18:40 PM PDT 24 |
3894707136 ps |
T713 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.142654855 |
|
|
Mar 12 04:11:20 PM PDT 24 |
Mar 12 04:21:58 PM PDT 24 |
5833654816 ps |
T712 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3668936803 |
|
|
Mar 12 04:15:01 PM PDT 24 |
Mar 12 04:21:59 PM PDT 24 |
4034619196 ps |
T319 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3220216574 |
|
|
Mar 12 03:48:14 PM PDT 24 |
Mar 12 03:54:00 PM PDT 24 |
3039089220 ps |
T406 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1004220850 |
|
|
Mar 12 03:51:12 PM PDT 24 |
Mar 12 03:54:43 PM PDT 24 |
2397600664 ps |
T879 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2370008744 |
|
|
Mar 12 03:48:17 PM PDT 24 |
Mar 12 04:09:20 PM PDT 24 |
7664198424 ps |
T113 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1731307519 |
|
|
Mar 12 03:50:46 PM PDT 24 |
Mar 12 06:49:42 PM PDT 24 |
255438845552 ps |
T204 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1913994233 |
|
|
Mar 12 03:53:18 PM PDT 24 |
Mar 12 04:25:40 PM PDT 24 |
25071718881 ps |
T105 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.3589482329 |
|
|
Mar 12 03:48:12 PM PDT 24 |
Mar 12 04:29:14 PM PDT 24 |
8992836840 ps |
T880 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3162184641 |
|
|
Mar 12 04:02:52 PM PDT 24 |
Mar 12 04:06:33 PM PDT 24 |
3215067777 ps |
T662 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.831779812 |
|
|
Mar 12 04:06:33 PM PDT 24 |
Mar 12 04:13:39 PM PDT 24 |
3918396544 ps |
T881 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3253800727 |
|
|
Mar 12 04:06:14 PM PDT 24 |
Mar 12 04:49:08 PM PDT 24 |
13025246388 ps |
T316 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.527350410 |
|
|
Mar 12 04:00:40 PM PDT 24 |
Mar 12 04:06:12 PM PDT 24 |
4028826478 ps |
T882 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.3147994452 |
|
|
Mar 12 04:05:23 PM PDT 24 |
Mar 12 04:09:47 PM PDT 24 |
3036867244 ps |
T314 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.823115752 |
|
|
Mar 12 04:13:55 PM PDT 24 |
Mar 12 04:25:28 PM PDT 24 |
5687908858 ps |
T883 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.1932998833 |
|
|
Mar 12 03:50:26 PM PDT 24 |
Mar 12 03:54:24 PM PDT 24 |
3064859024 ps |
T330 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.1681440066 |
|
|
Mar 12 03:55:24 PM PDT 24 |
Mar 12 04:04:57 PM PDT 24 |
2607843210 ps |
T884 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.657196198 |
|
|
Mar 12 03:53:41 PM PDT 24 |
Mar 12 04:25:11 PM PDT 24 |
6893739394 ps |
T678 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.826229571 |
|
|
Mar 12 03:45:03 PM PDT 24 |
Mar 12 03:54:11 PM PDT 24 |
7076778900 ps |
T709 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1212446703 |
|
|
Mar 12 04:11:01 PM PDT 24 |
Mar 12 04:16:12 PM PDT 24 |
3032538828 ps |
T143 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1765523536 |
|
|
Mar 12 04:05:37 PM PDT 24 |
Mar 12 04:17:58 PM PDT 24 |
5239008646 ps |
T229 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2356190256 |
|
|
Mar 12 03:52:17 PM PDT 24 |
Mar 12 04:00:27 PM PDT 24 |
5356354818 ps |
T224 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.2574481737 |
|
|
Mar 12 04:03:45 PM PDT 24 |
Mar 12 04:07:41 PM PDT 24 |
2306075140 ps |
T885 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.1683099358 |
|
|
Mar 12 04:07:12 PM PDT 24 |
Mar 12 04:21:40 PM PDT 24 |
4970868392 ps |
T886 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.652206407 |
|
|
Mar 12 03:57:01 PM PDT 24 |
Mar 12 04:02:46 PM PDT 24 |
3294255292 ps |
T123 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.3500561463 |
|
|
Mar 12 04:15:16 PM PDT 24 |
Mar 12 04:23:45 PM PDT 24 |
4926810320 ps |
T355 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1729115564 |
|
|
Mar 12 03:46:22 PM PDT 24 |
Mar 12 03:50:28 PM PDT 24 |
2953762230 ps |
T220 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3130348254 |
|
|
Mar 12 04:07:20 PM PDT 24 |
Mar 12 04:12:52 PM PDT 24 |
4428481804 ps |
T333 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3284793703 |
|
|
Mar 12 03:53:25 PM PDT 24 |
Mar 12 04:38:09 PM PDT 24 |
12531212468 ps |
T665 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3078991973 |
|
|
Mar 12 03:45:11 PM PDT 24 |
Mar 12 04:10:52 PM PDT 24 |
6524720432 ps |
T134 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2359824542 |
|
|
Mar 12 04:03:38 PM PDT 24 |
Mar 12 04:07:22 PM PDT 24 |
2946322320 ps |
T264 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.419093043 |
|
|
Mar 12 04:10:34 PM PDT 24 |
Mar 12 04:18:00 PM PDT 24 |
3936791498 ps |
T265 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.812145396 |
|
|
Mar 12 04:05:31 PM PDT 24 |
Mar 12 04:19:53 PM PDT 24 |
5546074412 ps |
T266 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.30958155 |
|
|
Mar 12 03:52:33 PM PDT 24 |
Mar 12 04:01:45 PM PDT 24 |
5455895048 ps |
T267 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.483462458 |
|
|
Mar 12 04:07:40 PM PDT 24 |
Mar 12 04:42:46 PM PDT 24 |
14093542838 ps |
T268 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1569125458 |
|
|
Mar 12 04:09:44 PM PDT 24 |
Mar 12 04:18:38 PM PDT 24 |
5261231841 ps |
T163 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3231161465 |
|
|
Mar 12 03:45:48 PM PDT 24 |
Mar 12 03:54:35 PM PDT 24 |
7559748730 ps |
T81 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.1870050423 |
|
|
Mar 12 04:12:53 PM PDT 24 |
Mar 12 04:21:57 PM PDT 24 |
5330163160 ps |
T85 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1170329629 |
|
|
Mar 12 03:47:27 PM PDT 24 |
Mar 12 03:50:49 PM PDT 24 |
2059180354 ps |
T86 |
/workspace/coverage/default/0.rom_e2e_smoke.1960833713 |
|
|
Mar 12 03:45:58 PM PDT 24 |
Mar 12 04:25:59 PM PDT 24 |
8498781208 ps |
T87 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1663631640 |
|
|
Mar 12 03:45:01 PM PDT 24 |
Mar 12 04:13:11 PM PDT 24 |
12871043808 ps |
T88 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3469342713 |
|
|
Mar 12 04:01:35 PM PDT 24 |
Mar 12 04:09:14 PM PDT 24 |
8127835626 ps |
T89 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.4219153700 |
|
|
Mar 12 03:44:41 PM PDT 24 |
Mar 12 07:14:58 PM PDT 24 |
64817771456 ps |
T90 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3558995184 |
|
|
Mar 12 03:48:47 PM PDT 24 |
Mar 12 04:01:54 PM PDT 24 |
4693285790 ps |
T91 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.1057238580 |
|
|
Mar 12 03:46:33 PM PDT 24 |
Mar 12 03:52:30 PM PDT 24 |
3435095222 ps |
T92 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1791582917 |
|
|
Mar 12 04:06:53 PM PDT 24 |
Mar 12 04:13:37 PM PDT 24 |
4023020072 ps |
T93 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2917483163 |
|
|
Mar 12 04:09:42 PM PDT 24 |
Mar 12 04:29:32 PM PDT 24 |
6935140648 ps |
T26 |
/workspace/coverage/default/0.chip_sw_gpio.1833040574 |
|
|
Mar 12 03:46:48 PM PDT 24 |
Mar 12 03:54:20 PM PDT 24 |
3890475720 ps |
T18 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3008606465 |
|
|
Mar 12 03:52:51 PM PDT 24 |
Mar 12 04:00:14 PM PDT 24 |
7696535072 ps |
T887 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.260486756 |
|
|
Mar 12 03:46:50 PM PDT 24 |
Mar 12 03:54:50 PM PDT 24 |
5020783308 ps |
T741 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.4250932424 |
|
|
Mar 12 03:51:19 PM PDT 24 |
Mar 12 03:57:34 PM PDT 24 |
4073552440 ps |
T226 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.935986944 |
|
|
Mar 12 04:01:04 PM PDT 24 |
Mar 12 04:05:38 PM PDT 24 |
3534357904 ps |
T408 |
/workspace/coverage/default/1.chip_jtag_mem_access.2966423852 |
|
|
Mar 12 03:44:33 PM PDT 24 |
Mar 12 04:06:38 PM PDT 24 |
12920235836 ps |
T19 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.3833131824 |
|
|
Mar 12 03:46:32 PM PDT 24 |
Mar 12 03:51:46 PM PDT 24 |
2895430440 ps |
T888 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2284614073 |
|
|
Mar 12 04:03:13 PM PDT 24 |
Mar 12 04:25:37 PM PDT 24 |
6169707272 ps |
T889 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.4231605596 |
|
|
Mar 12 03:47:01 PM PDT 24 |
Mar 12 03:55:51 PM PDT 24 |
5381948450 ps |
T213 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2692868972 |
|
|
Mar 12 04:11:36 PM PDT 24 |
Mar 12 04:19:02 PM PDT 24 |
3026682290 ps |
T41 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1596468961 |
|
|
Mar 12 03:54:32 PM PDT 24 |
Mar 12 04:25:36 PM PDT 24 |
19866338856 ps |
T203 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2220250064 |
|
|
Mar 12 03:50:02 PM PDT 24 |
Mar 12 05:14:13 PM PDT 24 |
49748588230 ps |
T890 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.4034835276 |
|
|
Mar 12 04:07:23 PM PDT 24 |
Mar 12 04:21:00 PM PDT 24 |
4971525016 ps |
T891 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3008706285 |
|
|
Mar 12 03:58:24 PM PDT 24 |
Mar 12 04:12:36 PM PDT 24 |
5716497640 ps |
T306 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3695333116 |
|
|
Mar 12 03:49:15 PM PDT 24 |
Mar 12 03:57:56 PM PDT 24 |
4057644972 ps |
T310 |
/workspace/coverage/default/2.chip_sival_flash_info_access.770328110 |
|
|
Mar 12 03:58:27 PM PDT 24 |
Mar 12 04:05:21 PM PDT 24 |
3205909494 ps |
T892 |
/workspace/coverage/default/0.chip_sw_kmac_idle.4182376115 |
|
|
Mar 12 03:46:57 PM PDT 24 |
Mar 12 03:52:32 PM PDT 24 |
3133406692 ps |
T893 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1390009792 |
|
|
Mar 12 03:44:36 PM PDT 24 |
Mar 12 03:49:23 PM PDT 24 |
2773447109 ps |
T742 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.2130736410 |
|
|
Mar 12 04:09:08 PM PDT 24 |
Mar 12 04:22:22 PM PDT 24 |
6212164424 ps |
T894 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.477438868 |
|
|
Mar 12 04:08:28 PM PDT 24 |
Mar 12 04:16:15 PM PDT 24 |
7496298620 ps |
T895 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.720193826 |
|
|
Mar 12 03:48:45 PM PDT 24 |
Mar 12 04:04:19 PM PDT 24 |
7339071884 ps |
T44 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.3706483728 |
|
|
Mar 12 03:57:17 PM PDT 24 |
Mar 12 04:03:38 PM PDT 24 |
4522443294 ps |