Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 95.43 94.14 95.01 94.90 97.38 99.49


Total tests in report: 2846
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
39.71 39.71 46.35 46.35 45.04 45.04 25.05 25.05 59.11 59.11 62.48 62.48 0.22 0.22 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3313621730
51.21 11.51 58.33 11.98 58.09 13.05 28.97 3.92 70.92 11.82 90.20 27.73 0.78 0.55 /workspace/coverage/default/0.chip_jtag_csr_rw.4221349481
58.07 6.86 71.10 12.77 67.09 9.00 36.70 7.73 81.98 11.06 90.39 0.18 1.19 0.41 /workspace/coverage/default/2.chip_jtag_csr_rw.2357827763
62.90 4.83 77.23 6.13 70.94 3.85 42.12 5.42 82.15 0.17 90.39 0.00 14.59 13.41 /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.4210867500
67.52 4.61 77.23 0.00 71.30 0.36 42.12 0.00 82.30 0.15 90.39 0.00 41.76 27.17 /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.4290716179
70.69 3.17 77.23 0.00 71.30 0.00 42.12 0.00 82.30 0.00 90.39 0.00 60.80 19.04 /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.2416925351
73.66 2.97 77.46 0.23 71.46 0.16 58.62 16.50 82.49 0.19 91.13 0.74 60.81 0.01 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3048577996
76.46 2.80 77.46 0.00 71.46 0.00 75.39 16.77 82.49 0.00 91.13 0.00 60.86 0.05 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.819084905
78.77 2.30 82.59 5.14 75.21 3.75 78.82 3.43 84.00 1.51 91.13 0.00 60.86 0.00 /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3900014651
80.52 1.75 86.48 3.89 77.33 2.12 80.82 2.00 86.50 2.50 91.13 0.00 60.86 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_0.52766623
82.09 1.57 86.48 0.00 77.38 0.05 80.82 0.00 86.50 0.00 91.13 0.00 70.21 9.35 /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.896095809
83.52 1.43 86.48 0.00 78.44 1.06 80.82 0.00 86.77 0.27 91.13 0.00 77.49 7.27 /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.2519772187
84.79 1.27 87.97 1.50 81.36 2.92 81.02 0.20 89.78 3.02 91.13 0.00 77.49 0.00 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.742421561
85.86 1.07 87.97 0.00 81.36 0.00 81.02 0.00 89.78 0.00 91.13 0.00 83.88 6.39 /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.887315518
86.68 0.82 88.53 0.56 81.94 0.58 84.04 3.02 90.16 0.38 91.50 0.37 83.88 0.00 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3331249454
87.45 0.78 88.88 0.34 82.04 0.10 84.06 0.02 90.30 0.14 95.56 4.07 83.88 0.00 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.443644891
88.17 0.72 88.88 0.00 82.04 0.00 84.06 0.00 90.30 0.00 95.56 0.00 88.19 4.31 /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.2954184700
88.86 0.68 89.55 0.68 83.89 1.84 84.52 0.46 90.57 0.27 95.56 0.00 89.04 0.85 /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1232608279
89.51 0.66 89.55 0.00 84.05 0.16 84.52 0.00 90.61 0.03 95.56 0.00 92.78 3.75 /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1118463216
90.12 0.60 90.80 1.25 84.96 0.91 85.28 0.75 91.32 0.71 95.56 0.00 92.78 0.00 /workspace/coverage/default/0.chip_sw_gpio_smoketest.2902114368
90.71 0.59 91.89 1.09 85.89 0.93 85.74 0.47 92.38 1.06 95.56 0.00 92.78 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_20.2423889825
91.27 0.56 91.90 0.01 88.83 2.94 85.74 0.00 92.38 0.00 95.56 0.00 93.21 0.42 /workspace/coverage/cover_reg_top/1.chip_tl_errors.3009292583
91.71 0.44 92.25 0.35 89.00 0.17 87.21 1.46 92.55 0.17 95.56 0.00 93.67 0.46 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.245853077
92.12 0.41 92.74 0.49 89.41 0.41 87.73 0.53 92.99 0.44 96.12 0.55 93.71 0.05 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.162194199
92.43 0.31 92.74 0.00 89.41 0.00 88.69 0.96 92.99 0.00 96.12 0.00 94.61 0.89 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.476639435
92.73 0.30 93.31 0.57 89.89 0.48 88.97 0.28 93.46 0.47 96.12 0.00 94.61 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_10.1603779720
92.98 0.26 93.31 0.00 89.89 0.00 90.51 1.54 93.46 0.00 96.12 0.00 94.61 0.00 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.622518622
93.19 0.21 93.31 0.00 89.89 0.00 90.51 0.00 93.46 0.00 96.12 0.00 95.89 1.28 /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2392534524
93.38 0.19 94.11 0.80 90.03 0.14 90.66 0.15 93.50 0.04 96.12 0.00 95.89 0.00 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.2260932933
93.57 0.19 94.11 0.00 90.03 0.01 90.66 0.00 93.50 0.00 96.12 0.00 96.99 1.10 /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.2017859260
93.74 0.17 94.12 0.01 90.04 0.01 91.65 0.99 93.50 0.00 96.12 0.00 96.99 0.00 /workspace/coverage/default/0.chip_sw_edn_auto_mode.1765642109
93.89 0.15 94.33 0.22 90.37 0.33 92.01 0.35 93.50 0.00 96.12 0.00 96.99 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.734207439
94.03 0.14 94.34 0.01 90.77 0.40 92.01 0.01 93.94 0.44 96.12 0.00 96.99 0.00 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.4196144335
94.14 0.11 94.34 0.00 90.80 0.03 92.01 0.00 93.96 0.02 96.12 0.00 97.63 0.63 /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.721314848
94.25 0.11 94.36 0.02 90.86 0.06 92.36 0.34 93.99 0.03 96.30 0.18 97.63 0.00 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3364076153
94.35 0.10 94.36 0.00 91.48 0.62 92.36 0.00 93.99 0.00 96.30 0.00 97.63 0.00 /workspace/coverage/cover_reg_top/11.chip_tl_errors.3013537287
94.45 0.10 94.36 0.00 91.76 0.27 92.36 0.00 94.31 0.31 96.30 0.00 97.63 0.00 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.304346763
94.54 0.09 94.36 0.00 91.85 0.09 92.36 0.00 94.32 0.02 96.30 0.00 98.06 0.43 /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.372431379
94.62 0.08 94.36 0.00 91.85 0.01 92.84 0.48 94.32 0.00 96.30 0.00 98.06 0.00 /workspace/coverage/default/95.chip_sw_all_escalation_resets.3500561463
94.69 0.06 94.49 0.13 91.96 0.10 92.88 0.04 94.42 0.10 96.30 0.00 98.07 0.01 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2143004409
94.75 0.06 94.49 0.00 91.96 0.00 93.25 0.38 94.42 0.00 96.30 0.00 98.07 0.00 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1878203285
94.80 0.05 94.53 0.03 91.97 0.01 93.30 0.05 94.43 0.01 96.49 0.18 98.08 0.01 /workspace/coverage/default/98.chip_sw_all_escalation_resets.804268558
94.85 0.05 94.54 0.01 91.98 0.01 93.30 0.00 94.45 0.02 96.67 0.18 98.13 0.05 /workspace/coverage/default/24.chip_sw_all_escalation_resets.1524691276
94.89 0.04 94.54 0.00 91.98 0.00 93.56 0.26 94.45 0.00 96.67 0.00 98.13 0.00 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3625415756
94.93 0.04 94.54 0.01 92.00 0.01 93.60 0.04 94.46 0.01 96.86 0.18 98.13 0.00 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.278046546
94.97 0.04 94.54 0.00 92.25 0.25 93.60 0.00 94.46 0.00 96.86 0.00 98.13 0.00 /workspace/coverage/cover_reg_top/7.chip_tl_errors.3810180101
95.01 0.04 94.60 0.05 92.37 0.13 93.60 0.00 94.53 0.07 96.86 0.00 98.13 0.00 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.3706483728
95.05 0.04 94.67 0.07 92.42 0.04 93.67 0.07 94.58 0.05 96.86 0.00 98.13 0.00 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.683514547
95.09 0.04 94.67 0.01 92.43 0.01 93.68 0.01 94.59 0.01 97.04 0.18 98.14 0.01 /workspace/coverage/default/64.chip_sw_all_escalation_resets.1870050423
95.13 0.04 94.68 0.01 92.45 0.01 93.68 0.00 94.60 0.01 97.23 0.18 98.16 0.01 /workspace/coverage/default/22.chip_sw_all_escalation_resets.1558374466
95.17 0.04 94.68 0.01 92.46 0.01 93.68 0.01 94.60 0.01 97.41 0.18 98.17 0.01 /workspace/coverage/default/1.chip_sw_all_escalation_resets.1681491065
95.20 0.04 94.76 0.08 92.46 0.00 93.82 0.14 94.61 0.01 97.41 0.00 98.17 0.00 /workspace/coverage/default/3.chip_tap_straps_rma.2504796846
95.24 0.04 94.76 0.00 92.52 0.06 93.82 0.00 94.64 0.03 97.41 0.00 98.28 0.12 /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.618585270
95.27 0.03 94.78 0.02 92.60 0.08 93.92 0.10 94.65 0.01 97.41 0.00 98.28 0.00 /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.760871059
95.31 0.03 94.78 0.00 92.60 0.00 94.09 0.17 94.65 0.00 97.41 0.00 98.32 0.04 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1158178779
95.34 0.03 94.78 0.00 92.77 0.17 94.09 0.00 94.65 0.00 97.41 0.00 98.32 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_0.1143440634
95.36 0.03 94.85 0.07 92.80 0.03 94.09 0.01 94.70 0.05 97.41 0.00 98.32 0.00 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1552419315
95.39 0.03 94.88 0.04 92.86 0.06 94.10 0.01 94.75 0.05 97.41 0.00 98.32 0.00 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2567605787
95.41 0.02 94.88 0.00 92.87 0.01 94.10 0.00 94.75 0.00 97.41 0.00 98.45 0.13 /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.345913275
95.43 0.02 94.89 0.01 93.00 0.13 94.10 0.00 94.75 0.00 97.41 0.00 98.45 0.00 /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.856231232
95.45 0.02 94.94 0.05 93.05 0.05 94.10 0.00 94.78 0.02 97.41 0.00 98.45 0.00 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3959131233
95.48 0.02 94.96 0.02 93.08 0.03 94.15 0.05 94.80 0.02 97.41 0.00 98.45 0.00 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.1534581635
95.50 0.02 94.96 0.00 93.08 0.00 94.28 0.12 94.80 0.00 97.41 0.00 98.45 0.00 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.663732165
95.52 0.02 94.96 0.00 93.08 0.01 94.39 0.11 94.80 0.00 97.41 0.00 98.45 0.00 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2439384671
95.53 0.02 94.96 0.00 93.13 0.04 94.39 0.00 94.82 0.02 97.41 0.00 98.50 0.05 /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.959348720
95.55 0.02 94.96 0.00 93.13 0.01 94.44 0.05 94.82 0.00 97.41 0.00 98.54 0.05 /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.352397954
95.57 0.02 94.96 0.00 93.23 0.10 94.44 0.00 94.82 0.00 97.41 0.00 98.54 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_0.1534940615
95.58 0.02 94.96 0.00 93.32 0.09 94.44 0.00 94.82 0.00 97.41 0.00 98.54 0.00 /workspace/coverage/cover_reg_top/14.chip_tl_errors.1174715490
95.60 0.02 94.96 0.00 93.34 0.02 94.45 0.01 94.82 0.00 97.41 0.00 98.61 0.07 /workspace/coverage/default/0.chip_sw_alert_test.3172141230
95.61 0.01 94.98 0.02 93.38 0.04 94.47 0.03 94.82 0.00 97.41 0.00 98.61 0.00 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2725283580
95.62 0.01 94.98 0.00 93.39 0.01 94.47 0.00 94.82 0.00 97.41 0.00 98.67 0.06 /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.3728968223
95.64 0.01 94.99 0.01 93.41 0.02 94.51 0.04 94.82 0.00 97.41 0.00 98.67 0.00 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3331303760
95.65 0.01 95.02 0.04 93.43 0.02 94.51 0.00 94.83 0.01 97.41 0.00 98.67 0.00 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.4195749389
95.66 0.01 95.02 0.00 93.49 0.06 94.51 0.00 94.83 0.00 97.41 0.00 98.67 0.00 /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.3713131870
95.67 0.01 95.05 0.03 93.50 0.01 94.52 0.01 94.84 0.02 97.41 0.00 98.67 0.00 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2460052823
95.67 0.01 95.05 0.00 93.50 0.00 94.58 0.06 94.84 0.00 97.41 0.00 98.67 0.00 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3834385193
95.68 0.01 95.05 0.00 93.55 0.05 94.58 0.00 94.84 0.00 97.41 0.00 98.67 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_20.2453968208
95.69 0.01 95.05 0.00 93.55 0.00 94.63 0.05 94.84 0.00 97.41 0.00 98.67 0.00 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.850502896
95.70 0.01 95.05 0.00 93.58 0.03 94.63 0.00 94.86 0.02 97.41 0.00 98.67 0.00 /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2489796935
95.71 0.01 95.07 0.02 93.59 0.01 94.63 0.01 94.88 0.02 97.41 0.00 98.67 0.00 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.948116867
95.72 0.01 95.07 0.00 93.64 0.05 94.63 0.00 94.88 0.00 97.41 0.00 98.67 0.00 /workspace/coverage/default/1.chip_sw_gpio.2013179809
95.72 0.01 95.07 0.00 93.67 0.03 94.64 0.01 94.88 0.00 97.41 0.00 98.67 0.00 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2491540279
95.73 0.01 95.07 0.00 93.71 0.04 94.64 0.00 94.88 0.00 97.41 0.00 98.67 0.00 /workspace/coverage/cover_reg_top/0.chip_tl_errors.3572499571
95.74 0.01 95.07 0.00 93.75 0.04 94.64 0.00 94.88 0.00 97.41 0.00 98.67 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_10.586563123
95.74 0.01 95.07 0.00 93.76 0.01 94.64 0.00 94.88 0.00 97.41 0.00 98.70 0.02 /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.787908310
95.75 0.01 95.07 0.00 93.76 0.00 94.68 0.04 94.88 0.00 97.41 0.00 98.70 0.00 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3040459584
95.75 0.01 95.08 0.01 93.78 0.01 94.68 0.01 94.88 0.01 97.41 0.00 98.70 0.00 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1349119653
95.76 0.01 95.09 0.01 93.78 0.00 94.71 0.03 94.88 0.00 97.41 0.00 98.70 0.00 /workspace/coverage/default/1.chip_jtag_csr_rw.2955268008
95.77 0.01 95.09 0.00 93.81 0.03 94.71 0.00 94.88 0.00 97.41 0.00 98.70 0.00 /workspace/coverage/cover_reg_top/39.xbar_access_same_device.2110579538
95.77 0.01 95.09 0.00 93.83 0.02 94.71 0.00 94.88 0.00 97.41 0.00 98.71 0.01 /workspace/coverage/cover_reg_top/77.xbar_stress_all.1985681447
95.78 0.01 95.11 0.02 93.83 0.00 94.72 0.01 94.88 0.00 97.41 0.00 98.71 0.00 /workspace/coverage/default/0.chip_sw_power_idle_load.4264448200
95.78 0.01 95.11 0.00 93.83 0.00 94.75 0.03 94.88 0.00 97.41 0.00 98.71 0.00 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.134908652
95.79 0.01 95.11 0.00 93.83 0.00 94.77 0.03 94.88 0.00 97.41 0.00 98.71 0.00 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3981847939
95.79 0.01 95.11 0.00 93.83 0.01 94.77 0.00 94.88 0.00 97.41 0.00 98.73 0.02 /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.2666004700
95.79 0.01 95.11 0.01 93.85 0.02 94.78 0.01 94.88 0.00 97.41 0.00 98.73 0.00 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3078097636
95.80 0.01 95.11 0.00 93.87 0.03 94.78 0.00 94.88 0.00 97.41 0.00 98.73 0.00 /workspace/coverage/cover_reg_top/42.xbar_stress_all.2400848566
95.80 0.01 95.11 0.00 93.90 0.03 94.78 0.00 94.88 0.00 97.41 0.00 98.73 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_20.2050711577
95.81 0.01 95.11 0.00 93.90 0.00 94.80 0.02 94.88 0.00 97.41 0.00 98.73 0.00 /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.278554156
95.81 0.01 95.11 0.00 93.90 0.00 94.83 0.02 94.88 0.00 97.41 0.00 98.73 0.00 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4224437666
95.81 0.01 95.11 0.00 93.90 0.00 94.84 0.01 94.88 0.00 97.41 0.00 98.74 0.01 /workspace/coverage/default/0.chip_sw_all_escalation_resets.282972395
95.82 0.01 95.11 0.00 93.90 0.00 94.84 0.00 94.88 0.00 97.41 0.00 98.77 0.02 /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3912860799
95.82 0.01 95.11 0.00 93.90 0.00 94.84 0.00 94.88 0.00 97.41 0.00 98.79 0.02 /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.1281014763
95.83 0.01 95.11 0.00 93.92 0.02 94.84 0.00 94.88 0.00 97.41 0.00 98.79 0.00 /workspace/coverage/cover_reg_top/64.xbar_stress_all.766856074
95.83 0.01 95.11 0.00 93.92 0.00 94.86 0.02 94.88 0.00 97.41 0.00 98.79 0.00 /workspace/coverage/default/0.chip_tap_straps_rma.1326251668
95.83 0.01 95.11 0.00 93.92 0.00 94.88 0.02 94.88 0.00 97.41 0.00 98.79 0.00 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.95508301
95.84 0.01 95.11 0.00 93.94 0.02 94.88 0.00 94.88 0.00 97.41 0.00 98.79 0.00 /workspace/coverage/cover_reg_top/44.xbar_stress_all.3781465452
95.84 0.01 95.11 0.00 93.96 0.02 94.88 0.00 94.88 0.00 97.41 0.00 98.79 0.00 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2932120339
95.84 0.01 95.11 0.00 93.96 0.00 94.90 0.02 94.88 0.00 97.41 0.00 98.79 0.00 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2197040863
95.84 0.01 95.11 0.00 93.96 0.00 94.91 0.02 94.88 0.00 97.41 0.00 98.79 0.00 /workspace/coverage/default/1.chip_sw_kmac_idle.826386467
95.85 0.01 95.11 0.00 93.97 0.01 94.91 0.00 94.88 0.00 97.41 0.00 98.79 0.00 /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2110490404
95.85 0.01 95.11 0.00 93.98 0.01 94.91 0.00 94.88 0.00 97.41 0.00 98.79 0.00 /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.193567432
95.85 0.01 95.11 0.00 94.00 0.01 94.91 0.00 94.88 0.00 97.41 0.00 98.79 0.00 /workspace/coverage/cover_reg_top/15.chip_tl_errors.4080698107
95.85 0.01 95.11 0.00 94.01 0.01 94.91 0.00 94.88 0.00 97.41 0.00 98.79 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_10.2143415720
95.86 0.01 95.11 0.01 94.02 0.01 94.91 0.00 94.88 0.00 97.41 0.00 98.79 0.00 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1860003618
95.86 0.01 95.12 0.01 94.03 0.01 94.92 0.01 94.88 0.00 97.41 0.00 98.79 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3644195798
95.86 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 98.80 0.01 /workspace/coverage/cover_reg_top/25.chip_tl_errors.192067106
95.86 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 98.81 0.01 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.954980888
95.86 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 98.82 0.01 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.4250932424
95.87 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 98.84 0.01 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3539501724
95.87 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 98.85 0.01 /workspace/coverage/default/10.chip_sw_all_escalation_resets.957226489
95.87 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 98.86 0.01 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3297326618
95.87 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 98.87 0.01 /workspace/coverage/default/11.chip_sw_all_escalation_resets.324131774
95.87 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 98.88 0.01 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.989826749
95.88 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 98.90 0.01 /workspace/coverage/default/13.chip_sw_all_escalation_resets.917408979
95.88 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 98.91 0.01 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.4178603345
95.88 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 98.92 0.01 /workspace/coverage/default/14.chip_sw_all_escalation_resets.3440493684
95.88 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 98.93 0.01 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.649578755
95.88 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 98.94 0.01 /workspace/coverage/default/16.chip_sw_all_escalation_resets.961192270
95.89 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 98.95 0.01 /workspace/coverage/default/17.chip_sw_all_escalation_resets.3769551191
95.89 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 98.97 0.01 /workspace/coverage/default/18.chip_sw_all_escalation_resets.569468500
95.89 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 98.98 0.01 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1331902141
95.89 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 98.99 0.01 /workspace/coverage/default/19.chip_sw_all_escalation_resets.3044287040
95.89 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.00 0.01 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1372382901
95.90 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.01 0.01 /workspace/coverage/default/2.chip_sw_all_escalation_resets.4058798262
95.90 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.02 0.01 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3153709588
95.90 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.04 0.01 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2444701645
95.90 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.05 0.01 /workspace/coverage/default/21.chip_sw_all_escalation_resets.45154163
95.90 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.06 0.01 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3342565683
95.91 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.07 0.01 /workspace/coverage/default/23.chip_sw_all_escalation_resets.4274327596
95.91 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.08 0.01 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2697140235
95.91 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.10 0.01 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1713814155
95.91 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.11 0.01 /workspace/coverage/default/27.chip_sw_all_escalation_resets.3735177137
95.91 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.12 0.01 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2423347249
95.91 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.13 0.01 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1479623869
95.92 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.14 0.01 /workspace/coverage/default/29.chip_sw_all_escalation_resets.506402198
95.92 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.15 0.01 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3593130543
95.92 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.17 0.01 /workspace/coverage/default/3.chip_sw_all_escalation_resets.2618843353
95.92 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.18 0.01 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3532089519
95.92 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.19 0.01 /workspace/coverage/default/31.chip_sw_all_escalation_resets.3199197634
95.93 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.20 0.01 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1724374684
95.93 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.21 0.01 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2948407093
95.93 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.22 0.01 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.423563627
95.93 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.24 0.01 /workspace/coverage/default/36.chip_sw_all_escalation_resets.1003240975
95.93 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.25 0.01 /workspace/coverage/default/37.chip_sw_all_escalation_resets.225348444
95.94 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.26 0.01 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1702339142
95.94 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.27 0.01 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2595184633
95.94 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.28 0.01 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.831779812
95.94 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.29 0.01 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.4208809398
95.94 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.31 0.01 /workspace/coverage/default/41.chip_sw_all_escalation_resets.1976086765
95.95 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.32 0.01 /workspace/coverage/default/42.chip_sw_all_escalation_resets.1897596246
95.95 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.33 0.01 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.546060418
95.95 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.34 0.01 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.4194047119
95.95 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.35 0.01 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1192095834
95.95 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.37 0.01 /workspace/coverage/default/47.chip_sw_all_escalation_resets.3110995122
95.96 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.38 0.01 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1715619107
95.96 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.39 0.01 /workspace/coverage/default/54.chip_sw_all_escalation_resets.1198221895
95.96 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.40 0.01 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2081290477
95.96 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.41 0.01 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.745922730
95.96 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.42 0.01 /workspace/coverage/default/63.chip_sw_all_escalation_resets.3720485955
95.97 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.44 0.01 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.793679424
95.97 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.45 0.01 /workspace/coverage/default/66.chip_sw_all_escalation_resets.1806082076
95.97 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.46 0.01 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3968768482
95.97 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.47 0.01 /workspace/coverage/default/74.chip_sw_all_escalation_resets.3120942438
95.97 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.48 0.01 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2072326254
95.98 0.01 95.12 0.00 94.03 0.00 94.92 0.00 94.88 0.00 97.41 0.00 99.49 0.01 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3494116312
95.98 0.01 95.12 0.00 94.04 0.01 94.92 0.00 94.88 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1929379922
95.98 0.01 95.12 0.00 94.05 0.01 94.92 0.00 94.88 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3770127973
95.98 0.01 95.12 0.00 94.06 0.01 94.92 0.00 94.88 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3119181686
95.98 0.01 95.12 0.01 94.06 0.01 94.92 0.00 94.88 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2511258158
95.98 0.01 95.13 0.01 94.06 0.00 94.93 0.01 94.88 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/90.chip_sw_all_escalation_resets.934068898
95.99 0.01 95.13 0.00 94.06 0.00 94.94 0.01 94.88 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.2502615506
95.99 0.01 95.13 0.00 94.06 0.00 94.95 0.01 94.88 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3231161465
95.99 0.01 95.13 0.00 94.06 0.00 94.95 0.01 94.88 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1525272576
95.99 0.01 95.13 0.00 94.06 0.00 94.96 0.01 94.88 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.214470953
95.99 0.01 95.13 0.00 94.06 0.00 94.96 0.00 94.89 0.01 97.41 0.00 99.49 0.00 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.661828470
95.99 0.01 95.13 0.00 94.06 0.00 94.96 0.00 94.90 0.01 97.41 0.00 99.49 0.00 /workspace/coverage/default/0.chip_tap_straps_dev.2787090687
95.99 0.01 95.13 0.00 94.07 0.01 94.96 0.00 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/cover_reg_top/10.xbar_random.4099052030
96.00 0.01 95.13 0.00 94.08 0.01 94.96 0.00 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/cover_reg_top/2.xbar_stress_all.529549255
96.00 0.01 95.13 0.00 94.09 0.01 94.96 0.00 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.645786153
96.00 0.01 95.13 0.00 94.09 0.01 94.96 0.00 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.3810306303
96.00 0.01 95.14 0.01 94.09 0.00 94.96 0.00 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/0.chip_sw_plic_sw_irq.1057238580
96.00 0.01 95.14 0.01 94.09 0.00 94.96 0.00 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/2.chip_sw_pattgen_ios.3089214869
96.00 0.01 95.14 0.00 94.09 0.00 94.97 0.01 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1349274090
96.00 0.01 95.14 0.00 94.09 0.00 94.98 0.01 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/0.chip_sw_edn_boot_mode.3091554644
96.00 0.01 95.14 0.00 94.09 0.00 94.98 0.01 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/0.chip_sw_hmac_enc.168622474
96.00 0.01 95.14 0.00 94.09 0.00 94.99 0.01 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3786829098
96.01 0.01 95.14 0.00 94.09 0.00 94.99 0.01 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2378686161
96.01 0.01 95.14 0.00 94.09 0.00 95.00 0.01 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3245354120
96.01 0.01 95.14 0.00 94.10 0.01 95.00 0.00 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/cover_reg_top/0.chip_csr_rw.3800213188
96.01 0.01 95.14 0.00 94.10 0.01 95.00 0.00 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/cover_reg_top/12.chip_tl_errors.100114351
96.01 0.01 95.14 0.00 94.10 0.01 95.00 0.00 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.1727326535
96.01 0.01 95.14 0.00 94.11 0.01 95.00 0.00 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.3762891237
96.01 0.01 95.14 0.00 94.11 0.01 95.00 0.00 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.255003064
96.01 0.01 95.14 0.00 94.11 0.01 95.00 0.00 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.3844482752
96.01 0.01 95.14 0.00 94.12 0.01 95.00 0.00 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1265846123
96.01 0.01 95.14 0.00 94.12 0.01 95.00 0.00 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1826364671
96.01 0.01 95.14 0.00 94.13 0.01 95.00 0.00 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/0.chip_sival_flash_info_access.1555044053
96.01 0.01 95.14 0.00 94.13 0.01 95.00 0.00 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1747921950
96.01 0.01 95.14 0.00 94.13 0.01 95.00 0.00 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/0.chip_sw_spi_device_tpm.3777015833
96.01 0.01 95.14 0.00 94.14 0.01 95.00 0.00 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/0.rom_e2e_asm_init_rma.2347602673
96.01 0.01 95.14 0.00 94.14 0.01 95.00 0.00 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/2.chip_sw_aon_timer_irq.1287669909
96.01 0.01 95.15 0.01 94.14 0.00 95.00 0.00 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1404171584
96.02 0.01 95.15 0.00 94.14 0.00 95.00 0.01 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3228408544
96.02 0.01 95.15 0.00 94.14 0.00 95.00 0.01 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2396876448
96.02 0.01 95.15 0.00 94.14 0.00 95.00 0.01 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1203439698
96.02 0.01 95.15 0.00 94.14 0.00 95.01 0.01 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1565972102
96.02 0.01 95.15 0.00 94.14 0.00 95.01 0.01 94.90 0.00 97.41 0.00 99.49 0.00 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3997109779


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1626964143
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.4227812796
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/workspace/coverage/default/97.chip_sw_all_escalation_resets.1403276851
/workspace/coverage/default/99.chip_sw_all_escalation_resets.452200002
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.4206956256
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.4008877737
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1291422753
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1829958690
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3731721834
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2669261825
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.477659302
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3754923811




Total test records in report: 2846
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3364076153 Mar 12 04:04:30 PM PDT 24 Mar 12 04:14:31 PM PDT 24 3886334726 ps
T2 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.502330921 Mar 12 04:13:26 PM PDT 24 Mar 12 04:19:03 PM PDT 24 3710592616 ps
T3 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3313621730 Mar 12 04:14:42 PM PDT 24 Mar 12 04:19:44 PM PDT 24 3771095944 ps
T79 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2842345292 Mar 12 03:45:27 PM PDT 24 Mar 12 03:51:23 PM PDT 24 3522857536 ps
T80 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1527751453 Mar 12 03:50:43 PM PDT 24 Mar 12 03:53:42 PM PDT 24 2758828944 ps
T49 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.214470953 Mar 12 03:46:42 PM PDT 24 Mar 12 04:56:47 PM PDT 24 24612855961 ps
T4 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3331249454 Mar 12 03:50:39 PM PDT 24 Mar 12 04:23:47 PM PDT 24 8348455475 ps
T53 /workspace/coverage/default/0.rom_volatile_raw_unlock.66232637 Mar 12 03:50:12 PM PDT 24 Mar 12 03:51:57 PM PDT 24 2346577736 ps
T32 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3816569698 Mar 12 03:46:23 PM PDT 24 Mar 12 03:54:46 PM PDT 24 3529000348 ps
T5 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3040459584 Mar 12 04:07:26 PM PDT 24 Mar 12 04:14:09 PM PDT 24 5083558675 ps
T6 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3048577996 Mar 12 03:46:33 PM PDT 24 Mar 12 04:02:09 PM PDT 24 8637918881 ps
T126 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1410674383 Mar 12 03:45:40 PM PDT 24 Mar 12 03:53:45 PM PDT 24 4440254772 ps
T129 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.4149263264 Mar 12 03:46:21 PM PDT 24 Mar 12 03:58:02 PM PDT 24 5690818232 ps
T121 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3834385193 Mar 12 03:50:08 PM PDT 24 Mar 12 03:54:34 PM PDT 24 3270267228 ps
T140 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.475520933 Mar 12 04:04:35 PM PDT 24 Mar 12 04:24:00 PM PDT 24 7328734688 ps
T141 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.149832361 Mar 12 03:58:33 PM PDT 24 Mar 12 04:16:34 PM PDT 24 6009636647 ps
T116 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2439384671 Mar 12 03:59:25 PM PDT 24 Mar 12 04:07:09 PM PDT 24 5527909360 ps
T13 /workspace/coverage/default/0.chip_sw_gpio_smoketest.2902114368 Mar 12 03:48:17 PM PDT 24 Mar 12 03:53:38 PM PDT 24 2915436531 ps
T52 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.622518622 Mar 12 03:44:46 PM PDT 24 Mar 12 05:08:36 PM PDT 24 49109787275 ps
T405 /workspace/coverage/default/2.chip_sw_example_rom.225556686 Mar 12 03:55:11 PM PDT 24 Mar 12 03:57:06 PM PDT 24 2866027180 ps
T57 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.101026553 Mar 12 03:43:19 PM PDT 24 Mar 12 03:46:27 PM PDT 24 2738836694 ps
T225 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.4053836900 Mar 12 03:55:34 PM PDT 24 Mar 12 04:00:11 PM PDT 24 2396290624 ps
T412 /workspace/coverage/default/1.chip_sw_kmac_idle.826386467 Mar 12 03:50:46 PM PDT 24 Mar 12 03:53:37 PM PDT 24 2271548312 ps
T269 /workspace/coverage/default/2.chip_sw_hmac_enc.9094429 Mar 12 04:03:51 PM PDT 24 Mar 12 04:09:14 PM PDT 24 3140826732 ps
T54 /workspace/coverage/default/99.chip_sw_all_escalation_resets.452200002 Mar 12 04:16:34 PM PDT 24 Mar 12 04:26:42 PM PDT 24 5707819880 ps
T144 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3945049435 Mar 12 04:02:45 PM PDT 24 Mar 12 04:13:31 PM PDT 24 4370365288 ps
T128 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2284632157 Mar 12 03:47:35 PM PDT 24 Mar 12 03:56:30 PM PDT 24 4963294528 ps
T55 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.245853077 Mar 12 03:45:26 PM PDT 24 Mar 12 04:16:43 PM PDT 24 14828475164 ps
T130 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1743214552 Mar 12 04:02:30 PM PDT 24 Mar 12 04:18:09 PM PDT 24 11321215416 ps
T677 /workspace/coverage/default/1.chip_sw_aes_entropy.381492295 Mar 12 03:51:44 PM PDT 24 Mar 12 03:56:40 PM PDT 24 3003765464 ps
T10 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.2260932933 Mar 12 03:57:13 PM PDT 24 Mar 12 04:09:39 PM PDT 24 6799810315 ps
T145 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1210333689 Mar 12 04:05:41 PM PDT 24 Mar 12 04:44:18 PM PDT 24 14527573041 ps
T173 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.254803429 Mar 12 04:06:36 PM PDT 24 Mar 12 04:23:52 PM PDT 24 6085082914 ps
T122 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.448664840 Mar 12 03:59:51 PM PDT 24 Mar 12 05:30:52 PM PDT 24 46726577096 ps
T63 /workspace/coverage/default/3.chip_tap_straps_rma.2504796846 Mar 12 04:05:30 PM PDT 24 Mar 12 04:07:54 PM PDT 24 2540685342 ps
T171 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3866885369 Mar 12 03:58:26 PM PDT 24 Mar 12 04:13:15 PM PDT 24 5072133816 ps
T117 /workspace/coverage/default/2.chip_sw_power_sleep_load.994235348 Mar 12 04:04:41 PM PDT 24 Mar 12 04:11:19 PM PDT 24 9471610584 ps
T131 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3625415756 Mar 12 03:57:23 PM PDT 24 Mar 12 04:01:37 PM PDT 24 3364834480 ps
T38 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1951492654 Mar 12 03:52:31 PM PDT 24 Mar 12 04:43:39 PM PDT 24 11100900236 ps
T56 /workspace/coverage/default/47.chip_sw_all_escalation_resets.3110995122 Mar 12 04:11:08 PM PDT 24 Mar 12 04:19:20 PM PDT 24 4733738096 ps
T118 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2736197360 Mar 12 04:08:19 PM PDT 24 Mar 12 04:16:15 PM PDT 24 6643456500 ps
T39 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.791915770 Mar 12 03:53:01 PM PDT 24 Mar 12 04:21:55 PM PDT 24 8488035165 ps
T66 /workspace/coverage/default/2.chip_tap_straps_prod.2889288255 Mar 12 04:02:16 PM PDT 24 Mar 12 04:18:24 PM PDT 24 9276635243 ps
T137 /workspace/coverage/default/1.chip_sw_power_sleep_load.544515200 Mar 12 03:57:28 PM PDT 24 Mar 12 04:03:20 PM PDT 24 4264753220 ps
T147 /workspace/coverage/default/0.chip_sw_edn_kat.3605752890 Mar 12 03:45:32 PM PDT 24 Mar 12 03:57:00 PM PDT 24 3674311276 ps
T193 /workspace/coverage/default/40.chip_sw_all_escalation_resets.1399803127 Mar 12 04:12:32 PM PDT 24 Mar 12 04:24:07 PM PDT 24 5039629248 ps
T14 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3896866199 Mar 12 03:56:38 PM PDT 24 Mar 12 04:12:24 PM PDT 24 5876590232 ps
T174 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.525981608 Mar 12 04:07:45 PM PDT 24 Mar 12 04:25:27 PM PDT 24 6017134752 ps
T307 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.879732740 Mar 12 03:44:28 PM PDT 24 Mar 12 03:53:22 PM PDT 24 4847277108 ps
T315 /workspace/coverage/default/0.chip_sw_all_escalation_resets.282972395 Mar 12 03:46:04 PM PDT 24 Mar 12 03:59:16 PM PDT 24 5938644440 ps
T190 /workspace/coverage/default/98.chip_sw_all_escalation_resets.804268558 Mar 12 04:14:22 PM PDT 24 Mar 12 04:24:07 PM PDT 24 5207886600 ps
T236 /workspace/coverage/default/1.chip_sw_hmac_enc.3763199441 Mar 12 03:50:36 PM PDT 24 Mar 12 03:54:44 PM PDT 24 2457000984 ps
T11 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1055754664 Mar 12 03:46:11 PM PDT 24 Mar 12 03:55:59 PM PDT 24 3651301350 ps
T148 /workspace/coverage/default/0.chip_sw_edn_auto_mode.1765642109 Mar 12 03:46:09 PM PDT 24 Mar 12 04:07:53 PM PDT 24 4839787500 ps
T20 /workspace/coverage/default/2.chip_jtag_csr_rw.2357827763 Mar 12 03:55:27 PM PDT 24 Mar 12 04:27:43 PM PDT 24 19961397600 ps
T237 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.427542707 Mar 12 04:03:05 PM PDT 24 Mar 12 04:14:17 PM PDT 24 7270943242 ps
T238 /workspace/coverage/default/45.chip_sw_all_escalation_resets.616457717 Mar 12 04:10:28 PM PDT 24 Mar 12 04:18:50 PM PDT 24 5032738520 ps
T149 /workspace/coverage/default/1.chip_sw_edn_kat.2464690158 Mar 12 03:52:36 PM PDT 24 Mar 12 04:03:00 PM PDT 24 2891035510 ps
T61 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.180280055 Mar 12 03:48:39 PM PDT 24 Mar 12 06:51:16 PM PDT 24 59777380532 ps
T62 /workspace/coverage/default/1.chip_jtag_csr_rw.2955268008 Mar 12 03:44:34 PM PDT 24 Mar 12 04:22:16 PM PDT 24 17903629358 ps
T328 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1177118125 Mar 12 03:47:31 PM PDT 24 Mar 12 03:52:23 PM PDT 24 2730901446 ps
T12 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.918522744 Mar 12 03:52:28 PM PDT 24 Mar 12 03:55:53 PM PDT 24 3318930074 ps
T228 /workspace/coverage/default/1.chip_sw_edn_auto_mode.3541459015 Mar 12 03:53:22 PM PDT 24 Mar 12 04:14:46 PM PDT 24 4801625412 ps
T329 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1372382901 Mar 12 04:01:18 PM PDT 24 Mar 12 04:09:01 PM PDT 24 4258042920 ps
T181 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.291590792 Mar 12 03:45:18 PM PDT 24 Mar 12 04:21:46 PM PDT 24 24369264508 ps
T133 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2913093840 Mar 12 03:47:25 PM PDT 24 Mar 12 04:00:36 PM PDT 24 8445798458 ps
T109 /workspace/coverage/default/2.chip_plic_all_irqs_10.1603779720 Mar 12 04:02:33 PM PDT 24 Mar 12 04:10:29 PM PDT 24 4161713244 ps
T175 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3439172277 Mar 12 03:58:26 PM PDT 24 Mar 12 04:14:26 PM PDT 24 5741953840 ps
T138 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3228408544 Mar 12 03:55:33 PM PDT 24 Mar 12 04:46:47 PM PDT 24 15709291788 ps
T853 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1953597006 Mar 12 04:06:26 PM PDT 24 Mar 12 04:17:36 PM PDT 24 10344795942 ps
T214 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.4244383325 Mar 12 04:01:56 PM PDT 24 Mar 12 04:11:46 PM PDT 24 3268259464 ps
T16 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3059326769 Mar 12 03:45:53 PM PDT 24 Mar 12 04:21:40 PM PDT 24 19109269400 ps
T97 /workspace/coverage/default/52.chip_sw_all_escalation_resets.2486547752 Mar 12 04:10:22 PM PDT 24 Mar 12 04:22:40 PM PDT 24 5262400982 ps
T98 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3369689532 Mar 12 03:50:11 PM PDT 24 Mar 12 04:19:28 PM PDT 24 24704947030 ps
T99 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.811635164 Mar 12 04:02:17 PM PDT 24 Mar 12 04:06:50 PM PDT 24 3018646693 ps
T100 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2838081752 Mar 12 03:47:48 PM PDT 24 Mar 12 04:23:45 PM PDT 24 13254142935 ps
T101 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1659759537 Mar 12 03:52:40 PM PDT 24 Mar 12 04:03:05 PM PDT 24 4806458750 ps
T21 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1990053734 Mar 12 03:50:29 PM PDT 24 Mar 12 04:49:43 PM PDT 24 20148395556 ps
T102 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1592801294 Mar 12 04:09:21 PM PDT 24 Mar 12 04:34:01 PM PDT 24 8558751331 ps
T103 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3507102596 Mar 12 03:53:03 PM PDT 24 Mar 12 04:22:45 PM PDT 24 8523617764 ps
T104 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1023870985 Mar 12 04:03:04 PM PDT 24 Mar 12 04:10:40 PM PDT 24 4109701394 ps
T194 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.819084905 Mar 12 04:03:59 PM PDT 24 Mar 12 05:09:48 PM PDT 24 12983683812 ps
T854 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.498701891 Mar 12 03:57:35 PM PDT 24 Mar 12 04:14:22 PM PDT 24 5943179889 ps
T127 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1878203285 Mar 12 03:45:02 PM PDT 24 Mar 12 03:56:32 PM PDT 24 4679547850 ps
T142 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1914344594 Mar 12 03:49:14 PM PDT 24 Mar 12 03:57:11 PM PDT 24 4754548317 ps
T146 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4251462669 Mar 12 03:49:02 PM PDT 24 Mar 12 04:00:09 PM PDT 24 4274371570 ps
T657 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2948407093 Mar 12 04:09:16 PM PDT 24 Mar 12 04:15:04 PM PDT 24 3402366902 ps
T107 /workspace/coverage/default/1.rom_raw_unlock.3430452754 Mar 12 03:55:53 PM PDT 24 Mar 12 04:29:12 PM PDT 24 16720308263 ps
T186 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1200974034 Mar 12 04:13:00 PM PDT 24 Mar 12 04:18:23 PM PDT 24 3456655680 ps
T658 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1105548899 Mar 12 04:14:26 PM PDT 24 Mar 12 04:19:02 PM PDT 24 3461179200 ps
T660 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2889604510 Mar 12 04:03:24 PM PDT 24 Mar 12 04:09:30 PM PDT 24 3474284658 ps
T855 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3255940893 Mar 12 03:56:26 PM PDT 24 Mar 12 03:59:33 PM PDT 24 2293207368 ps
T663 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.989826749 Mar 12 04:07:32 PM PDT 24 Mar 12 04:15:14 PM PDT 24 3767841602 ps
T198 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3740857077 Mar 12 04:01:29 PM PDT 24 Mar 12 04:10:21 PM PDT 24 5060352296 ps
T631 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.98951306 Mar 12 04:08:01 PM PDT 24 Mar 12 04:33:04 PM PDT 24 9299396789 ps
T35 /workspace/coverage/default/0.chip_sw_spi_device_tpm.3777015833 Mar 12 03:45:38 PM PDT 24 Mar 12 03:52:38 PM PDT 24 3646095001 ps
T856 /workspace/coverage/default/1.chip_sw_csrng_smoketest.1275128957 Mar 12 03:55:25 PM PDT 24 Mar 12 03:59:38 PM PDT 24 2463589730 ps
T857 /workspace/coverage/default/0.chip_sw_coremark.2231528451 Mar 12 03:46:09 PM PDT 24 Mar 12 06:32:20 PM PDT 24 49615070288 ps
T290 /workspace/coverage/default/0.chip_sival_flash_info_access.1555044053 Mar 12 03:43:08 PM PDT 24 Mar 12 03:49:42 PM PDT 24 3332821162 ps
T184 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3016452160 Mar 12 04:14:55 PM PDT 24 Mar 12 04:20:16 PM PDT 24 3617575584 ps
T858 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4209766332 Mar 12 03:59:13 PM PDT 24 Mar 12 04:11:22 PM PDT 24 4341073366 ps
T239 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1659981902 Mar 12 03:53:43 PM PDT 24 Mar 12 04:27:25 PM PDT 24 8748807542 ps
T717 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.954980888 Mar 12 03:45:59 PM PDT 24 Mar 12 03:52:16 PM PDT 24 3826995912 ps
T859 /workspace/coverage/default/0.chip_sw_example_flash.2558556355 Mar 12 03:44:03 PM PDT 24 Mar 12 03:47:44 PM PDT 24 3038244292 ps
T179 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3119181686 Mar 12 04:08:47 PM PDT 24 Mar 12 04:20:52 PM PDT 24 4311413040 ps
T860 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1525272576 Mar 12 04:07:45 PM PDT 24 Mar 12 04:26:00 PM PDT 24 11106776070 ps
T413 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.4182817973 Mar 12 04:01:58 PM PDT 24 Mar 12 04:07:37 PM PDT 24 3328971276 ps
T861 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3336894448 Mar 12 03:51:25 PM PDT 24 Mar 12 04:04:16 PM PDT 24 4010161096 ps
T132 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.652695550 Mar 12 03:46:01 PM PDT 24 Mar 12 03:48:37 PM PDT 24 3292272144 ps
T187 /workspace/coverage/default/3.chip_sw_all_escalation_resets.2618843353 Mar 12 04:07:06 PM PDT 24 Mar 12 04:17:40 PM PDT 24 5455622544 ps
T219 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3844675652 Mar 12 04:14:59 PM PDT 24 Mar 12 04:21:20 PM PDT 24 3519804036 ps
T258 /workspace/coverage/default/2.chip_sw_otbn_randomness.1325926901 Mar 12 04:04:02 PM PDT 24 Mar 12 04:18:46 PM PDT 24 5659558774 ps
T168 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2972831845 Mar 12 03:56:49 PM PDT 24 Mar 12 04:39:08 PM PDT 24 23765850157 ps
T259 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1966049865 Mar 12 03:58:44 PM PDT 24 Mar 12 04:05:34 PM PDT 24 4286458448 ps
T260 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2979205696 Mar 12 03:45:36 PM PDT 24 Mar 12 04:45:09 PM PDT 24 38494437763 ps
T191 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.278046546 Mar 12 04:05:50 PM PDT 24 Mar 12 04:16:42 PM PDT 24 4142487720 ps
T185 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.663732165 Mar 12 03:50:42 PM PDT 24 Mar 12 05:19:15 PM PDT 24 51717637735 ps
T242 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2773367779 Mar 12 04:14:49 PM PDT 24 Mar 12 04:21:56 PM PDT 24 3742262922 ps
T243 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2491540279 Mar 12 03:48:45 PM PDT 24 Mar 12 04:00:22 PM PDT 24 5068342750 ps
T72 /workspace/coverage/default/2.chip_jtag_mem_access.3851660460 Mar 12 03:55:35 PM PDT 24 Mar 12 04:18:10 PM PDT 24 13397028754 ps
T244 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.4209396314 Mar 12 04:00:30 PM PDT 24 Mar 12 04:39:25 PM PDT 24 35842023620 ps
T245 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3010085116 Mar 12 04:01:05 PM PDT 24 Mar 12 04:06:40 PM PDT 24 2677720450 ps
T246 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3157072371 Mar 12 04:08:48 PM PDT 24 Mar 12 04:15:07 PM PDT 24 3433345110 ps
T247 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3091997138 Mar 12 03:48:35 PM PDT 24 Mar 12 03:52:41 PM PDT 24 2555081632 ps
T248 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3825809666 Mar 12 03:49:56 PM PDT 24 Mar 12 04:06:09 PM PDT 24 5545363200 ps
T862 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1823570864 Mar 12 03:56:51 PM PDT 24 Mar 12 04:23:25 PM PDT 24 8350289964 ps
T188 /workspace/coverage/default/80.chip_sw_all_escalation_resets.3358030845 Mar 12 04:13:06 PM PDT 24 Mar 12 04:22:35 PM PDT 24 4836560400 ps
T863 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3970004207 Mar 12 03:52:54 PM PDT 24 Mar 12 04:11:43 PM PDT 24 6001868284 ps
T75 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1751716547 Mar 12 03:46:53 PM PDT 24 Mar 12 06:57:26 PM PDT 24 254506330892 ps
T303 /workspace/coverage/default/1.chip_sw_otbn_randomness.1721693334 Mar 12 03:49:15 PM PDT 24 Mar 12 04:05:21 PM PDT 24 6163587036 ps
T641 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1515169427 Mar 12 04:11:36 PM PDT 24 Mar 12 04:18:38 PM PDT 24 3714961208 ps
T864 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.4027013668 Mar 12 03:51:24 PM PDT 24 Mar 12 03:59:53 PM PDT 24 5013026672 ps
T647 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1518085940 Mar 12 03:57:26 PM PDT 24 Mar 12 03:59:12 PM PDT 24 2315402843 ps
T865 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2146828056 Mar 12 03:59:33 PM PDT 24 Mar 12 05:04:51 PM PDT 24 47865380603 ps
T192 /workspace/coverage/default/10.chip_sw_all_escalation_resets.957226489 Mar 12 04:07:23 PM PDT 24 Mar 12 04:17:03 PM PDT 24 4649546504 ps
T866 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3158082581 Mar 12 03:52:01 PM PDT 24 Mar 12 04:19:23 PM PDT 24 6751018196 ps
T180 /workspace/coverage/default/4.chip_sw_uart_tx_rx.3369480371 Mar 12 04:06:52 PM PDT 24 Mar 12 04:19:34 PM PDT 24 5236922860 ps
T240 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.721254987 Mar 12 03:52:11 PM PDT 24 Mar 12 03:58:29 PM PDT 24 3460872029 ps
T114 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.629437511 Mar 12 04:13:32 PM PDT 24 Mar 12 04:19:19 PM PDT 24 3448960280 ps
T115 /workspace/coverage/default/74.chip_sw_all_escalation_resets.3120942438 Mar 12 04:15:06 PM PDT 24 Mar 12 04:24:01 PM PDT 24 5897964440 ps
T867 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3088403695 Mar 12 03:49:55 PM PDT 24 Mar 12 04:04:20 PM PDT 24 8295800749 ps
T868 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.3477176513 Mar 12 04:04:01 PM PDT 24 Mar 12 04:07:27 PM PDT 24 3286928211 ps
T869 /workspace/coverage/default/2.chip_sw_edn_kat.2285019555 Mar 12 04:01:46 PM PDT 24 Mar 12 04:14:24 PM PDT 24 3392012800 ps
T64 /workspace/coverage/default/4.chip_tap_straps_rma.1838112480 Mar 12 04:07:22 PM PDT 24 Mar 12 04:09:29 PM PDT 24 2207045807 ps
T870 /workspace/coverage/default/0.rom_e2e_asm_init_rma.2347602673 Mar 12 03:51:58 PM PDT 24 Mar 12 04:26:11 PM PDT 24 9264962649 ps
T288 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3731365106 Mar 12 04:01:12 PM PDT 24 Mar 12 04:12:24 PM PDT 24 3811417840 ps
T871 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3793794613 Mar 12 03:52:27 PM PDT 24 Mar 12 04:26:31 PM PDT 24 8857264920 ps
T872 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2559236177 Mar 12 04:01:43 PM PDT 24 Mar 12 04:07:30 PM PDT 24 2965235064 ps
T17 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1983850081 Mar 12 03:50:52 PM PDT 24 Mar 12 03:56:19 PM PDT 24 5128905736 ps
T659 /workspace/coverage/default/92.chip_sw_all_escalation_resets.4167285389 Mar 12 04:15:29 PM PDT 24 Mar 12 04:23:57 PM PDT 24 5558641524 ps
T873 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.954037195 Mar 12 03:49:47 PM PDT 24 Mar 12 03:56:51 PM PDT 24 3968235560 ps
T177 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2143004409 Mar 12 03:52:49 PM PDT 24 Mar 12 07:27:29 PM PDT 24 79677315630 ps
T664 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3593130543 Mar 12 04:07:45 PM PDT 24 Mar 12 04:14:07 PM PDT 24 3826901224 ps
T15 /workspace/coverage/default/2.chip_sw_gpio_smoketest.1188038346 Mar 12 04:05:21 PM PDT 24 Mar 12 04:11:07 PM PDT 24 2573655313 ps
T76 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.476639435 Mar 12 04:01:48 PM PDT 24 Mar 12 04:21:24 PM PDT 24 10151042976 ps
T169 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.648562914 Mar 12 03:57:24 PM PDT 24 Mar 12 04:07:23 PM PDT 24 4616106288 ps
T178 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2567605787 Mar 12 03:46:25 PM PDT 24 Mar 12 07:24:18 PM PDT 24 78528027880 ps
T356 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1808013165 Mar 12 03:50:36 PM PDT 24 Mar 12 04:15:58 PM PDT 24 10218355708 ps
T874 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.493679732 Mar 12 03:52:37 PM PDT 24 Mar 12 03:57:20 PM PDT 24 2397944129 ps
T313 /workspace/coverage/default/96.chip_sw_all_escalation_resets.1050229859 Mar 12 04:13:48 PM PDT 24 Mar 12 04:23:23 PM PDT 24 4968595956 ps
T77 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.2415505741 Mar 12 04:00:50 PM PDT 24 Mar 12 04:04:59 PM PDT 24 2903944462 ps
T875 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.193713978 Mar 12 03:51:33 PM PDT 24 Mar 12 04:21:42 PM PDT 24 8061492770 ps
T217 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3119650860 Mar 12 03:47:16 PM PDT 24 Mar 12 03:55:31 PM PDT 24 5431940234 ps
T33 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2725283580 Mar 12 03:44:14 PM PDT 24 Mar 12 03:48:25 PM PDT 24 2617235584 ps
T40 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3959131233 Mar 12 04:00:32 PM PDT 24 Mar 12 04:04:53 PM PDT 24 3354729738 ps
T202 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.699499438 Mar 12 04:00:37 PM PDT 24 Mar 12 05:22:42 PM PDT 24 45488275229 ps
T383 /workspace/coverage/default/26.chip_sw_all_escalation_resets.696875347 Mar 12 04:10:01 PM PDT 24 Mar 12 04:20:27 PM PDT 24 4830423528 ps
T170 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1071114872 Mar 12 03:51:18 PM PDT 24 Mar 12 04:02:03 PM PDT 24 4832949528 ps
T336 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1565972102 Mar 12 03:54:27 PM PDT 24 Mar 12 03:56:47 PM PDT 24 2753592170 ps
T384 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3877590818 Mar 12 03:48:35 PM PDT 24 Mar 12 03:58:48 PM PDT 24 4278995950 ps
T172 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3381306437 Mar 12 03:49:50 PM PDT 24 Mar 12 03:54:28 PM PDT 24 2809092079 ps
T385 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3849854263 Mar 12 04:04:00 PM PDT 24 Mar 12 04:22:06 PM PDT 24 5895471194 ps
T386 /workspace/coverage/default/84.chip_sw_all_escalation_resets.1049437846 Mar 12 04:12:57 PM PDT 24 Mar 12 04:20:46 PM PDT 24 4331851768 ps
T387 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3474789530 Mar 12 04:08:01 PM PDT 24 Mar 12 05:07:16 PM PDT 24 23309935094 ps
T707 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2072326254 Mar 12 04:13:07 PM PDT 24 Mar 12 04:19:54 PM PDT 24 3883690476 ps
T876 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1175906729 Mar 12 03:51:59 PM PDT 24 Mar 12 04:18:30 PM PDT 24 6275145115 ps
T298 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1860003618 Mar 12 03:46:05 PM PDT 24 Mar 12 04:00:00 PM PDT 24 4954879160 ps
T296 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3331303760 Mar 12 03:49:14 PM PDT 24 Mar 12 04:06:13 PM PDT 24 5511403009 ps
T877 /workspace/coverage/default/0.chip_sw_aon_timer_irq.1627354007 Mar 12 03:46:13 PM PDT 24 Mar 12 03:55:06 PM PDT 24 3339923800 ps
T291 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2511258158 Mar 12 03:44:50 PM PDT 24 Mar 12 04:01:43 PM PDT 24 5960720100 ps
T878 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2390886422 Mar 12 03:49:53 PM PDT 24 Mar 12 03:53:18 PM PDT 24 2394472760 ps
T719 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.745922730 Mar 12 04:12:52 PM PDT 24 Mar 12 04:18:40 PM PDT 24 3894707136 ps
T713 /workspace/coverage/default/53.chip_sw_all_escalation_resets.142654855 Mar 12 04:11:20 PM PDT 24 Mar 12 04:21:58 PM PDT 24 5833654816 ps
T712 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3668936803 Mar 12 04:15:01 PM PDT 24 Mar 12 04:21:59 PM PDT 24 4034619196 ps
T319 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3220216574 Mar 12 03:48:14 PM PDT 24 Mar 12 03:54:00 PM PDT 24 3039089220 ps
T406 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1004220850 Mar 12 03:51:12 PM PDT 24 Mar 12 03:54:43 PM PDT 24 2397600664 ps
T879 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2370008744 Mar 12 03:48:17 PM PDT 24 Mar 12 04:09:20 PM PDT 24 7664198424 ps
T113 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1731307519 Mar 12 03:50:46 PM PDT 24 Mar 12 06:49:42 PM PDT 24 255438845552 ps
T204 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1913994233 Mar 12 03:53:18 PM PDT 24 Mar 12 04:25:40 PM PDT 24 25071718881 ps
T105 /workspace/coverage/default/0.chip_sw_otbn_smoketest.3589482329 Mar 12 03:48:12 PM PDT 24 Mar 12 04:29:14 PM PDT 24 8992836840 ps
T880 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3162184641 Mar 12 04:02:52 PM PDT 24 Mar 12 04:06:33 PM PDT 24 3215067777 ps
T662 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.831779812 Mar 12 04:06:33 PM PDT 24 Mar 12 04:13:39 PM PDT 24 3918396544 ps
T881 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3253800727 Mar 12 04:06:14 PM PDT 24 Mar 12 04:49:08 PM PDT 24 13025246388 ps
T316 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.527350410 Mar 12 04:00:40 PM PDT 24 Mar 12 04:06:12 PM PDT 24 4028826478 ps
T882 /workspace/coverage/default/2.chip_sw_uart_smoketest.3147994452 Mar 12 04:05:23 PM PDT 24 Mar 12 04:09:47 PM PDT 24 3036867244 ps
T314 /workspace/coverage/default/33.chip_sw_all_escalation_resets.823115752 Mar 12 04:13:55 PM PDT 24 Mar 12 04:25:28 PM PDT 24 5687908858 ps
T883 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.1932998833 Mar 12 03:50:26 PM PDT 24 Mar 12 03:54:24 PM PDT 24 3064859024 ps
T330 /workspace/coverage/default/1.chip_sw_edn_boot_mode.1681440066 Mar 12 03:55:24 PM PDT 24 Mar 12 04:04:57 PM PDT 24 2607843210 ps
T884 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.657196198 Mar 12 03:53:41 PM PDT 24 Mar 12 04:25:11 PM PDT 24 6893739394 ps
T678 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.826229571 Mar 12 03:45:03 PM PDT 24 Mar 12 03:54:11 PM PDT 24 7076778900 ps
T709 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1212446703 Mar 12 04:11:01 PM PDT 24 Mar 12 04:16:12 PM PDT 24 3032538828 ps
T143 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1765523536 Mar 12 04:05:37 PM PDT 24 Mar 12 04:17:58 PM PDT 24 5239008646 ps
T229 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2356190256 Mar 12 03:52:17 PM PDT 24 Mar 12 04:00:27 PM PDT 24 5356354818 ps
T224 /workspace/coverage/default/2.chip_sw_plic_sw_irq.2574481737 Mar 12 04:03:45 PM PDT 24 Mar 12 04:07:41 PM PDT 24 2306075140 ps
T885 /workspace/coverage/default/3.chip_sw_uart_tx_rx.1683099358 Mar 12 04:07:12 PM PDT 24 Mar 12 04:21:40 PM PDT 24 4970868392 ps
T886 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.652206407 Mar 12 03:57:01 PM PDT 24 Mar 12 04:02:46 PM PDT 24 3294255292 ps
T123 /workspace/coverage/default/95.chip_sw_all_escalation_resets.3500561463 Mar 12 04:15:16 PM PDT 24 Mar 12 04:23:45 PM PDT 24 4926810320 ps
T355 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1729115564 Mar 12 03:46:22 PM PDT 24 Mar 12 03:50:28 PM PDT 24 2953762230 ps
T220 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3130348254 Mar 12 04:07:20 PM PDT 24 Mar 12 04:12:52 PM PDT 24 4428481804 ps
T333 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3284793703 Mar 12 03:53:25 PM PDT 24 Mar 12 04:38:09 PM PDT 24 12531212468 ps
T665 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3078991973 Mar 12 03:45:11 PM PDT 24 Mar 12 04:10:52 PM PDT 24 6524720432 ps
T134 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2359824542 Mar 12 04:03:38 PM PDT 24 Mar 12 04:07:22 PM PDT 24 2946322320 ps
T264 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.419093043 Mar 12 04:10:34 PM PDT 24 Mar 12 04:18:00 PM PDT 24 3936791498 ps
T265 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.812145396 Mar 12 04:05:31 PM PDT 24 Mar 12 04:19:53 PM PDT 24 5546074412 ps
T266 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.30958155 Mar 12 03:52:33 PM PDT 24 Mar 12 04:01:45 PM PDT 24 5455895048 ps
T267 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.483462458 Mar 12 04:07:40 PM PDT 24 Mar 12 04:42:46 PM PDT 24 14093542838 ps
T268 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1569125458 Mar 12 04:09:44 PM PDT 24 Mar 12 04:18:38 PM PDT 24 5261231841 ps
T163 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3231161465 Mar 12 03:45:48 PM PDT 24 Mar 12 03:54:35 PM PDT 24 7559748730 ps
T81 /workspace/coverage/default/64.chip_sw_all_escalation_resets.1870050423 Mar 12 04:12:53 PM PDT 24 Mar 12 04:21:57 PM PDT 24 5330163160 ps
T85 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1170329629 Mar 12 03:47:27 PM PDT 24 Mar 12 03:50:49 PM PDT 24 2059180354 ps
T86 /workspace/coverage/default/0.rom_e2e_smoke.1960833713 Mar 12 03:45:58 PM PDT 24 Mar 12 04:25:59 PM PDT 24 8498781208 ps
T87 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1663631640 Mar 12 03:45:01 PM PDT 24 Mar 12 04:13:11 PM PDT 24 12871043808 ps
T88 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3469342713 Mar 12 04:01:35 PM PDT 24 Mar 12 04:09:14 PM PDT 24 8127835626 ps
T89 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.4219153700 Mar 12 03:44:41 PM PDT 24 Mar 12 07:14:58 PM PDT 24 64817771456 ps
T90 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3558995184 Mar 12 03:48:47 PM PDT 24 Mar 12 04:01:54 PM PDT 24 4693285790 ps
T91 /workspace/coverage/default/0.chip_sw_plic_sw_irq.1057238580 Mar 12 03:46:33 PM PDT 24 Mar 12 03:52:30 PM PDT 24 3435095222 ps
T92 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1791582917 Mar 12 04:06:53 PM PDT 24 Mar 12 04:13:37 PM PDT 24 4023020072 ps
T93 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2917483163 Mar 12 04:09:42 PM PDT 24 Mar 12 04:29:32 PM PDT 24 6935140648 ps
T26 /workspace/coverage/default/0.chip_sw_gpio.1833040574 Mar 12 03:46:48 PM PDT 24 Mar 12 03:54:20 PM PDT 24 3890475720 ps
T18 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3008606465 Mar 12 03:52:51 PM PDT 24 Mar 12 04:00:14 PM PDT 24 7696535072 ps
T887 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.260486756 Mar 12 03:46:50 PM PDT 24 Mar 12 03:54:50 PM PDT 24 5020783308 ps
T741 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.4250932424 Mar 12 03:51:19 PM PDT 24 Mar 12 03:57:34 PM PDT 24 4073552440 ps
T226 /workspace/coverage/default/2.chip_sw_rv_timer_irq.935986944 Mar 12 04:01:04 PM PDT 24 Mar 12 04:05:38 PM PDT 24 3534357904 ps
T408 /workspace/coverage/default/1.chip_jtag_mem_access.2966423852 Mar 12 03:44:33 PM PDT 24 Mar 12 04:06:38 PM PDT 24 12920235836 ps
T19 /workspace/coverage/default/0.chip_sw_usbdev_pullup.3833131824 Mar 12 03:46:32 PM PDT 24 Mar 12 03:51:46 PM PDT 24 2895430440 ps
T888 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2284614073 Mar 12 04:03:13 PM PDT 24 Mar 12 04:25:37 PM PDT 24 6169707272 ps
T889 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.4231605596 Mar 12 03:47:01 PM PDT 24 Mar 12 03:55:51 PM PDT 24 5381948450 ps
T213 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2692868972 Mar 12 04:11:36 PM PDT 24 Mar 12 04:19:02 PM PDT 24 3026682290 ps
T41 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1596468961 Mar 12 03:54:32 PM PDT 24 Mar 12 04:25:36 PM PDT 24 19866338856 ps
T203 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2220250064 Mar 12 03:50:02 PM PDT 24 Mar 12 05:14:13 PM PDT 24 49748588230 ps
T890 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.4034835276 Mar 12 04:07:23 PM PDT 24 Mar 12 04:21:00 PM PDT 24 4971525016 ps
T891 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3008706285 Mar 12 03:58:24 PM PDT 24 Mar 12 04:12:36 PM PDT 24 5716497640 ps
T306 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3695333116 Mar 12 03:49:15 PM PDT 24 Mar 12 03:57:56 PM PDT 24 4057644972 ps
T310 /workspace/coverage/default/2.chip_sival_flash_info_access.770328110 Mar 12 03:58:27 PM PDT 24 Mar 12 04:05:21 PM PDT 24 3205909494 ps
T892 /workspace/coverage/default/0.chip_sw_kmac_idle.4182376115 Mar 12 03:46:57 PM PDT 24 Mar 12 03:52:32 PM PDT 24 3133406692 ps
T893 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1390009792 Mar 12 03:44:36 PM PDT 24 Mar 12 03:49:23 PM PDT 24 2773447109 ps
T742 /workspace/coverage/default/35.chip_sw_all_escalation_resets.2130736410 Mar 12 04:09:08 PM PDT 24 Mar 12 04:22:22 PM PDT 24 6212164424 ps
T894 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.477438868 Mar 12 04:08:28 PM PDT 24 Mar 12 04:16:15 PM PDT 24 7496298620 ps
T895 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.720193826 Mar 12 03:48:45 PM PDT 24 Mar 12 04:04:19 PM PDT 24 7339071884 ps
T44 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.3706483728 Mar 12 03:57:17 PM PDT 24 Mar 12 04:03:38 PM PDT 24 4522443294 ps
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