Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	149836	1			T69	5		T70	69		T73	44
values[2]	7280	1			T70	11		T74	2		T222	9
values[3]	3381	1			T70	1		T222	12		T388	9
values[4]	2005	1			T222	17		T388	7		T503	8
values[5]	1384	1			T222	6		T388	5		T503	14
values[6]	970	1			T222	3		T388	13		T503	11
values[7]	877	1			T222	17		T388	12		T503	5
values[8]	766	1			T222	3		T388	5		T503	6
values[9]	710	1			T222	11		T388	15		T503	5
values[10]	656	1			T222	10		T388	8		T503	9
values[11]	735	1			T222	26		T388	6		T503	16
values[12]	646	1			T222	3		T388	7		T503	7
values[13]	547	1			T222	12		T388	14		T503	12
values[14]	599	1			T222	6		T388	10		T503	8
values[15]	522	1			T222	6		T388	12		T503	9
values[16]	563	1			T222	16		T388	9		T503	5
values[17]	513	1			T222	6		T388	8		T503	5
values[18]	505	1			T222	6		T388	15		T503	6
values[19]	534	1			T222	10		T388	5		T503	4
values[20]	464	1			T222	9		T388	10		T503	3
values[21]	445	1			T222	6		T388	5		T503	5
values[22]	551	1			T222	12		T388	5		T503	5
values[23]	504	1			T222	17		T388	8		T503	5
values[24]	486	1			T222	6		T388	18		T503	5
values[25]	440	1			T222	11		T388	22		T503	10
values[26]	516	1			T222	9		T388	7		T503	11
values[27]	469	1			T388	9		T503	25		T792	3
values[28]	469	1			T388	6		T503	16		T792	1
values[29]	438	1			T388	8		T503	8		T792	2
values[30]	408	1			T388	3		T503	3		T792	3
values[31]	454	1			T388	15		T503	3		T792	2
values[32]	384	1			T388	8		T503	5		T792	3
values[33]	370	1			T388	18		T503	5		T792	1
values[34]	441	1			T388	5		T503	4		T792	6
values[35]	447	1			T388	11		T503	7		T792	4
values[36]	438	1			T388	6		T503	3		T792	5
values[37]	501	1			T388	10		T503	6		T792	7
values[38]	401	1			T388	6		T503	5		T792	8
values[39]	370	1			T388	12		T503	4		T792	5
values[40]	366	1			T388	9		T503	6		T792	4
values[41]	381	1			T388	6		T503	18		T792	6
values[42]	323	1			T388	12		T503	10		T792	2
values[43]	314	1			T388	11		T503	5		T792	2
values[44]	373	1			T388	12		T503	7		T792	1
values[45]	300	1			T388	14		T503	12		T792	2
values[46]	244	1			T503	9		T792	5		T800	1
values[47]	239	1			T503	6		T792	4		T800	2
values[48]	253	1			T503	4		T792	1		T800	1
values[49]	218	1			T503	4		T792	2		T800	1
values[50]	205	1			T503	10		T792	2		T800	1
values[51]	190	1			T503	15		T792	1		T800	1
values[52]	180	1			T503	17		T792	2		T800	1
values[53]	105	1			T503	11		T792	3		T800	1
values[54]	92	1			T503	6		T792	5		T800	1
values[55]	120	1			T503	13		T792	4		T800	1
values[56]	95	1			T503	6		T792	4		T800	1
values[57]	90	1			T503	17		T792	3		T800	1
values[58]	62	1			T503	9		T792	1		T800	1
values[59]	58	1			T503	4		T792	2		T800	1
values[60]	59	1			T503	8		T792	1		T800	1
values[61]	63	1			T503	6		T792	5		T800	1
values[62]	78	1			T503	13		T792	6		T800	1
values[63]	95	1			T503	14		T792	7		T800	1
values[64]	64	1			T503	8		T792	6		T800	1
values[65]	76	1			T503	8		T792	5		T800	1
values[66]	78	1			T503	9		T792	2		T800	1
values[67]	71	1			T503	7		T792	6		T800	1
values[68]	89	1			T503	12		T792	1		T800	1
values[69]	92	1			T503	6		T792	11		T800	1
values[70]	82	1			T503	7		T792	8		T800	1
values[71]	115	1			T503	20		T792	8		T800	1
values[72]	111	1			T503	17		T792	9		T800	1
values[73]	84	1			T503	11		T792	7		T800	1
values[74]	95	1			T503	7		T792	6		T800	1
values[75]	102	1			T503	7		T792	16		T800	1
values[76]	88	1			T503	10		T792	5		T800	1
values[77]	101	1			T503	6		T792	4		T800	1
values[78]	88	1			T503	5		T792	2		T800	1
values[79]	107	1			T503	6		T792	4		T800	1
values[80]	108	1			T503	7		T792	2		T800	1
values[81]	138	1			T503	22		T792	3		T800	1
values[82]	104	1			T503	16		T792	1		T800	1
values[83]	89	1			T503	6		T792	2		T800	1
values[84]	107	1			T503	11		T792	2		T800	1
values[85]	125	1			T503	16		T792	9		T800	1
values[86]	102	1			T503	5		T792	3		T800	1
values[87]	92	1			T503	11		T792	1		T800	1
values[88]	93	1			T503	12		T792	2		T800	1
values[89]	104	1			T503	11		T792	3		T800	1
values[90]	98	1			T503	14		T792	3		T800	1
values[91]	87	1			T503	12		T792	6		T800	1
values[92]	101	1			T503	13		T792	4		T800	1
values[93]	90	1			T503	9		T792	3		T800	1
values[94]	97	1			T503	5		T792	5		T800	1
values[95]	77	1			T503	7		T792	5		T800	1
values[96]	69	1			T503	7		T792	6		T800	1
values[97]	88	1			T503	13		T792	11		T800	1
values[98]	93	1			T503	16		T792	18		T800	1
values[99]	85	1			T503	4		T792	14		T800	1
values[100]	66	1			T503	2		T792	8		T800	1
values[101]	71	1			T503	2		T792	6		T800	1
values[102]	54	1			T503	2		T792	2		T800	1
values[103]	55	1			T503	1		T800	1		T787	1
values[104]	65	1			T503	2		T800	1		T787	1
values[105]	59	1			T503	2		T800	1		T787	1
values[106]	59	1			T503	17		T800	1		T787	1
values[107]	59	1			T503	12		T800	1		T787	1
values[108]	67	1			T503	7		T800	1		T787	1
values[109]	62	1			T503	7		T800	1		T787	1
values[110]	54	1			T503	6		T800	1		T787	1
values[111]	53	1			T503	8		T800	1		T787	1
values[112]	53	1			T503	6		T800	1		T787	1
values[113]	41	1			T503	3		T800	1		T787	1
values[114]	38	1			T503	2		T800	1		T787	1
values[115]	46	1			T503	4		T800	1		T787	1
values[116]	44	1			T503	4		T800	1		T787	1
values[117]	58	1			T503	5		T800	1		T787	1
values[118]	49	1			T503	5		T800	1		T787	1
values[119]	56	1			T503	5		T800	1		T787	1
values[120]	48	1			T503	3		T800	1		T787	1
values[121]	60	1			T503	7		T800	1		T787	1
values[122]	52	1			T503	4		T800	1		T787	1
values[123]	51	1			T503	2		T800	1		T787	1
values[124]	41	1			T503	6		T800	1		T787	1
values[125]	41	1			T503	8		T800	1		T787	2
values[126]	117	1			T503	10		T800	8		T787	3
values[127]	1431	1			T503	2		T800	72		T787	60
values[128]	6571	1			T800	335		T787	290		T810	314